From 8b926a3ba55b2e4adb8fcbac386809b86efc8ea1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 26 Sep 2018 06:37:51 +0100 Subject: [PATCH] comment why sv_insn_t is set up the way it is; add vector loop stub --- riscv/insn_template_sv.cc | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc index b83f877..c340142 100644 --- a/riscv/insn_template_sv.cc +++ b/riscv/insn_template_sv.cc @@ -4,11 +4,26 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc) { int xlen = ISASZ; reg_t npc = sext_xlen(pc + insn_length(INSNCODE)); + // messy way to do it: insn_t is used elsewhere in a union, + // so a workaround is to grab the bits from the insn_t + // and create an sv-variant. also an opportunity to pass + // in the loop index (voffs) which will be added on to + // any registers that are marked as "vectorised" insn_bits_t bits = s_insn.bits(); +#ifndef USING_NOREGS int voffs = 0; + int vlen = 1; sv_insn_t insn(bits, voffs); + bool vectorop = false; + for (; voffs < vlen; voffs++) + { + #include INCLUDEFILE + } +#else + insn_t insn(bits); #include INCLUDEFILE - trace_opcode(p, INSNCODE, s_insn); +#endif + trace_opcode(p, INSNCODE, insn); return npc; } -- 2.30.2