From 8b9aa16d2e7d00d49304fed13a0d4c4d80d5d1e2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 6 May 2020 16:16:41 +0200 Subject: [PATCH] boards/platforms: update xilinx programmers. --- litex/boards/platforms/arty.py | 2 +- litex/boards/platforms/genesys2.py | 2 +- litex/boards/platforms/kc705.py | 2 +- litex/boards/platforms/nexys4ddr.py | 2 +- litex/boards/platforms/nexys_video.py | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py index 712cd9ab..1f8101d4 100644 --- a/litex/boards/platforms/arty.py +++ b/litex/boards/platforms/arty.py @@ -259,7 +259,7 @@ class Platform(XilinxPlatform): def create_programmer(self): bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit" - return OpenOCD("openocd_xilinx_xc7.cfg", bscan_spi) + return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi) def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py index 7e5ebc43..7da31c87 100644 --- a/litex/boards/platforms/genesys2.py +++ b/litex/boards/platforms/genesys2.py @@ -117,7 +117,7 @@ class Platform(XilinxPlatform): XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado") def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit") + return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex/boards/platforms/kc705.py b/litex/boards/platforms/kc705.py index 394e5867..dcb0001e 100644 --- a/litex/boards/platforms/kc705.py +++ b/litex/boards/platforms/kc705.py @@ -549,7 +549,7 @@ set_property CONFIG_VOLTAGE 2.5 [current_design] self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit") + return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex/boards/platforms/nexys4ddr.py b/litex/boards/platforms/nexys4ddr.py index e112ca62..060caeb0 100644 --- a/litex/boards/platforms/nexys4ddr.py +++ b/litex/boards/platforms/nexys4ddr.py @@ -132,7 +132,7 @@ class Platform(XilinxPlatform): self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a100t.bit") + return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a100t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex/boards/platforms/nexys_video.py b/litex/boards/platforms/nexys_video.py index c8604e9f..6dbb9456 100644 --- a/litex/boards/platforms/nexys_video.py +++ b/litex/boards/platforms/nexys_video.py @@ -232,7 +232,7 @@ class Platform(XilinxPlatform): self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]") def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit") + return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a200t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) -- 2.30.2