From 8bd302d4376ce7859f617cc6fc528e4e454811aa Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 7 Aug 2023 16:04:00 -0700
Subject: [PATCH] split out instructions from openpower/isa/av.mdwn

---
 openpower/isa/av.mdwn              | 258 ++---------------------------
 openpower/isa/av/absdacs.mdwn      |  14 ++
 openpower/isa/av/absdacs_code.mdwn |   3 +
 openpower/isa/av/absdacu.mdwn      |  14 ++
 openpower/isa/av/absdacu_code.mdwn |   3 +
 openpower/isa/av/absds.mdwn        |  14 ++
 openpower/isa/av/absds_code.mdwn   |   2 +
 openpower/isa/av/absdu.mdwn        |  14 ++
 openpower/isa/av/absdu_code.mdwn   |   2 +
 openpower/isa/av/avgadd.mdwn       |  14 ++
 openpower/isa/av/avgadd_code.mdwn  |   6 +
 openpower/isa/av/bmask.mdwn        |  13 ++
 openpower/isa/av/bmask_code.mdwn   |  23 +++
 openpower/isa/av/cprop.mdwn        |  14 ++
 openpower/isa/av/cprop_code.mdwn   |   4 +
 openpower/isa/av/fishmv.mdwn       |  13 ++
 openpower/isa/av/fishmv_code.mdwn  |   3 +
 openpower/isa/av/fmvis.mdwn        |  13 ++
 openpower/isa/av/fmvis_code.mdwn   |   3 +
 openpower/isa/av/minmax..mdwn      |  13 ++
 openpower/isa/av/minmax._code.mdwn |  30 ++++
 openpower/isa/av/minmax.mdwn       |  13 ++
 openpower/isa/av/minmax_code.mdwn  |  30 ++++
 23 files changed, 269 insertions(+), 247 deletions(-)
 create mode 100644 openpower/isa/av/absdacs.mdwn
 create mode 100644 openpower/isa/av/absdacs_code.mdwn
 create mode 100644 openpower/isa/av/absdacu.mdwn
 create mode 100644 openpower/isa/av/absdacu_code.mdwn
 create mode 100644 openpower/isa/av/absds.mdwn
 create mode 100644 openpower/isa/av/absds_code.mdwn
 create mode 100644 openpower/isa/av/absdu.mdwn
 create mode 100644 openpower/isa/av/absdu_code.mdwn
 create mode 100644 openpower/isa/av/avgadd.mdwn
 create mode 100644 openpower/isa/av/avgadd_code.mdwn
 create mode 100644 openpower/isa/av/bmask.mdwn
 create mode 100644 openpower/isa/av/bmask_code.mdwn
 create mode 100644 openpower/isa/av/cprop.mdwn
 create mode 100644 openpower/isa/av/cprop_code.mdwn
 create mode 100644 openpower/isa/av/fishmv.mdwn
 create mode 100644 openpower/isa/av/fishmv_code.mdwn
 create mode 100644 openpower/isa/av/fmvis.mdwn
 create mode 100644 openpower/isa/av/fmvis_code.mdwn
 create mode 100644 openpower/isa/av/minmax..mdwn
 create mode 100644 openpower/isa/av/minmax._code.mdwn
 create mode 100644 openpower/isa/av/minmax.mdwn
 create mode 100644 openpower/isa/av/minmax_code.mdwn

diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn
index 94c3e1c8..22fac067 100644
--- a/openpower/isa/av.mdwn
+++ b/openpower/isa/av.mdwn
@@ -2,260 +2,24 @@
 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
 <!-- https://libre-soc.org/openpower/sv/av_opcodes/ -->
 
-# DRAFT Minimum/Maximum (Rc=1)
+[[!inline pagenames="openpower/isa/av/minmax." raw="yes"]]
 
-MM-Form
+[[!inline pagenames="openpower/isa/av/minmax" raw="yes"]]
 
-* minmax. RT,RA,RB,MMM (Rc=1)
+[[!inline pagenames="openpower/isa/av/avgadd" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/av/absds" raw="yes"]]
 
-    a <- (RA|0)
-    b <- (RB)
-    if MMM[0] then  # word mode
-        # shift left by XLEN/2 to make the dword comparison
-        # do word comparison of the original inputs
-        a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
-        b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
-    if MMM[1] then  # signed mode
-        # invert sign bits to make the unsigned comparison
-        # do signed comparison of the original inputs
-        a[0] <- ¬a[0]
-        b[0] <- ¬b[0]
-    # if Rc = 1 then store the result of comparing a and b to CR0
-    if Rc = 1 then
-        if a <u b then
-            CR0 <- 0b100 || XER[SO]
-        if a = b then
-            CR0 <- 0b001 || XER[SO]
-        if a >u b then
-            CR0 <- 0b010 || XER[SO]
-    if MMM[2] then  # max mode
-        # swap a and b to make the less than comparison do
-        # greater than comparison of the original inputs
-        t <- a
-        a <- b
-        b <- t
-    # store the entire selected source (even in word mode)
-    # if Rc = 1 then store the result of comparing a and b to CR0
-    if a <u b then RT <- (RA|0)
-    else RT <- (RB)
+[[!inline pagenames="openpower/isa/av/absdu" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/av/absdacu" raw="yes"]]
 
-    CR0                     (if Rc=1)
+[[!inline pagenames="openpower/isa/av/absdacs" raw="yes"]]
 
-# DRAFT Minimum/Maximum
+[[!inline pagenames="openpower/isa/av/cprop" raw="yes"]]
 
-MM-Form
+[[!inline pagenames="openpower/isa/av/bmask" raw="yes"]]
 
-* minmax RT,RA,RB,MMM (Rc=0)
+[[!inline pagenames="openpower/isa/av/fmvis" raw="yes"]]
 
-Pseudo-code:
-
-    a <- (RA|0)
-    b <- (RB)
-    if MMM[0] then  # word mode
-        # shift left by XLEN/2 to make the dword comparison
-        # do word comparison of the original inputs
-        a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
-        b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
-    if MMM[1] then  # signed mode
-        # invert sign bits to make the unsigned comparison
-        # do signed comparison of the original inputs
-        a[0] <- ¬a[0]
-        b[0] <- ¬b[0]
-    # if Rc = 1 then store the result of comparing a and b to CR0
-    # if Rc = 1 then
-    #     if a <u b then
-    #         CR0 <- 0b100 || XER[SO]
-    #     if a = b then
-    #         CR0 <- 0b001 || XER[SO]
-    #     if a >u b then
-    #         CR0 <- 0b010 || XER[SO]
-    if MMM[2] then  # max mode
-        # swap a and b to make the less than comparison do
-        # greater than comparison of the original inputs
-        t <- a
-        a <- b
-        b <- t
-    # store the entire selected source (even in word mode)
-    # if Rc = 1 then store the result of comparing a and b to CR0
-    if a <u b then RT <- (RA|0)
-    else RT <- (RB)
-
-Special Registers Altered:
-
-    None
-
-# DRAFT Average Add
-
-X-Form
-
-* avgadd  RT,RA,RB (Rc=0)
-* avgadd. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    a <- [0] * (XLEN+1)
-    b <- [0] * (XLEN+1)
-    a[1:XLEN] <- (RA)
-    b[1:XLEN] <- (RB)
-    r <- (a + b + 1)
-    RT <- r[0:XLEN-1]
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-
-# DRAFT Absolute Signed Difference
-
-X-Form
-
-* absds  RT,RA,RB (Rc=0)
-* absds. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    if (RA) < (RB) then RT <- ¬(RA) + (RB) + 1
-    else                RT <- ¬(RB) + (RA) + 1
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-
-# DRAFT Absolute Unsigned Difference
-
-X-Form
-
-* absdu  RT,RA,RB (Rc=0)
-* absdu. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    if (RA) <u (RB) then RT <- ¬(RA) + (RB) + 1
-    else                RT <- ¬(RB) + (RA) + 1
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-
-# DRAFT Absolute Accumulate Unsigned Difference
-
-X-Form
-
-* absdacu  RT,RA,RB (Rc=0)
-* absdacu. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    if (RA) <u (RB) then r <- ¬(RA) + (RB) + 1
-    else                 r <- ¬(RB) + (RA) + 1
-    RT <- (RT) + r
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-
-# DRAFT Absolute Accumulate Signed Difference
-
-X-Form
-
-* absdacs  RT,RA,RB (Rc=0)
-* absdacs. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    if (RA) < (RB) then r <- ¬(RA) + (RB) + 1
-    else                r <- ¬(RB) + (RA) + 1
-    RT <- (RT) + r
-
-Special Registers Altered:
-
-    CR0                     (if Rc=1)
-
-# Carry Propagate
-
-X-Form
-
-* cprop RT,RA,RB (Rc=0)
-* cprop. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
-    P <- (RA)
-    G <- (RB)
-    temp <- (P|G)+G
-    RT <- temp^P
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# DRAFT Bitmanip Masked
-
-BM2-Form
-
-* bmask  RT,RA,RB,bm,L
-
-Pseudo-code:
-
-    if _RB = 0 then mask <- [1] * XLEN
-    else mask <- (RB)
-    ra <- (RA) & mask
-    a1 <- ra
-    if bm[4] = 0 then a1 <- ¬ra
-    mode2 <- bm[2:3]
-    if mode2 = 0 then a2 <- (¬ra)+1
-    if mode2 = 1 then a2 <- ra-1
-    if mode2 = 2 then a2 <- ra+1
-    if mode2 = 3 then a2 <- ¬(ra+1)
-    a1 <- a1 & mask
-    a2 <- a2 & mask
-    # select operator
-    mode3 <- bm[0:1]
-    if mode3 = 0 then result <- a1 | a2
-    if mode3 = 1 then result <- a1 & a2
-    if mode3 = 2 then result <- a1 ^ a2
-    if mode3 = 3 then result <- undefined([0]*XLEN)
-    result <- result & mask
-    # optionally restore masked-out bits
-    if L = 1 then
-        result <- result | (RA & ¬mask)
-    RT <- result
-
-Special Registers Altered:
-
-    None
-
-# Load Floating-Point Immediate
-
-DX-Form
-
-* fmvis FRS,D
-
-Pseudo-code:
-
-    bf16 <- d0 || d1 || d2
-    fp32 <- bf16 || [0]*16
-    FRS  <- DOUBLE(fp32)
-
-Special Registers Altered:
-
-    None
-
-# Float Replace Lower-Half Single, Immediate
-
-DX-Form
-
-* fishmv FRS,D
-
-Pseudo-code:
-
-    fp32 <- SINGLE((FRS))
-    fp32[16:31] <- d0 || d1 || d2
-    FRS <- DOUBLE(fp32)
-
-Special Registers Altered:
-
-    None
+[[!inline pagenames="openpower/isa/av/fishmv" raw="yes"]]
diff --git a/openpower/isa/av/absdacs.mdwn b/openpower/isa/av/absdacs.mdwn
new file mode 100644
index 00000000..860e1f9c
--- /dev/null
+++ b/openpower/isa/av/absdacs.mdwn
@@ -0,0 +1,14 @@
+# DRAFT Absolute Accumulate Signed Difference
+
+X-Form
+
+* absdacs  RT,RA,RB (Rc=0)
+* absdacs. RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/av/absdacs_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
diff --git a/openpower/isa/av/absdacs_code.mdwn b/openpower/isa/av/absdacs_code.mdwn
new file mode 100644
index 00000000..5d0bc254
--- /dev/null
+++ b/openpower/isa/av/absdacs_code.mdwn
@@ -0,0 +1,3 @@
+    if (RA) < (RB) then r <- ¬(RA) + (RB) + 1
+    else                r <- ¬(RB) + (RA) + 1
+    RT <- (RT) + r
diff --git a/openpower/isa/av/absdacu.mdwn b/openpower/isa/av/absdacu.mdwn
new file mode 100644
index 00000000..49f21524
--- /dev/null
+++ b/openpower/isa/av/absdacu.mdwn
@@ -0,0 +1,14 @@
+# DRAFT Absolute Accumulate Unsigned Difference
+
+X-Form
+
+* absdacu  RT,RA,RB (Rc=0)
+* absdacu. RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/av/absdacu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
diff --git a/openpower/isa/av/absdacu_code.mdwn b/openpower/isa/av/absdacu_code.mdwn
new file mode 100644
index 00000000..48d9a1f6
--- /dev/null
+++ b/openpower/isa/av/absdacu_code.mdwn
@@ -0,0 +1,3 @@
+    if (RA) <u (RB) then r <- ¬(RA) + (RB) + 1
+    else                 r <- ¬(RB) + (RA) + 1
+    RT <- (RT) + r
diff --git a/openpower/isa/av/absds.mdwn b/openpower/isa/av/absds.mdwn
new file mode 100644
index 00000000..0453972b
--- /dev/null
+++ b/openpower/isa/av/absds.mdwn
@@ -0,0 +1,14 @@
+# DRAFT Absolute Signed Difference
+
+X-Form
+
+* absds  RT,RA,RB (Rc=0)
+* absds. RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/av/absds_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
diff --git a/openpower/isa/av/absds_code.mdwn b/openpower/isa/av/absds_code.mdwn
new file mode 100644
index 00000000..62bf78c7
--- /dev/null
+++ b/openpower/isa/av/absds_code.mdwn
@@ -0,0 +1,2 @@
+    if (RA) < (RB) then RT <- ¬(RA) + (RB) + 1
+    else                RT <- ¬(RB) + (RA) + 1
diff --git a/openpower/isa/av/absdu.mdwn b/openpower/isa/av/absdu.mdwn
new file mode 100644
index 00000000..38de7816
--- /dev/null
+++ b/openpower/isa/av/absdu.mdwn
@@ -0,0 +1,14 @@
+# DRAFT Absolute Unsigned Difference
+
+X-Form
+
+* absdu  RT,RA,RB (Rc=0)
+* absdu. RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/av/absdu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
diff --git a/openpower/isa/av/absdu_code.mdwn b/openpower/isa/av/absdu_code.mdwn
new file mode 100644
index 00000000..5b7a8aa5
--- /dev/null
+++ b/openpower/isa/av/absdu_code.mdwn
@@ -0,0 +1,2 @@
+    if (RA) <u (RB) then RT <- ¬(RA) + (RB) + 1
+    else                RT <- ¬(RB) + (RA) + 1
diff --git a/openpower/isa/av/avgadd.mdwn b/openpower/isa/av/avgadd.mdwn
new file mode 100644
index 00000000..cf626fd9
--- /dev/null
+++ b/openpower/isa/av/avgadd.mdwn
@@ -0,0 +1,14 @@
+# DRAFT Average Add
+
+X-Form
+
+* avgadd  RT,RA,RB (Rc=0)
+* avgadd. RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/av/avgadd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
diff --git a/openpower/isa/av/avgadd_code.mdwn b/openpower/isa/av/avgadd_code.mdwn
new file mode 100644
index 00000000..9f21faff
--- /dev/null
+++ b/openpower/isa/av/avgadd_code.mdwn
@@ -0,0 +1,6 @@
+    a <- [0] * (XLEN+1)
+    b <- [0] * (XLEN+1)
+    a[1:XLEN] <- (RA)
+    b[1:XLEN] <- (RB)
+    r <- (a + b + 1)
+    RT <- r[0:XLEN-1]
diff --git a/openpower/isa/av/bmask.mdwn b/openpower/isa/av/bmask.mdwn
new file mode 100644
index 00000000..c58e0ae9
--- /dev/null
+++ b/openpower/isa/av/bmask.mdwn
@@ -0,0 +1,13 @@
+# DRAFT Bitmanip Masked
+
+BM2-Form
+
+* bmask  RT,RA,RB,bm,L
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/av/bmask_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/av/bmask_code.mdwn b/openpower/isa/av/bmask_code.mdwn
new file mode 100644
index 00000000..51195c2f
--- /dev/null
+++ b/openpower/isa/av/bmask_code.mdwn
@@ -0,0 +1,23 @@
+    if _RB = 0 then mask <- [1] * XLEN
+    else mask <- (RB)
+    ra <- (RA) & mask
+    a1 <- ra
+    if bm[4] = 0 then a1 <- ¬ra
+    mode2 <- bm[2:3]
+    if mode2 = 0 then a2 <- (¬ra)+1
+    if mode2 = 1 then a2 <- ra-1
+    if mode2 = 2 then a2 <- ra+1
+    if mode2 = 3 then a2 <- ¬(ra+1)
+    a1 <- a1 & mask
+    a2 <- a2 & mask
+    # select operator
+    mode3 <- bm[0:1]
+    if mode3 = 0 then result <- a1 | a2
+    if mode3 = 1 then result <- a1 & a2
+    if mode3 = 2 then result <- a1 ^ a2
+    if mode3 = 3 then result <- undefined([0]*XLEN)
+    result <- result & mask
+    # optionally restore masked-out bits
+    if L = 1 then
+        result <- result | (RA & ¬mask)
+    RT <- result
diff --git a/openpower/isa/av/cprop.mdwn b/openpower/isa/av/cprop.mdwn
new file mode 100644
index 00000000..9bfc64d5
--- /dev/null
+++ b/openpower/isa/av/cprop.mdwn
@@ -0,0 +1,14 @@
+# Carry Propagate
+
+X-Form
+
+* cprop RT,RA,RB (Rc=0)
+* cprop. RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/av/cprop_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
diff --git a/openpower/isa/av/cprop_code.mdwn b/openpower/isa/av/cprop_code.mdwn
new file mode 100644
index 00000000..17d4e65f
--- /dev/null
+++ b/openpower/isa/av/cprop_code.mdwn
@@ -0,0 +1,4 @@
+    P <- (RA)
+    G <- (RB)
+    temp <- (P|G)+G
+    RT <- temp^P
diff --git a/openpower/isa/av/fishmv.mdwn b/openpower/isa/av/fishmv.mdwn
new file mode 100644
index 00000000..34af93ab
--- /dev/null
+++ b/openpower/isa/av/fishmv.mdwn
@@ -0,0 +1,13 @@
+# Float Replace Lower-Half Single, Immediate
+
+DX-Form
+
+* fishmv FRS,D
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/av/fishmv_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/av/fishmv_code.mdwn b/openpower/isa/av/fishmv_code.mdwn
new file mode 100644
index 00000000..1fdcbfa9
--- /dev/null
+++ b/openpower/isa/av/fishmv_code.mdwn
@@ -0,0 +1,3 @@
+    fp32 <- SINGLE((FRS))
+    fp32[16:31] <- d0 || d1 || d2
+    FRS <- DOUBLE(fp32)
diff --git a/openpower/isa/av/fmvis.mdwn b/openpower/isa/av/fmvis.mdwn
new file mode 100644
index 00000000..f77e37c1
--- /dev/null
+++ b/openpower/isa/av/fmvis.mdwn
@@ -0,0 +1,13 @@
+# Load Floating-Point Immediate
+
+DX-Form
+
+* fmvis FRS,D
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/av/fmvis_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/av/fmvis_code.mdwn b/openpower/isa/av/fmvis_code.mdwn
new file mode 100644
index 00000000..2c3f9f16
--- /dev/null
+++ b/openpower/isa/av/fmvis_code.mdwn
@@ -0,0 +1,3 @@
+    bf16 <- d0 || d1 || d2
+    fp32 <- bf16 || [0]*16
+    FRS  <- DOUBLE(fp32)
diff --git a/openpower/isa/av/minmax..mdwn b/openpower/isa/av/minmax..mdwn
new file mode 100644
index 00000000..d1e58ff0
--- /dev/null
+++ b/openpower/isa/av/minmax..mdwn
@@ -0,0 +1,13 @@
+# DRAFT Minimum/Maximum (Rc=1)
+
+MM-Form
+
+* minmax. RT,RA,RB,MMM (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/av/minmax._code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
diff --git a/openpower/isa/av/minmax._code.mdwn b/openpower/isa/av/minmax._code.mdwn
new file mode 100644
index 00000000..ac32d0ae
--- /dev/null
+++ b/openpower/isa/av/minmax._code.mdwn
@@ -0,0 +1,30 @@
+    a <- (RA|0)
+    b <- (RB)
+    if MMM[0] then  # word mode
+        # shift left by XLEN/2 to make the dword comparison
+        # do word comparison of the original inputs
+        a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
+        b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
+    if MMM[1] then  # signed mode
+        # invert sign bits to make the unsigned comparison
+        # do signed comparison of the original inputs
+        a[0] <- ¬a[0]
+        b[0] <- ¬b[0]
+    # if Rc = 1 then store the result of comparing a and b to CR0
+    if Rc = 1 then
+        if a <u b then
+            CR0 <- 0b100 || XER[SO]
+        if a = b then
+            CR0 <- 0b001 || XER[SO]
+        if a >u b then
+            CR0 <- 0b010 || XER[SO]
+    if MMM[2] then  # max mode
+        # swap a and b to make the less than comparison do
+        # greater than comparison of the original inputs
+        t <- a
+        a <- b
+        b <- t
+    # store the entire selected source (even in word mode)
+    # if Rc = 1 then store the result of comparing a and b to CR0
+    if a <u b then RT <- (RA|0)
+    else RT <- (RB)
diff --git a/openpower/isa/av/minmax.mdwn b/openpower/isa/av/minmax.mdwn
new file mode 100644
index 00000000..f9b7b6e9
--- /dev/null
+++ b/openpower/isa/av/minmax.mdwn
@@ -0,0 +1,13 @@
+# DRAFT Minimum/Maximum
+
+MM-Form
+
+* minmax RT,RA,RB,MMM (Rc=0)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/av/minmax_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/av/minmax_code.mdwn b/openpower/isa/av/minmax_code.mdwn
new file mode 100644
index 00000000..970dc054
--- /dev/null
+++ b/openpower/isa/av/minmax_code.mdwn
@@ -0,0 +1,30 @@
+    a <- (RA|0)
+    b <- (RB)
+    if MMM[0] then  # word mode
+        # shift left by XLEN/2 to make the dword comparison
+        # do word comparison of the original inputs
+        a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
+        b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
+    if MMM[1] then  # signed mode
+        # invert sign bits to make the unsigned comparison
+        # do signed comparison of the original inputs
+        a[0] <- ¬a[0]
+        b[0] <- ¬b[0]
+    # if Rc = 1 then store the result of comparing a and b to CR0
+    # if Rc = 1 then
+    #     if a <u b then
+    #         CR0 <- 0b100 || XER[SO]
+    #     if a = b then
+    #         CR0 <- 0b001 || XER[SO]
+    #     if a >u b then
+    #         CR0 <- 0b010 || XER[SO]
+    if MMM[2] then  # max mode
+        # swap a and b to make the less than comparison do
+        # greater than comparison of the original inputs
+        t <- a
+        a <- b
+        b <- t
+    # store the entire selected source (even in word mode)
+    # if Rc = 1 then store the result of comparing a and b to CR0
+    if a <u b then RT <- (RA|0)
+    else RT <- (RB)
-- 
2.30.2