From 8bf2d24abfb53704039c6a9964dda114b6b0d0f0 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 9 Dec 2020 00:41:21 +0000 Subject: [PATCH] --- openpower/sv/av_opcodes.mdwn | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/openpower/sv/av_opcodes.mdwn b/openpower/sv/av_opcodes.mdwn index 089644a8f..d3b7fef2f 100644 --- a/openpower/sv/av_opcodes.mdwn +++ b/openpower/sv/av_opcodes.mdwn @@ -78,3 +78,10 @@ signed and unsigned, 8/16/32: these are all of the form: result = (src1 > src2) ? src1 : src2 # max result = (src1 < src2) ? src1 : src2 # min +## vmerge operations + +these take two src vectors of various widths and splice them together. the best technique to cover these is a simple straightforward predicated pair of mv operations, inverting the predicate in the second case, or, alternately, to use a pair of vec2 (SUBVL=2) swizzled operations. + +in the swizzle case the first instruction would be destvect2.X = srcvec2.X and the second would swizzle-select Y. macro-op fusion in both the prefixated variant and the swizzle variant would interleave the two into the same SIMD backend ALUs. + +with twin predication the elwidth can be overridden on both src and dest such that either straight scalar mv or extsw/b/h can be used to provide the combinations of coverage needed, with only 2 actual instructions (plus vectir prefixing) -- 2.30.2