From 8c06a4fb63ed62579fe295fb9977e7ade31d5e8b Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 24 Sep 2022 11:47:32 +0100 Subject: [PATCH] --- openpower/sv/normal.mdwn | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn index 0f9a277e9..b41a0c1a7 100644 --- a/openpower/sv/normal.mdwn +++ b/openpower/sv/normal.mdwn @@ -64,7 +64,7 @@ Fields: * **RG** inverts the Vector Loop order (VL-1 downto 0) rather than the normal 0..VL-1 * **N** sets signed/unsigned saturation. -* **RC1** as if Rc=1, stores CRs *but not the result* +* **RC1** as if Rc=1, enables access to `VLi`. * **VLi** VL inclusive: in fail-first mode, the truncation of VL *includes* the current element at the failure point rather than excludes it from the count. @@ -180,6 +180,12 @@ and ffirst applied to the crop instead of to the arithmetic vector. Note that crops are covered by the [[sv/cr_ops]] Mode format. +*Programmer's note: `VLi` is only accessible in normal operations +which in turn limits the CR field bit-testing to only `EQ/NE`. +[[sv/cr_ops]] are not so limited. Thus it is possible to use for +example `sv.cror/ff=gt/vli *0,*0,*0`, which is not a `nop` because +it allows Fail-First Mode to perform a test and truncate VL.* + Two extremely important aspects of ffirst are: * LDST ffirst may never set VL equal to zero. This because on the first -- 2.30.2