From 8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b Mon Sep 17 00:00:00 2001
From: Nathan Binkert <nate@binkert.org>
Date: Tue, 19 Apr 2011 18:45:23 -0700
Subject: [PATCH] tests: update stats for name changes

---
 .../ref/alpha/tru64/inorder-timing/config.ini |    3 +
 .../ref/alpha/tru64/inorder-timing/simout     |    7 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |   94 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |    2 +
 .../00.gzip/ref/alpha/tru64/o3-timing/simout  |    6 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  336 ++---
 .../ref/alpha/tru64/simple-atomic/simout      |    7 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   10 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |    3 +
 .../ref/alpha/tru64/simple-timing/simout      |    7 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   18 +-
 .../ref/arm/linux/o3-timing/config.ini        |    2 +-
 .../00.gzip/ref/arm/linux/o3-timing/simout    |    8 +-
 .../00.gzip/ref/arm/linux/o3-timing/stats.txt |  334 ++---
 .../ref/arm/linux/simple-atomic/config.ini    |    4 +-
 .../ref/arm/linux/simple-atomic/simout        |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../ref/arm/linux/simple-timing/simout        |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   18 +-
 .../ref/sparc/linux/o3-timing/config.ini      |    2 +
 .../00.gzip/ref/sparc/linux/o3-timing/simout  |    6 +-
 .../ref/sparc/linux/o3-timing/stats.txt       |  330 ++---
 .../ref/sparc/linux/simple-atomic/simout      |    7 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   10 +-
 .../ref/sparc/linux/simple-timing/config.ini  |    3 +
 .../ref/sparc/linux/simple-timing/simout      |    7 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   18 +-
 .../ref/x86/linux/o3-timing/config.ini        |    2 +
 .../00.gzip/ref/x86/linux/o3-timing/simout    |    6 +-
 .../00.gzip/ref/x86/linux/o3-timing/stats.txt |  330 ++---
 .../ref/x86/linux/simple-atomic/simout        |    7 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/x86/linux/simple-timing/config.ini    |    3 +
 .../ref/x86/linux/simple-timing/simout        |    7 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   18 +-
 .../alpha/linux/tsunami-o3-dual/config.ini    |    4 +
 .../ref/alpha/linux/tsunami-o3-dual/simout    |    6 +-
 .../ref/alpha/linux/tsunami-o3-dual/stats.txt |  662 ++++-----
 .../ref/alpha/linux/tsunami-o3/config.ini     |    2 +
 .../ref/alpha/linux/tsunami-o3/simout         |    6 +-
 .../ref/alpha/linux/tsunami-o3/stats.txt      |  336 ++---
 .../ref/arm/linux/realview-o3/config.ini      |    4 +-
 .../ref/arm/linux/realview-o3/simout          |   10 +-
 .../ref/arm/linux/realview-o3/stats.txt       |  334 ++---
 .../ref/arm/linux/realview-o3/status          |    2 +-
 .../10.mcf/ref/arm/linux/o3-timing/config.ini |    4 +-
 .../10.mcf/ref/arm/linux/o3-timing/simout     |    8 +-
 .../10.mcf/ref/arm/linux/o3-timing/stats.txt  |  336 ++---
 .../ref/arm/linux/simple-atomic/config.ini    |    6 +-
 .../10.mcf/ref/arm/linux/simple-atomic/simout |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    6 +-
 .../10.mcf/ref/arm/linux/simple-timing/simout |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   18 +-
 .../ref/sparc/linux/simple-atomic/simout      |    7 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   10 +-
 .../ref/sparc/linux/simple-timing/config.ini  |    3 +
 .../ref/sparc/linux/simple-timing/simout      |    7 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   18 +-
 .../10.mcf/ref/x86/linux/o3-timing/config.ini |    2 +
 .../10.mcf/ref/x86/linux/o3-timing/simout     |    6 +-
 .../10.mcf/ref/x86/linux/o3-timing/stats.txt  |  330 ++---
 .../10.mcf/ref/x86/linux/simple-atomic/simout |    7 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/x86/linux/simple-timing/config.ini    |    3 +
 .../10.mcf/ref/x86/linux/simple-timing/simout |    7 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   18 +-
 .../ref/arm/linux/o3-timing/config.ini        |    4 +-
 .../20.parser/ref/arm/linux/o3-timing/simout  |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |  336 ++---
 .../ref/arm/linux/simple-atomic/config.ini    |    6 +-
 .../ref/arm/linux/simple-atomic/simout        |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    6 +-
 .../ref/arm/linux/simple-timing/simout        |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   18 +-
 .../ref/x86/linux/o3-timing/config.ini        |    2 +
 .../20.parser/ref/x86/linux/o3-timing/simout  |    6 +-
 .../ref/x86/linux/o3-timing/stats.txt         |  330 ++---
 .../ref/x86/linux/simple-atomic/config.ini    |    2 +-
 .../ref/x86/linux/simple-atomic/simout        |    9 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/x86/linux/simple-timing/config.ini    |    5 +-
 .../ref/x86/linux/simple-timing/simout        |    9 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   18 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |    2 +
 .../30.eon/ref/alpha/tru64/o3-timing/simout   |    6 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  336 ++---
 .../ref/alpha/tru64/simple-atomic/simout      |    7 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   10 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |    3 +
 .../ref/alpha/tru64/simple-timing/simout      |    7 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   18 +-
 .../30.eon/ref/arm/linux/o3-timing/config.ini |    2 +-
 .../30.eon/ref/arm/linux/o3-timing/simout     |    8 +-
 .../30.eon/ref/arm/linux/o3-timing/stats.txt  |  336 ++---
 .../ref/arm/linux/simple-atomic/config.ini    |    4 +-
 .../30.eon/ref/arm/linux/simple-atomic/simout |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../30.eon/ref/arm/linux/simple-timing/simout |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   18 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |    2 +
 .../ref/alpha/tru64/o3-timing/simout          |    6 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  336 ++---
 .../ref/alpha/tru64/simple-atomic/simout      |    7 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   10 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |    3 +
 .../ref/alpha/tru64/simple-timing/simout      |    7 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   18 +-
 .../ref/arm/linux/o3-timing/config.ini        |    2 +-
 .../40.perlbmk/ref/arm/linux/o3-timing/simout |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |  336 ++---
 .../ref/arm/linux/simple-atomic/config.ini    |    4 +-
 .../ref/arm/linux/simple-atomic/simout        |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../ref/arm/linux/simple-timing/simout        |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   18 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |    3 +
 .../ref/alpha/tru64/inorder-timing/simout     |    7 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |   94 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |    2 +
 .../ref/alpha/tru64/o3-timing/simout          |    6 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  336 ++---
 .../ref/alpha/tru64/simple-atomic/simout      |    7 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   10 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |    3 +
 .../ref/alpha/tru64/simple-timing/simout      |    7 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   18 +-
 .../ref/arm/linux/o3-timing/config.ini        |    2 +-
 .../50.vortex/ref/arm/linux/o3-timing/simout  |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |  336 ++---
 .../ref/arm/linux/simple-atomic/config.ini    |    4 +-
 .../ref/arm/linux/simple-atomic/simout        |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../ref/arm/linux/simple-timing/simout        |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   18 +-
 .../ref/sparc/linux/simple-atomic/simout      |    7 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   10 +-
 .../ref/sparc/linux/simple-timing/config.ini  |    3 +
 .../ref/sparc/linux/simple-timing/simout      |    7 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   18 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |    3 +
 .../ref/alpha/tru64/inorder-timing/simout     |    9 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |   94 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |    2 +
 .../60.bzip2/ref/alpha/tru64/o3-timing/simout |    6 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  336 ++---
 .../ref/alpha/tru64/simple-atomic/simout      |    7 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   10 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |    3 +
 .../ref/alpha/tru64/simple-timing/simout      |    7 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   18 +-
 .../ref/arm/linux/o3-timing/config.ini        |    2 +-
 .../60.bzip2/ref/arm/linux/o3-timing/simout   |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |  336 ++---
 .../ref/arm/linux/simple-atomic/config.ini    |    4 +-
 .../ref/arm/linux/simple-atomic/simout        |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../ref/arm/linux/simple-timing/simout        |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   18 +-
 .../ref/x86/linux/simple-atomic/simout        |    7 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/x86/linux/simple-timing/config.ini    |    3 +
 .../ref/x86/linux/simple-timing/simout        |    7 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   18 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |    3 +
 .../ref/alpha/tru64/inorder-timing/simout     |    7 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |   94 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |    2 +
 .../70.twolf/ref/alpha/tru64/o3-timing/simout |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  334 ++---
 .../ref/alpha/tru64/simple-atomic/simout      |    7 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   10 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |    3 +
 .../ref/alpha/tru64/simple-timing/simout      |    7 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   18 +-
 .../ref/arm/linux/o3-timing/config.ini        |    2 +-
 .../70.twolf/ref/arm/linux/o3-timing/simout   |   10 +-
 .../ref/arm/linux/o3-timing/stats.txt         |  334 ++---
 .../ref/arm/linux/simple-atomic/config.ini    |    4 +-
 .../ref/arm/linux/simple-atomic/simout        |   10 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../ref/arm/linux/simple-timing/simout        |   10 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   18 +-
 .../ref/sparc/linux/simple-atomic/simout      |    7 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   10 +-
 .../ref/sparc/linux/simple-timing/config.ini  |    3 +
 .../ref/sparc/linux/simple-timing/simout      |    7 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   18 +-
 .../ref/x86/linux/o3-timing/config.ini        |    2 +
 .../70.twolf/ref/x86/linux/o3-timing/simout   |    8 +-
 .../ref/x86/linux/o3-timing/stats.txt         |  328 ++---
 .../ref/x86/linux/simple-atomic/simout        |    9 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   10 +-
 .../ref/x86/linux/simple-timing/config.ini    |    3 +
 .../ref/x86/linux/simple-timing/simout        |    9 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   18 +-
 .../sparc/solaris/t1000-simple-atomic/simout  |    7 +-
 .../solaris/t1000-simple-atomic/stats.txt     |    8 +-
 .../ref/alpha/linux/inorder-timing/config.ini |    3 +
 .../ref/alpha/linux/inorder-timing/simout     |    7 +-
 .../ref/alpha/linux/inorder-timing/stats.txt  |   92 +-
 .../ref/alpha/linux/o3-timing/config.ini      |    2 +
 .../00.hello/ref/alpha/linux/o3-timing/simout |    6 +-
 .../ref/alpha/linux/o3-timing/stats.txt       |  332 ++---
 .../ref/alpha/linux/simple-atomic/simout      |    7 +-
 .../ref/alpha/linux/simple-atomic/stats.txt   |    8 +-
 .../config.ini                                |    3 +-
 .../ruby.stats                                |   32 +-
 .../simout                                    |    7 +-
 .../stats.txt                                 |   10 +-
 .../config.ini                                |    3 +-
 .../ruby.stats                                |  124 +-
 .../simout                                    |    7 +-
 .../stats.txt                                 |   10 +-
 .../config.ini                                |    2 +-
 .../ruby.stats                                |   18 +-
 .../simple-timing-ruby-MOESI_CMP_token/simout |    6 +-
 .../stats.txt                                 |   10 +-
 .../config.ini                                |    3 +-
 .../ruby.stats                                |  192 ++-
 .../simple-timing-ruby-MOESI_hammer/simout    |    7 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt |   10 +-
 .../alpha/linux/simple-timing-ruby/config.ini |    1 +
 .../alpha/linux/simple-timing-ruby/ruby.stats |   34 +-
 .../ref/alpha/linux/simple-timing-ruby/simout |    7 +-
 .../alpha/linux/simple-timing-ruby/stats.txt  |   10 +-
 .../ref/alpha/linux/simple-timing/config.ini  |    3 +
 .../ref/alpha/linux/simple-timing/simout      |    7 +-
 .../ref/alpha/linux/simple-timing/stats.txt   |   16 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |    2 +
 .../00.hello/ref/alpha/tru64/o3-timing/simout |    6 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  332 ++---
 .../ref/alpha/tru64/simple-atomic/simout      |    7 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |    8 +-
 .../config.ini                                |    3 +-
 .../ruby.stats                                |   24 +-
 .../simout                                    |    7 +-
 .../stats.txt                                 |   10 +-
 .../config.ini                                |    3 +-
 .../ruby.stats                                |  124 +-
 .../simout                                    |    7 +-
 .../stats.txt                                 |   10 +-
 .../config.ini                                |    2 +-
 .../ruby.stats                                |   26 +-
 .../simple-timing-ruby-MOESI_CMP_token/simout |    6 +-
 .../stats.txt                                 |   10 +-
 .../config.ini                                |    3 +-
 .../ruby.stats                                |  192 ++-
 .../simple-timing-ruby-MOESI_hammer/simout    |    7 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt |   10 +-
 .../alpha/tru64/simple-timing-ruby/config.ini |    1 +
 .../alpha/tru64/simple-timing-ruby/ruby.stats |   34 +-
 .../ref/alpha/tru64/simple-timing-ruby/simout |    7 +-
 .../alpha/tru64/simple-timing-ruby/stats.txt  |   10 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |    3 +
 .../ref/alpha/tru64/simple-timing/simout      |    7 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   14 +-
 .../ref/arm/linux/o3-timing/config.ini        |    2 +-
 .../00.hello/ref/arm/linux/o3-timing/simout   |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |  332 ++---
 .../ref/arm/linux/simple-atomic/config.ini    |    2 +-
 .../ref/arm/linux/simple-atomic/simout        |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |    8 +-
 .../ref/arm/linux/simple-timing/config.ini    |    2 +-
 .../ref/arm/linux/simple-timing/simout        |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   16 +-
 .../ref/mips/linux/inorder-timing/config.ini  |   57 +-
 .../ref/mips/linux/inorder-timing/simout      |    7 +-
 .../ref/mips/linux/inorder-timing/stats.txt   |   92 +-
 .../ref/mips/linux/o3-timing/config.ini       |   56 +-
 .../00.hello/ref/mips/linux/o3-timing/simout  |    6 +-
 .../ref/mips/linux/o3-timing/stats.txt        |  330 ++---
 .../ref/mips/linux/simple-atomic/config.ini   |   54 -
 .../ref/mips/linux/simple-atomic/simout       |    7 +-
 .../ref/mips/linux/simple-atomic/stats.txt    |   10 +-
 .../mips/linux/simple-timing-ruby/config.ini  |   55 +-
 .../ref/mips/linux/simple-timing-ruby/simout  |    7 +-
 .../mips/linux/simple-timing-ruby/stats.txt   |   10 +-
 .../ref/mips/linux/simple-timing/config.ini   |   57 +-
 .../ref/mips/linux/simple-timing/simout       |    7 +-
 .../ref/mips/linux/simple-timing/stats.txt    |   16 +-
 .../ref/power/linux/o3-timing/config.ini      |    2 +
 .../00.hello/ref/power/linux/o3-timing/simerr |    2 +-
 .../00.hello/ref/power/linux/o3-timing/simout |    6 +-
 .../ref/power/linux/o3-timing/stats.txt       |  332 ++---
 .../ref/power/linux/simple-atomic/simerr      |    2 +-
 .../ref/power/linux/simple-atomic/simout      |    7 +-
 .../ref/power/linux/simple-atomic/stats.txt   |   10 +-
 .../ref/sparc/linux/simple-atomic/simout      |    7 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   10 +-
 .../sparc/linux/simple-timing-ruby/config.ini |    1 +
 .../sparc/linux/simple-timing-ruby/ruby.stats |   38 +-
 .../ref/sparc/linux/simple-timing-ruby/simout |    7 +-
 .../sparc/linux/simple-timing-ruby/stats.txt  |   10 +-
 .../ref/sparc/linux/simple-timing/config.ini  |    3 +
 .../ref/sparc/linux/simple-timing/simout      |    7 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   16 +-
 .../ref/x86/linux/o3-timing/config.ini        |    2 +
 .../00.hello/ref/x86/linux/o3-timing/simout   |    6 +-
 .../ref/x86/linux/o3-timing/stats.txt         |  328 ++---
 .../ref/x86/linux/simple-atomic/simout        |    7 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |    8 +-
 .../x86/linux/simple-timing-ruby/config.ini   |    1 +
 .../x86/linux/simple-timing-ruby/ruby.stats   |   26 +-
 .../ref/x86/linux/simple-timing-ruby/simout   |    7 +-
 .../x86/linux/simple-timing-ruby/stats.txt    |   10 +-
 .../ref/x86/linux/simple-timing/config.ini    |    3 +
 .../ref/x86/linux/simple-timing/simout        |    7 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   16 +-
 .../ref/alpha/linux/o3-timing/config.ini      |    2 +
 .../ref/alpha/linux/o3-timing/simout          |    6 +-
 .../ref/alpha/linux/o3-timing/stats.txt       |  576 ++++----
 .../ref/sparc/linux/o3-timing/config.ini      |    2 +
 .../ref/sparc/linux/o3-timing/simout          |    6 +-
 .../ref/sparc/linux/o3-timing/stats.txt       |  322 ++---
 .../ref/sparc/linux/simple-atomic/simout      |    7 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   10 +-
 .../ref/sparc/linux/simple-timing/config.ini  |    3 +
 .../ref/sparc/linux/simple-timing/simout      |    7 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   16 +-
 .../tsunami-simple-atomic-dual/config.ini     |    6 +
 .../linux/tsunami-simple-atomic-dual/simout   |    7 +-
 .../tsunami-simple-atomic-dual/stats.txt      |   24 +-
 .../linux/tsunami-simple-atomic/config.ini    |    4 +
 .../alpha/linux/tsunami-simple-atomic/simout  |    7 +-
 .../linux/tsunami-simple-atomic/stats.txt     |   18 +-
 .../tsunami-simple-timing-dual/config.ini     |    6 +
 .../linux/tsunami-simple-timing-dual/simout   |    7 +-
 .../tsunami-simple-timing-dual/stats.txt      |   26 +-
 .../linux/tsunami-simple-timing/config.ini    |    4 +
 .../alpha/linux/tsunami-simple-timing/simout  |    7 +-
 .../linux/tsunami-simple-timing/stats.txt     |   18 +-
 .../linux/realview-simple-atomic/config.ini   |    4 +-
 .../arm/linux/realview-simple-atomic/simout   |   10 +-
 .../linux/realview-simple-atomic/stats.txt    |   16 +-
 .../arm/linux/realview-simple-atomic/status   |    2 +-
 .../linux/realview-simple-timing/config.ini   |    4 +-
 .../arm/linux/realview-simple-timing/simout   |   10 +-
 .../linux/realview-simple-timing/stats.txt    |   16 +-
 .../arm/linux/realview-simple-timing/status   |    2 +-
 .../ref/x86/linux/pc-simple-atomic/config.ini |    6 +
 .../ref/x86/linux/pc-simple-atomic/simout     |   10 +-
 .../ref/x86/linux/pc-simple-atomic/stats.txt  |   22 +-
 .../ref/x86/linux/pc-simple-timing/config.ini |    6 +
 .../ref/x86/linux/pc-simple-timing/simout     |   10 +-
 .../ref/x86/linux/pc-simple-timing/stats.txt  |   22 +-
 .../ref/alpha/eio/simple-atomic/simout        |    7 +-
 .../ref/alpha/eio/simple-atomic/stats.txt     |   10 +-
 .../ref/alpha/eio/simple-timing/config.ini    |    3 +
 .../ref/alpha/eio/simple-timing/simout        |    7 +-
 .../ref/alpha/eio/simple-timing/stats.txt     |   16 +-
 .../ref/alpha/eio/simple-atomic-mp/config.ini |    9 +
 .../ref/alpha/eio/simple-atomic-mp/simerr     |    5 +-
 .../ref/alpha/eio/simple-atomic-mp/simout     |    7 +-
 .../ref/alpha/eio/simple-atomic-mp/stats.txt  |   42 +-
 .../ref/alpha/eio/simple-timing-mp/config.ini |    9 +
 .../ref/alpha/eio/simple-timing-mp/simerr     |    4 +-
 .../ref/alpha/eio/simple-timing-mp/simout     |    7 +-
 .../ref/alpha/eio/simple-timing-mp/stats.txt  |   42 +-
 .../ref/sparc/linux/o3-timing-mp/config.ini   |    8 +
 .../ref/sparc/linux/o3-timing-mp/simout       |    6 +-
 .../ref/sparc/linux/o3-timing-mp/stats.txt    | 1276 ++++++++---------
 .../sparc/linux/simple-atomic-mp/config.ini   |    9 +
 .../ref/sparc/linux/simple-atomic-mp/simout   |    7 +-
 .../sparc/linux/simple-atomic-mp/stats.txt    |   36 +-
 .../sparc/linux/simple-timing-mp/config.ini   |    9 +
 .../ref/sparc/linux/simple-timing-mp/simout   |    7 +-
 .../sparc/linux/simple-timing-mp/stats.txt    |   42 +-
 .../config.ini                                |    8 +
 .../ruby.stats                                |   30 +-
 .../memtest-ruby-MESI_CMP_directory/simout    |    7 +-
 .../memtest-ruby-MESI_CMP_directory/stats.txt |    6 +-
 .../config.ini                                |    8 +
 .../ruby.stats                                |  122 +-
 .../memtest-ruby-MOESI_CMP_directory/simout   |    7 +-
 .../stats.txt                                 |    6 +-
 .../memtest-ruby-MOESI_CMP_token/ruby.stats   |   30 +-
 .../linux/memtest-ruby-MOESI_CMP_token/simout |    6 +-
 .../memtest-ruby-MOESI_CMP_token/stats.txt    |    6 +-
 .../memtest-ruby-MOESI_hammer/config.ini      |    8 +
 .../memtest-ruby-MOESI_hammer/ruby.stats      |  238 ++-
 .../linux/memtest-ruby-MOESI_hammer/simout    |    7 +-
 .../linux/memtest-ruby-MOESI_hammer/stats.txt |    6 +-
 .../ref/alpha/linux/memtest-ruby/config.ini   |   24 +-
 .../ref/alpha/linux/memtest-ruby/ruby.stats   |   46 +-
 .../ref/alpha/linux/memtest-ruby/simout       |    7 +-
 .../ref/alpha/linux/memtest-ruby/stats.txt    |    6 +-
 .../ref/alpha/linux/memtest/config.ini        |    9 +
 .../50.memtest/ref/alpha/linux/memtest/simout |    7 +-
 .../ref/alpha/linux/memtest/stats.txt         |   56 +-
 .../config.ini                                |    2 +
 .../ruby.stats                                |   24 +-
 .../rubytest-ruby-MESI_CMP_directory/simout   |    7 +-
 .../stats.txt                                 |    6 +-
 .../config.ini                                |    2 +
 .../ruby.stats                                |  124 +-
 .../rubytest-ruby-MOESI_CMP_directory/simout  |    7 +-
 .../stats.txt                                 |    6 +-
 .../rubytest-ruby-MOESI_CMP_token/config.ini  |    1 +
 .../rubytest-ruby-MOESI_CMP_token/ruby.stats  |   26 +-
 .../rubytest-ruby-MOESI_CMP_token/simout      |    6 +-
 .../rubytest-ruby-MOESI_CMP_token/stats.txt   |    6 +-
 .../rubytest-ruby-MOESI_hammer/config.ini     |    2 +
 .../rubytest-ruby-MOESI_hammer/ruby.stats     |  190 ++-
 .../linux/rubytest-ruby-MOESI_hammer/simout   |    7 +-
 .../rubytest-ruby-MOESI_hammer/stats.txt      |    6 +-
 .../ref/alpha/linux/rubytest-ruby/config.ini  |    2 +
 .../ref/alpha/linux/rubytest-ruby/ruby.stats  |   26 +-
 .../ref/alpha/linux/rubytest-ruby/simout      |    7 +-
 .../ref/alpha/linux/rubytest-ruby/stats.txt   |    6 +-
 .../twosys-tsunami-simple-atomic/config.ini   |    4 +-
 .../linux/twosys-tsunami-simple-atomic/simout |    7 +-
 .../twosys-tsunami-simple-atomic/stats.txt    |   14 +-
 420 files changed, 9084 insertions(+), 8183 deletions(-)

diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
index 85d434144..23a53cd4f 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
@@ -86,6 +86,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +122,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -156,6 +158,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
index 8f9b1263d..ff066f3a4 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 23 2011 05:47:47
-M5 revision Unknown
-M5 started Feb 23 2011 05:49:05
-M5 executing on m55-001.pool
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:24
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
index 97f36d33a..74577bc37 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,37 +1,25 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 145740                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 390376                       # Number of bytes of host memory used
-host_seconds                                  4129.65                       # Real time elapsed on the host
-host_tick_rate                               63356930                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 209357                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 403360                       # Number of bytes of host memory used
+host_seconds                                  2874.78                       # Real time elapsed on the host
+host_tick_rate                               91012809                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_seconds                                  0.261642                       # Number of seconds simulated
 sim_ticks                                261641972500                       # Number of ticks simulated
-system.cpu.AGEN-Unit.agens                  155868116                       # Number of Address Generations
-system.cpu.Branch-Predictor.BTBHitPct       90.344266                       # BTB Hit Percentage
-system.cpu.Branch-Predictor.BTBHits          29143677                       # Number of BTB hits
-system.cpu.Branch-Predictor.BTBLookups       32258469                       # Number of BTB lookups
-system.cpu.Branch-Predictor.RASInCorrect            6                       # Number of incorrect RAS predictions.
-system.cpu.Branch-Predictor.condIncorrect     22153653                       # Number of conditional branches incorrect
-system.cpu.Branch-Predictor.condPredicted     59309256                       # Number of conditional branches predicted
-system.cpu.Branch-Predictor.lookups          64114012                       # Number of BP lookups
-system.cpu.Branch-Predictor.predictedNotTaken     31921338                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken     32192674                       # Number of Branches Predicted As Taken (True).
-system.cpu.Branch-Predictor.usedRAS           1197609                       # Number of times the RAS was used to get a target.
-system.cpu.Execution-Unit.executions        419011350                       # Number of Instructions Executed.
-system.cpu.Execution-Unit.mispredictPct     35.419120                       # Percentage of Incorrect Branches Predicts
-system.cpu.Execution-Unit.mispredicted       22153653                       # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predicted          40393506                       # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predictedNotTakenIncorrect     19275234                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.Execution-Unit.predictedTakenIncorrect      2878419                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.Mult-Div-Unit.divides                    0                       # Number of Divide Operations Executed
-system.cpu.Mult-Div-Unit.multiplies              6482                       # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses   1022190210                       # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads     558335321                       # Number of Reads from Register File
-system.cpu.RegFile-Manager.regFileWrites    463854889                       # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards      256259728                       # Number of Registers Read Through Forwarding Logic
 system.cpu.activity                         88.058146                       # Percentage of cycles cpu is active
+system.cpu.agen_unit.agens                  155868116                       # Number of Address Generations
+system.cpu.branch_predictor.BTBHitPct       90.344266                       # BTB Hit Percentage
+system.cpu.branch_predictor.BTBHits          29143677                       # Number of BTB hits
+system.cpu.branch_predictor.BTBLookups       32258469                       # Number of BTB lookups
+system.cpu.branch_predictor.RASInCorrect            6                       # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.condIncorrect     22153653                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.condPredicted     59309256                       # Number of conditional branches predicted
+system.cpu.branch_predictor.lookups          64114012                       # Number of BP lookups
+system.cpu.branch_predictor.predictedNotTaken     31921338                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.branch_predictor.predictedTaken     32192674                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.usedRAS           1197609                       # Number of times the RAS was used to get a target.
 system.cpu.comBranches                       62547159                       # Number of Branches instructions committed
 system.cpu.comFloats                               24                       # Number of Floating Point instructions committed
 system.cpu.comInts                          349039879                       # Number of Integer instructions committed
@@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses           455395                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.998946                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4091.682212                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.998946                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          153965363                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 21854.685324                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 19449.234181                       # average overall mshr miss latency
@@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses                39453623                       # DT
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_hits                    39451321                       # DTB write hits
 system.cpu.dtb.write_misses                      2302                       # DTB write misses
+system.cpu.execution_unit.executions        419011350                       # Number of Instructions Executed.
+system.cpu.execution_unit.mispredictPct     35.419120                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.mispredicted       22153653                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted          40393506                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predictedNotTakenIncorrect     19275234                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.predictedTakenIncorrect      2878419                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.icache.ReadReq_accesses           25645163                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 55761.178862                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 53508.177570                       # average ReadReq mshr miss latency
@@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses              856                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.355592                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            728.253324                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.355592                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           25645163                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55761.178862                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 53508.177570                       # average overall mshr miss latency
@@ -246,10 +240,10 @@ system.cpu.l2cache.demand_mshr_misses           92098                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.050363                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.487947                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          1650.286010                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         15989.036396                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.050363                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.487947                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            456251                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 52157.973029                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 40004.212904                       # average overall mshr miss latency
@@ -271,31 +265,37 @@ system.cpu.l2cache.tagsinuse             17639.322406                       # Cy
 system.cpu.l2cache.total_refs                  445702                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                   59346                       # number of writebacks
+system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.mult_div_unit.multiplies              6482                       # Number of Multipy Operations Executed
 system.cpu.numCycles                        523283946                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.regfile_manager.regFileAccesses   1022190210                       # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.regfile_manager.regFileReads     558335321                       # Number of Reads from Register File
+system.cpu.regfile_manager.regFileWrites    463854889                       # Number of Writes to Register File
+system.cpu.regfile_manager.regForwards      256259728                       # Number of Registers Read Through Forwarding Logic
 system.cpu.runCycles                        460794140                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles               186436323                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-0.runCycles                336847623                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization              64.371863                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles               209154116                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles                314129830                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization              60.030473                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles               197582511                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-2.runCycles                325701435                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization              62.241817                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles               410314498                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-3.runCycles                112969448                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization              21.588556                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles               180086100                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-4.runCycles                343197846                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization              65.585396                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage0.idleCycles                186436323                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                 336847623                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               64.371863                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                209154116                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                 314129830                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               60.030473                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                197582511                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                 325701435                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               62.241817                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                410314498                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                 112969448                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               21.588556                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                180086100                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                 343197846                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               65.585396                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.threadCycles                     508404874                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.timesIdled                          455729                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index 8d44452f2..2c97093b4 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
index 6c138b362..10e34acb3 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 21:44:37
-M5 started Mar 17 2011 22:44:08
-M5 executing on zizzer
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:05:54
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index 93acfbb63..bb82434d0 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 243015                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 208616                       # Number of bytes of host memory used
-host_seconds                                  2327.23                       # Real time elapsed on the host
-host_tick_rate                               69757618                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 385051                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204468                       # Number of bytes of host memory used
+host_seconds                                  1468.77                       # Real time elapsed on the host
+host_tick_rate                              110529153                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   565552443                       # Number of instructions simulated
 sim_seconds                                  0.162342                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect            4119052                       # Nu
 system.cpu.BPredUnit.condPredicted           70244988                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                 76158972                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                  1672188                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               62547159                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          20370282                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    315015358                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.910564                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     2.344745                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    102187516     32.44%     32.44% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    100337503     31.85%     64.29% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     36333939     11.53%     75.82% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      9834278      3.12%     78.95% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      9585018      3.04%     81.99% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5     21675104      6.88%     88.87% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6     13171126      4.18%     93.05% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      1520592      0.48%     93.53% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     20370282      6.47%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    315015358                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                 601856963                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                   1520                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls          1197610                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts             563954763                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                 114514042                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  153965363                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts           4118243                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                   62547159                       # Number of branches committed
+system.cpu.commit.bw_lim_events              20370282                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts      601856963                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts        59876142                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples    315015358                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.910564                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.344745                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    102187516     32.44%     32.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    100337503     31.85%     64.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     36333939     11.53%     75.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9834278      3.12%     78.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      9585018      3.04%     81.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     21675104      6.88%     88.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     13171126      4.18%     93.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1520592      0.48%     93.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     20370282      6.47%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    315015358                       # Number of insts commited each cycle
+system.cpu.commit.count                     601856963                       # Number of instructions committed
+system.cpu.commit.fp_insts                       1520                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls              1197610                       # Number of function calls committed.
+system.cpu.commit.int_insts                 563954763                       # Number of committed integer instructions.
+system.cpu.commit.loads                     114514042                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                      153965363                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                   565552443                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             565552443                       # Number of Instructions Simulated
 system.cpu.cpi                               0.574101                       # CPI: Cycles Per Instruction
@@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses           475134                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999549                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4094.151824                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999549                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          151655852                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 14624.181040                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  9493.104038                       # average overall mshr miss latency
@@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse               4094.151824                       # Cy
 system.cpu.dcache.total_refs                149582206                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              126677000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   423176                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       44833716                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred            844                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved       4163323                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts       687863087                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         142213399                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          122593858                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         9601978                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts           3402                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles        5374385                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles              44833716                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                   844                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved              4163323                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts              687863087                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                142213399                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                 122593858                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                9601978                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                  3402                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles               5374385                       # Number of cycles decode is unblocking
 system.cpu.dtb.data_accesses                163150258                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                    163097305                       # DTB hits
@@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses              909                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.378270                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            774.695980                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.378270                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           65447834                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 36501.303215                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 35511.551155                       # average overall mshr miss latency
@@ -233,21 +233,13 @@ system.cpu.icache.total_refs                 65446683                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                           67100                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 67449018                       # Number of branches executed
-system.cpu.iew.EXEC:nop                      43212719                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.845435                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    163178153                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   40932468                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 486897348                       # num instructions consuming a value
-system.cpu.iew.WB:count                     595948678                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.812979                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                 395837342                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.835470                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      597097102                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts              4605504                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                 67449018                       # Number of branches executed
+system.cpu.iew.exec_nop                      43212719                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.845435                       # Inst execution rate
+system.cpu.iew.exec_refs                    163178153                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                   40932468                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                 1354512                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts             125962189                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                 25                       # Number of dispatched non-speculative instructions
@@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores      3134413                       #
 system.cpu.iew.memOrderViolationEvents          24101                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       952315                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        3653189                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                 486897348                       # num instructions consuming a value
+system.cpu.iew.wb_count                     595948678                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.812979                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                 395837342                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.835470                       # insts written-back per cycle
+system.cpu.iew.wb_sent                      597097102                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                844972523                       # number of integer regfile reads
 system.cpu.int_regfile_writes               489243634                       # number of integer regfile writes
 system.cpu.ipc                               1.741853                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.741853                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       439577743     72.58%     72.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult           6656      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd            30      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             5      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             5      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            4      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     72.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      124281005     20.52%     93.11% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      41743673      6.89%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        605609121                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               5929666                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.009791                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu           5228922     88.18%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult               48      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     88.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead           403247      6.80%     94.98% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          297449      5.02%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    324617336                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.865609                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.727719                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      90473429     27.87%     27.87% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      62743019     19.33%     47.20% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      78570143     24.20%     71.40% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3      32526937     10.02%     81.42% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      31455135      9.69%     91.11% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      13029774      4.01%     95.13% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6      14124566      4.35%     99.48% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       1126465      0.35%     99.83% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        567868      0.17%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    324617336                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.865224                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             439577743     72.58%     72.58% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 6656      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  30      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   5      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   5      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     72.59% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            124281005     20.52%     93.11% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            41743673      6.89%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              605609121                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                    1669                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                3317                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses         1594                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes               1802                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                     5929666                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009791                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 5228922     88.18%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     48      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     88.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 403247      6.80%     94.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                297449      5.02%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses              611537118                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads         1541773318                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses    595947084                       # Number of integer instruction queue wakeup accesses
@@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined        51673321                       # Nu
 system.cpu.iq.iqSquashedInstsIssued             11391                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved              8                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined     26894119                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples     324617336                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.865609                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.727719                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            90473429     27.87%     27.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            62743019     19.33%     47.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            78570143     24.20%     71.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            32526937     10.02%     81.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            31455135      9.69%     91.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            13029774      4.01%     95.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            14124566      4.35%     99.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1126465      0.35%     99.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              567868      0.17%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       324617336                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.865224                       # Inst issue rate
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
@@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses           92757                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.052925                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.487884                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          1734.245593                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         15986.969370                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.052925                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.487884                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            476043                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34447.863773                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31236.300225                       # average overall mshr miss latency
@@ -477,28 +477,28 @@ system.cpu.misc_regfile_writes                      1                       # nu
 system.cpu.numCycles                        324684436                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         12564419                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps      463854889                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents        31522766                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         149604933                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents         659383                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents            101                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups      894089158                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       678776451                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    517767610                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          115293181                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         9601978                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       37552130                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          53912721                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups         1965                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups    894087193                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles          695                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts           31                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           73444449                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts           30                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                12564419                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps             463854889                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents               31522766                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                149604933                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents                659383                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                   101                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups             894089158                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts              678776451                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands           517767610                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                 115293181                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                9601978                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles              37552130                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                 53912721                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups              1965                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups        894087193                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles            695                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts                 31                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                  73444449                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts             30                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                    956313792                       # The number of ROB reads
 system.cpu.rob.rob_writes                  1333072216                       # The number of ROB writes
 system.cpu.timesIdled                            2037                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
index b96d561c3..87e51a8e2 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:37
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:35
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
index 4dfa82a45..fdb2e2919 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1697811                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 218112                       # Number of bytes of host memory used
-host_seconds                                   354.49                       # Real time elapsed on the host
-host_tick_rate                              848911876                       # Simulator tick rate (ticks/s)
+host_inst_rate                                6401056                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195828                       # Number of bytes of host memory used
+host_seconds                                    94.02                       # Real time elapsed on the host
+host_tick_rate                             3200547989                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_seconds                                  0.300931                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes          463854847                       # nu
 system.cpu.num_load_insts                   114516673                       # Number of load instructions
 system.cpu.num_mem_refs                     153970296                       # number of memory refs
 system.cpu.num_store_insts                   39453623                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 5dbdc6426..50ef6266f 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
index 5133de4f2..dc72f58cf 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:36
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:24
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
index 0f44a109b..f9d483c5d 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 591495                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 225828                       # Number of bytes of host memory used
-host_seconds                                  1017.52                       # Real time elapsed on the host
-host_tick_rate                              752441266                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2829112                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203572                       # Number of bytes of host memory used
+host_seconds                                   212.74                       # Real time elapsed on the host
+host_tick_rate                             3598913072                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_seconds                                  0.765623                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses           455395                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999553                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4094.170317                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999553                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          153965363                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 22414.479737                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737                       # average overall mshr miss latency
@@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses              795                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.328778                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            673.337154                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.328778                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          601861898                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses           92031                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.052565                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.491366                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          1722.436058                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         16101.078831                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.052565                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.491366                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            456190                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -250,6 +250,6 @@ system.cpu.num_int_register_writes          463854847                       # nu
 system.cpu.num_load_insts                   114516673                       # Number of load instructions
 system.cpu.num_mem_refs                     153970296                       # number of memory refs
 system.cpu.num_store_insts                   39453623                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
index d12448d3c..07f2d92be 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
@@ -498,7 +498,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/gzip
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
index 0ab77604f..facf2b9b0 100755
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 17:54:33
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 12:47:12
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
index a5940d4c5..5fb65989e 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 238408                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 258640                       # Number of bytes of host memory used
-host_seconds                                  2526.59                       # Real time elapsed on the host
-host_tick_rate                               77778012                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 283332                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214996                       # Number of bytes of host memory used
+host_seconds                                  2125.99                       # Real time elapsed on the host
+host_tick_rate                               92433779                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   602359865                       # Number of instructions simulated
 sim_seconds                                  0.196513                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect            3832102                       # Nu
 system.cpu.BPredUnit.condPredicted           81880205                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                 88398894                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                  1393010                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               70828614                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           7897771                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    379244728                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.588315                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.904338                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    123478650     32.56%     32.56% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    123013107     32.44%     65.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     59170888     15.60%     80.60% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     18488020      4.87%     85.47% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     17225820      4.54%     90.01% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5     14373715      3.79%     93.80% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6      7590349      2.00%     95.81% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      8006408      2.11%     97.92% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      7897771      2.08%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    379244728                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                 602359916                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                     16                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls           997573                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts             533522691                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                 148952607                       # Number of loads committed
-system.cpu.commit.COM:membars                    1328                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  219173633                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts           3891220                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                   70828614                       # Number of branches committed
+system.cpu.commit.bw_lim_events               7897771                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts      602359916                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls            6310                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts        86859726                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples    379244728                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.588315                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.904338                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    123478650     32.56%     32.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    123013107     32.44%     65.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     59170888     15.60%     80.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     18488020      4.87%     85.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     17225820      4.54%     90.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14373715      3.79%     93.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7590349      2.00%     95.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      8006408      2.11%     97.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      7897771      2.08%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    379244728                       # Number of insts commited each cycle
+system.cpu.commit.count                     602359916                       # Number of instructions committed
+system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls               997573                       # Number of function calls committed.
+system.cpu.commit.int_insts                 533522691                       # Number of committed integer instructions.
+system.cpu.commit.loads                     148952607                       # Number of loads committed
+system.cpu.commit.membars                        1328                       # Number of memory barriers committed
+system.cpu.commit.refs                      219173633                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                   602359865                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             602359865                       # Number of Instructions Simulated
 system.cpu.cpi                               0.652478                       # CPI: Cycles Per Instruction
@@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses           443820                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999719                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4094.849519                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999719                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          208812765                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 17229.974009                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  9270.687452                       # average overall mshr miss latency
@@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse               4094.849519                       # Cy
 system.cpu.dcache.total_refs                207082021                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               89315000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   394264                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       64227537                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred           1274                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved       5983982                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts       722350979                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         163737957                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          138388023                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        12871984                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts           4747                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles       12891210                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles              64227537                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                  1274                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved              5983982                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts              722350979                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                163737957                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                 138388023                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles               12871984                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                  4747                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles              12891210                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -220,8 +220,8 @@ system.cpu.icache.demand_mshr_misses              722                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.307172                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            629.087764                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.307172                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           71395519                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 35429.359823                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 34341.412742                       # average overall mshr miss latency
@@ -244,21 +244,13 @@ system.cpu.icache.total_refs                 71394613                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                          909571                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 73704412                       # Number of branches executed
-system.cpu.iew.EXEC:nop                         61098                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.622472                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    239165331                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   73423365                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 736448308                       # num instructions consuming a value
-system.cpu.iew.WB:count                     631945179                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.594878                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                 438096934                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.607895                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      632881856                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts              4305441                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                 73704412                       # Number of branches executed
+system.cpu.iew.exec_nop                         61098                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.622472                       # Inst execution rate
+system.cpu.iew.exec_refs                    239165331                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                   73423365                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                  811047                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts             176106355                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts               5819                       # Number of dispatched non-speculative instructions
@@ -286,103 +278,93 @@ system.cpu.iew.lsq.thread.0.squashedStores     11966835                       #
 system.cpu.iew.memOrderViolationEvents         611520                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       628522                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        3676919                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                 736448308                       # num instructions consuming a value
+system.cpu.iew.wb_count                     631945179                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.594878                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                 438096934                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.607895                       # insts written-back per cycle
+system.cpu.iew.wb_sent                      632881856                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads               1724767298                       # number of integer regfile reads
 system.cpu.int_regfile_writes               495432851                       # number of integer regfile writes
 system.cpu.ipc                               1.532620                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.532620                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       400863775     62.26%     62.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult           6585      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            3      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     62.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      168265891     26.14%     88.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      74671891     11.60%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        643808145                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               3945011                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.006128                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu            107679      2.73%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      2.73% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          3407280     86.37%     89.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          430052     10.90%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    392116711                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.641879                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.551770                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     108904518     27.77%     27.77% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     107421508     27.40%     55.17% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      76290088     19.46%     74.62% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3      48454562     12.36%     86.98% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      26882762      6.86%     93.84% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      16851716      4.30%     98.14% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       5414053      1.38%     99.52% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       1011203      0.26%     99.77% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        886301      0.23%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    392116711                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.638079                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             400863775     62.26%     62.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 6585      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.27% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            168265891     26.14%     88.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            74671891     11.60%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              643808145                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                     3945011                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006128                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  107679      2.73%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                3407280     86.37%     89.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                430052     10.90%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses              647753136                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads         1684034505                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses    631945163                       # Number of integer instruction queue wakeup accesses
@@ -394,6 +376,24 @@ system.cpu.iq.iqSquashedInstsExamined        86496318                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            356529                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved            850                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined    162226931                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples     392116711                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.641879                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.551770                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           108904518     27.77%     27.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           107421508     27.40%     55.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            76290088     19.46%     74.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            48454562     12.36%     86.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            26882762      6.86%     93.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            16851716      4.30%     98.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5414053      1.38%     99.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1011203      0.26%     99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              886301      0.23%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       392116711                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.638079                       # Inst issue rate
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -468,10 +468,10 @@ system.cpu.l2cache.demand_mshr_misses           91150                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.057260                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.487109                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          1876.282231                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         15961.603623                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.057260                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.487109                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            444538                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34340.043442                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.047175                       # average overall mshr miss latency
@@ -502,27 +502,27 @@ system.cpu.misc_regfile_writes                   2682                       # nu
 system.cpu.numCycles                        393026282                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles          9628088                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps      471021820                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents        50048668                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         176696020                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        1915065                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups     2034394520                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       711291370                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    553214444                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          138291459                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        12871984                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       54521168                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          82192621                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups           96                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups   2034394424                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles       107992                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts         6480                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           91409775                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts         6477                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                 9628088                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps             471021820                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents               50048668                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                176696020                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents               1915065                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenameLookups            2034394520                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts              711291370                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands           553214444                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                 138291459                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles               12871984                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles              54521168                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                 82192621                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups                96                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups       2034394424                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles         107992                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts               6480                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                  91409775                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts           6477                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                   1060565987                       # The number of ROB reads
 system.cpu.rob.rob_writes                  1391311417                       # The number of ROB writes
 system.cpu.timesIdled                           36947                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
index b07d285b7..17d38a039 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
@@ -61,12 +61,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
index d9332d696..ceb1053f2 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 17:54:33
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 12:47:58
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
index f0089af03..3089a85c4 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1048186                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 246964                       # Number of bytes of host memory used
-host_seconds                                   574.67                       # Real time elapsed on the host
-host_tick_rate                              524112689                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4079554                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206080                       # Number of bytes of host memory used
+host_seconds                                   147.65                       # Real time elapsed on the host
+host_tick_rate                             2039852029                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   602359851                       # Number of instructions simulated
 sim_seconds                                  0.301191                       # Number of seconds simulated
@@ -71,6 +71,6 @@ system.cpu.num_int_register_writes          458076290                       # nu
 system.cpu.num_load_insts                   148952594                       # Number of load instructions
 system.cpu.num_mem_refs                     219173607                       # number of memory refs
 system.cpu.num_store_insts                   70221013                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
index 5a251a60a..f2a118cfd 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
@@ -164,12 +164,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
index 9680f68d5..99cb1ccc7 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 17:54:33
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 12:48:29
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
index 9997800cb..e356c348b 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 590565                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 254684                       # Number of bytes of host memory used
-host_seconds                                  1016.65                       # Real time elapsed on the host
-host_tick_rate                              783712761                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2132031                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213820                       # Number of bytes of host memory used
+host_seconds                                   281.61                       # Real time elapsed on the host
+host_tick_rate                             2829324901                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   600398281                       # Number of instructions simulated
 sim_seconds                                  0.796763                       # Number of seconds simulated
@@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses           437564                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999566                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4094.222434                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999566                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          217209383                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 22578.841038                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038                       # average overall mshr miss latency
@@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses              643                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.282094                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            577.728532                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.282094                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          570074535                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 54236.391913                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913                       # average overall mshr miss latency
@@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses           89992                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.053777                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.492610                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          1762.179345                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         16141.835335                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.053777                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.492610                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            438207                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -264,6 +264,6 @@ system.cpu.num_int_register_writes          458076290                       # nu
 system.cpu.num_load_insts                   148952594                       # Number of load instructions
 system.cpu.num_mem_refs                     219173607                       # number of memory refs
 system.cpu.num_store_insts                   70221013                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index 2c96b363d..3ff1381e0 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
index bc6585d4f..9d435e3a3 100755
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 23:04:27
-M5 started Mar 17 2011 23:11:57
-M5 executing on zizzer
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:20:08
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index 0f4eafb7d..04c8a25b6 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 165963                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 210376                       # Number of bytes of host memory used
-host_seconds                                  8469.40                       # Real time elapsed on the host
-host_tick_rate                               68767363                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 280029                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206320                       # Number of bytes of host memory used
+host_seconds                                  5019.49                       # Real time elapsed on the host
+host_tick_rate                              116031336                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1405604152                       # Number of instructions simulated
 sim_seconds                                  0.582418                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect            5339067                       # Nu
 system.cpu.BPredUnit.condPredicted          103713551                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                103713551                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               86248929                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          26710610                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples   1136580592                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.310530                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.747403                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    402922453     35.45%     35.45% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    477569543     42.02%     77.47% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     55697713      4.90%     82.37% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     97088718      8.54%     90.91% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     32658945      2.87%     93.78% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      8438570      0.74%     94.53% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6     25679618      2.26%     96.79% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      9814422      0.86%     97.65% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     26710610      2.35%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total   1136580592                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                1489523295                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                8452036                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts            1319476388                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                 402512844                       # Number of loads committed
-system.cpu.commit.COM:membars                   51356                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  569360986                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts           5339067                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                   86248929                       # Number of branches committed
+system.cpu.commit.bw_lim_events              26710610                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts     1489523295                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls         2243671                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts       199490556                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples   1136580592                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.310530                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.747403                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    402922453     35.45%     35.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    477569543     42.02%     77.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     55697713      4.90%     82.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     97088718      8.54%     90.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     32658945      2.87%     93.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      8438570      0.74%     94.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     25679618      2.26%     96.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      9814422      0.86%     97.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     26710610      2.35%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1136580592                       # Number of insts commited each cycle
+system.cpu.commit.count                    1489523295                       # Number of instructions committed
+system.cpu.commit.fp_insts                    8452036                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.int_insts                1319476388                       # Number of committed integer instructions.
+system.cpu.commit.loads                     402512844                       # Number of loads committed
+system.cpu.commit.membars                       51356                       # Number of memory barriers committed
+system.cpu.commit.refs                      569360986                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                  1405604152                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1405604152                       # Number of Instructions Simulated
 system.cpu.cpi                               0.828709                       # CPI: Cycles Per Instruction
@@ -106,8 +106,8 @@ system.cpu.dcache.demand_mshr_misses           481375                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999855                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4095.405595                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999855                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          458308294                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 15159.332747                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 10578.009334                       # average overall mshr miss latency
@@ -129,12 +129,12 @@ system.cpu.dcache.tagsinuse               4095.405595                       # Cy
 system.cpu.dcache.total_refs                455672050                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              132278000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   428224                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles      373408138                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts      1727466392                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         394807577                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          348667632                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        27885594                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles       19696634                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles             373408138                       # Number of cycles decode is blocked
+system.cpu.decode.DecodedInsts             1727466392                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                394807577                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                 348667632                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles               27885594                       # Number of cycles decode is squashing
+system.cpu.decode.UnblockCycles              19696634                       # Number of cycles decode is unblocking
 system.cpu.fetch.Branches                   103713551                       # Number of branches that fetch encountered
 system.cpu.fetch.CacheLines                 170870865                       # Number of cache lines fetched
 system.cpu.fetch.Cycles                     370648133                       # Number of cycles fetch has run and was not squashing or blocked
@@ -198,8 +198,8 @@ system.cpu.icache.demand_mshr_misses             1297                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.511535                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1047.623620                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.511535                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          170870865                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 35272.495756                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 35056.283732                       # average overall mshr miss latency
@@ -222,21 +222,13 @@ system.cpu.icache.total_refs                170869098                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                          370544                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 89603944                       # Number of branches executed
-system.cpu.iew.EXEC:nop                     100373819                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.267070                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    591399205                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                  170154785                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                1209973999                       # num instructions consuming a value
-system.cpu.iew.WB:count                    1473173854                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.961076                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                1162877329                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.264705                       # insts written-back per cycle
-system.cpu.iew.WB:sent                     1474297623                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts              5675287                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                 89603944                       # Number of branches executed
+system.cpu.iew.exec_nop                     100373819                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.267070                       # Inst execution rate
+system.cpu.iew.exec_refs                    591399205                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                  170154785                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                 2507924                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts             461157302                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts            2999936                       # Number of dispatched non-speculative instructions
@@ -264,103 +256,93 @@ system.cpu.iew.lsq.thread.0.squashedStores     20174020                       #
 system.cpu.iew.memOrderViolationEvents         460365                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       670427                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        5004860                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                1209973999                       # num instructions consuming a value
+system.cpu.iew.wb_count                    1473173854                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.961076                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                1162877329                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.264705                       # insts written-back per cycle
+system.cpu.iew.wb_sent                     1474297623                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads               1997794756                       # number of integer regfile reads
 system.cpu.int_regfile_writes              1296594839                       # number of integer regfile writes
 system.cpu.ipc                               1.206697                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.206697                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       883945189     59.64%     59.64% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              0      0.00%     59.64% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     59.64% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd       2631981      0.18%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     59.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      424001958     28.61%     88.42% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite     171668003     11.58%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total       1482247131                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               3391020                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.002288                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu            214212      6.32%      6.32% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      6.32% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      6.32% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd          187778      5.54%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     11.85% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          2748667     81.06%     92.91% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          240363      7.09%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples   1164465575                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.272899                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.148641                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     309298241     26.56%     26.56% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     465738905     40.00%     66.56% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2     229121985     19.68%     86.23% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3     104115000      8.94%     95.17% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      41467759      3.56%     98.74% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       8912842      0.77%     99.50% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       5349281      0.46%     99.96% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        304172      0.03%     99.99% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        157390      0.01%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total   1164465575                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.272494                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             883945189     59.64%     59.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     59.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     59.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2631981      0.18%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.81% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            424001958     28.61%     88.42% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           171668003     11.58%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             1482247131                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                 9142959                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads            17762219                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses      8523024                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes            9165283                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                     3391020                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.002288                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  214212      6.32%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                187778      5.54%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2748667     81.06%     92.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                240363      7.09%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses             1476495192                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads         4114870575                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses   1464650830                       # Number of integer instruction queue wakeup accesses
@@ -372,6 +354,24 @@ system.cpu.iq.iqSquashedInstsExamined       182705519                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            281937                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved         855886                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined    240684944                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples    1164465575                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.272899                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.148641                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           309298241     26.56%     26.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           465738905     40.00%     66.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           229121985     19.68%     86.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           104115000      8.94%     95.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            41467759      3.56%     98.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             8912842      0.77%     99.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5349281      0.46%     99.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              304172      0.03%     99.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              157390      0.01%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1164465575                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.272494                       # Inst issue rate
 system.cpu.l2cache.ReadExReq_accesses          268051                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.834444                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31320.706026                       # average ReadExReq mshr miss latency
@@ -416,10 +416,10 @@ system.cpu.l2cache.demand_mshr_misses           94147                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.059800                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.479227                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          1959.521413                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         15703.307498                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.059800                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.479227                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            482679                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34275.266339                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31207.701786                       # average overall mshr miss latency
@@ -450,28 +450,28 @@ system.cpu.misc_regfile_writes                2258933                       # nu
 system.cpu.numCycles                       1164836119                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles        115497905                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps     1244770452                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:FullRegisterEvents     28107626                       # Number of times there has been no free registers
-system.cpu.rename.RENAME:IQFullEvents       128337052                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         433132347                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents       40459205                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups     2887426636                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      1709740875                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands   1426816340                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          325737783                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        27885594                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles      209164686                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps         182045888                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups     33660518                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups   2853766118                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles     53047260                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts      3085415                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts          378977297                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts      3085429                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles               115497905                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps            1244770452                       # Number of HB maps that are committed
+system.cpu.rename.FullRegisterEvents         28107626                       # Number of times there has been no free registers
+system.cpu.rename.IQFullEvents              128337052                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                433132347                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents              40459205                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenameLookups            2887426636                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts             1709740875                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands          1426816340                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                 325737783                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles               27885594                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles             209164686                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                182045888                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups          33660518                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups       2853766118                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles       53047260                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts            3085415                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                 378977297                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts        3085429                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                   2798818963                       # The number of ROB reads
 system.cpu.rob.rob_writes                  3405946340                       # The number of ROB writes
 system.cpu.timesIdled                           11499                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              49                       # Number of system calls
+system.cpu.workload.num_syscalls                   49                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
index 4748a164d..6bfdef722 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:14:57
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:21:44
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
index 16c920737..d5fea60de 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1524596                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 219684                       # Number of bytes of host memory used
-host_seconds                                   977.00                       # Real time elapsed on the host
-host_tick_rate                              762300416                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4954155                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197572                       # Number of bytes of host memory used
+host_seconds                                   300.66                       # Real time elapsed on the host
+host_tick_rate                             2477084432                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1489523295                       # Number of instructions simulated
 sim_seconds                                  0.744764                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes         1234411208                       # nu
 system.cpu.num_load_insts                   402515346                       # Number of load instructions
 system.cpu.num_mem_refs                     569365767                       # number of memory refs
 system.cpu.num_store_insts                  166850421                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              49                       # Number of system calls
+system.cpu.workload.num_syscalls                   49                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
index 9789f7d05..d8d6cf280 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
index f2b4b3e16..e55df7545 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:13:36
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:20:53
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index 8bc8178fc..6356f769a 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 594721                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 227400                       # Number of bytes of host memory used
-host_seconds                                  2504.58                       # Real time elapsed on the host
-host_tick_rate                              824195004                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2608442                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 205324                       # Number of bytes of host memory used
+host_seconds                                   571.04                       # Real time elapsed on the host
+host_tick_rate                             3614912787                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1489523295                       # Number of instructions simulated
 sim_seconds                                  2.064259                       # Number of seconds simulated
@@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses           453214                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999811                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4095.226955                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999811                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          569359660                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 22454.694692                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692                       # average overall mshr miss latency
@@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses             1107                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.442603                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            906.450625                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.442603                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses         1485113012                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55848.238482                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482                       # average overall mshr miss latency
@@ -183,10 +183,10 @@ system.cpu.l2cache.demand_mshr_misses           92343                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.057187                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.483685                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          1873.919591                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         15849.385934                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.057187                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.483685                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            454328                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -228,6 +228,6 @@ system.cpu.num_int_register_writes         1234411207                       # nu
 system.cpu.num_load_insts                   402515346                       # Number of load instructions
 system.cpu.num_mem_refs                     569365767                       # number of memory refs
 system.cpu.num_store_insts                  166850421                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              49                       # Number of system calls
+system.cpu.workload.num_syscalls                   49                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
index 2af9a6819..21fe896ca 100644
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
index f0ec00748..f0ad86715 100755
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 18 2011 20:12:06
-M5 started Mar 18 2011 20:12:27
-M5 executing on zizzer
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:31:00
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
index 3726448fa..99a6b6318 100644
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 151077                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 216016                       # Number of bytes of host memory used
-host_seconds                                 10732.89                       # Real time elapsed on the host
-host_tick_rate                               69979188                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 229365                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211952                       # Number of bytes of host memory used
+host_seconds                                  7069.49                       # Real time elapsed on the host
+host_tick_rate                              106242349                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1621493982                       # Number of instructions simulated
 sim_seconds                                  0.751079                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect            8971423                       # Nu
 system.cpu.BPredUnit.condPredicted          179993455                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                179993455                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches              107161579                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          11445860                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples   1402522347                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.156127                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.381739                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    522037324     37.22%     37.22% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    531767209     37.92%     75.14% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2    125147036      8.92%     84.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3    139348503      9.94%     93.99% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     42559094      3.03%     97.03% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5     23457685      1.67%     98.70% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6      5021941      0.36%     99.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      1737695      0.12%     99.18% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     11445860      0.82%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total   1402522347                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                1621493982                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                      0                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts            1621354492                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                 419042125                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  607228182                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts           8971450                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                  107161579                       # Number of branches committed
+system.cpu.commit.bw_lim_events              11445860                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts     1621493982                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls              50                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts       721713449                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples   1402522347                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.156127                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.381739                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    522037324     37.22%     37.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    531767209     37.92%     75.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    125147036      8.92%     84.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3    139348503      9.94%     93.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     42559094      3.03%     97.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     23457685      1.67%     98.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      5021941      0.36%     99.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1737695      0.12%     99.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11445860      0.82%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1402522347                       # Number of insts commited each cycle
+system.cpu.commit.count                    1621493982                       # Number of instructions committed
+system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.int_insts                1621354492                       # Number of committed integer instructions.
+system.cpu.commit.loads                     419042125                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                      607228182                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                  1621493982                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1621493982                       # Number of Instructions Simulated
 system.cpu.cpi                               0.926404                       # CPI: Cycles Per Instruction
@@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses           465016                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999792                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4095.146726                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999792                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          513587988                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 18150.803874                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  8690.812783                       # average overall mshr miss latency
@@ -119,12 +119,12 @@ system.cpu.dcache.tagsinuse               4095.146726                       # Cy
 system.cpu.dcache.total_refs                512136646                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              317706000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   411408                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles      587921420                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts      2472731706                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         429893143                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          331529130                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        99378480                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles       53178654                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles             587921420                       # Number of cycles decode is blocked
+system.cpu.decode.DecodedInsts             2472731706                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                429893143                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                 331529130                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles               99378480                       # Number of cycles decode is squashing
+system.cpu.decode.UnblockCycles              53178654                       # Number of cycles decode is unblocking
 system.cpu.fetch.Branches                   179993455                       # Number of branches that fetch encountered
 system.cpu.fetch.CacheLines                 170058043                       # Number of cache lines fetched
 system.cpu.fetch.Cycles                     400227143                       # Number of cycles fetch has run and was not squashing or blocked
@@ -187,8 +187,8 @@ system.cpu.icache.demand_mshr_misses              869                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.387535                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            793.670730                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.387535                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          170058043                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 35240.756303                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 35321.058688                       # average overall mshr miss latency
@@ -211,21 +211,13 @@ system.cpu.icache.total_refs                170056853                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                          257635                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                111429178                       # Number of branches executed
-system.cpu.iew.EXEC:nop                             0                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.227514                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    636597814                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                  191695864                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                2082700302                       # num instructions consuming a value
-system.cpu.iew.WB:count                    1838995466                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.683970                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                1424504384                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.224235                       # insts written-back per cycle
-system.cpu.iew.WB:sent                     1842743630                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts              9107858                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                111429178                       # Number of branches executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.227514                       # Inst execution rate
+system.cpu.iew.exec_refs                    636597814                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                  191695864                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                 1395305                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts             615851374                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                 81                       # Number of dispatched non-speculative instructions
@@ -253,103 +245,93 @@ system.cpu.iew.lsq.thread.0.squashedStores     62612798                       #
 system.cpu.iew.memOrderViolationEvents        6399400                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      4677718                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        4430140                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                2082700302                       # num instructions consuming a value
+system.cpu.iew.wb_count                    1838995466                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.683970                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                1424504384                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.224235                       # insts written-back per cycle
+system.cpu.iew.wb_sent                     1842743630                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads               3236941415                       # number of integer regfile reads
 system.cpu.int_regfile_writes              1831971139                       # number of integer regfile writes
 system.cpu.ipc                               1.079443                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.079443                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass     28079218      1.51%      1.51% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu      1185434411     63.84%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      451340139     24.30%     89.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite     192134588     10.35%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total       1856988356                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               4273878                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.002302                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu            161807      3.79%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          3493887     81.75%     85.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          618184     14.46%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples   1501900827                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.236425                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.221094                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     463034659     30.83%     30.83% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     580779168     38.67%     69.50% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2     218589752     14.55%     84.05% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3     151066938     10.06%     94.11% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      63504112      4.23%     98.34% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      18859628      1.26%     99.60% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       5092601      0.34%     99.94% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        833076      0.06%     99.99% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        140893      0.01%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total   1501900827                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.236213                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass          28079218      1.51%      1.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1185434411     63.84%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.35% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            451340139     24.30%     89.65% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           192134588     10.35%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             1856988356                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                      19                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                  35                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           12                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                 32                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                     4273878                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.002302                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  161807      3.79%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                3493887     81.75%     85.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                618184     14.46%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses             1833182997                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads         5220358647                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses   1838995454                       # Number of integer instruction queue wakeup accesses
@@ -361,6 +343,24 @@ system.cpu.iq.iqSquashedInstsExamined       721564206                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            207265                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             31                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined   1518322063                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples    1501900827                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.236425                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.221094                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           463034659     30.83%     30.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           580779168     38.67%     69.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           218589752     14.55%     84.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           151066938     10.06%     94.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            63504112      4.23%     98.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            18859628      1.26%     99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5092601      0.34%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              833076      0.06%     99.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              140893      0.01%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1501900827                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.236213                       # Inst issue rate
 system.cpu.l2cache.ReadExReq_accesses          250113                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.651379                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.730459                       # average ReadExReq mshr miss latency
@@ -405,10 +405,10 @@ system.cpu.l2cache.demand_mshr_misses           91933                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.058491                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.491164                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          1916.626475                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         16094.448281                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.058491                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.491164                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            465885                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34310.106273                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.889419                       # average overall mshr miss latency
@@ -438,28 +438,28 @@ system.cpu.misc_regfile_reads               931071836                       # nu
 system.cpu.numCycles                       1502158462                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles        169288978                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps     1617994650                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents       298516669                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         493321936                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents      107168100                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents             70                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     5808956116                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      2397077126                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands   2395694665                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          310095488                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        99378480                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles      429812969                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps         777700015                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups           64                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups   5808956052                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles         2976                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts           89                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts          706930007                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts           89                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles               169288978                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps            1617994650                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents              298516669                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                493321936                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents             107168100                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                    70                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups            5808956116                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts             2397077126                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands          2395694665                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                 310095488                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles               99378480                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles             429812969                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                777700015                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups                64                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups       5808956052                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles           2976                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts                 89                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                 706930007                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts             89                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                   3734283918                       # The number of ROB reads
 system.cpu.rob.rob_writes                  4785794667                       # The number of ROB writes
 system.cpu.timesIdled                           45615                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
index bb6395625..b229bc589 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb  8 2011 00:58:34
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:22:36
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index 5b839ec88..f6fa9ef1e 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2470310                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 224012                       # Number of bytes of host memory used
-host_seconds                                   656.39                       # Real time elapsed on the host
-host_tick_rate                             1468620897                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3280168                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202508                       # Number of bytes of host memory used
+host_seconds                                   494.33                       # Real time elapsed on the host
+host_tick_rate                             1950088412                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1621493983                       # Number of instructions simulated
 sim_seconds                                  0.963993                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes         1617994650                       # nu
 system.cpu.num_load_insts                   419042125                       # Number of load instructions
 system.cpu.num_mem_refs                     607228182                       # number of memory refs
 system.cpu.num_store_insts                  188186057                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
index 967d3d328..fa700a969 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
index 920574653..eb8442791 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb  8 2011 00:58:34
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:23:09
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
index 120240c59..1cc5290ea 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1667736                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 231728                       # Number of bytes of host memory used
-host_seconds                                   972.27                       # Real time elapsed on the host
-host_tick_rate                             1854683738                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2023797                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 210248                       # Number of bytes of host memory used
+host_seconds                                   801.21                       # Real time elapsed on the host
+host_tick_rate                             2250658484                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1621493983                       # Number of instructions simulated
 sim_seconds                                  1.803259                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses           442048                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999731                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4094.896939                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999731                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          607228182                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 22431.962140                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140                       # average overall mshr miss latency
@@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses              722                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.322357                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            660.186297                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.322357                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses         1186516740                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses           89468                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.057043                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.494010                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          1869.199731                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         16187.723361                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.057043                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.494010                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            442770                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -218,6 +218,6 @@ system.cpu.num_int_register_writes         1617994650                       # nu
 system.cpu.num_load_insts                   419042125                       # Number of load instructions
 system.cpu.num_mem_refs                     607228182                       # number of memory refs
 system.cpu.num_store_insts                  188186057                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
+system.cpu.workload.num_syscalls                   48                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index 1b7aa47b5..674bf0325 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -50,6 +50,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
@@ -483,6 +485,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index c0c960a9c..9ebdcf06b 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 22:48:41
-M5 started Mar 17 2011 22:50:14
-M5 executing on zizzer
+M5 compiled Apr 19 2011 12:17:36
+M5 started Apr 19 2011 12:17:43
+M5 executing on maize
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 1aa5f5dbb..31187c584 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 127019                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 296760                       # Number of bytes of host memory used
-host_seconds                                   449.39                       # Real time elapsed on the host
-host_tick_rate                             4231820542                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 245660                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 294304                       # Number of bytes of host memory used
+host_seconds                                   232.36                       # Real time elapsed on the host
+host_tick_rate                             8184534150                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    57080594                       # Number of instructions simulated
 sim_seconds                                  1.901725                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu0.BPredUnit.condIncorrect            455851                       # Nu
 system.cpu0.BPredUnit.condPredicted           9912652                       # Number of conditional branches predicted
 system.cpu0.BPredUnit.lookups                11764241                       # Number of BP lookups
 system.cpu0.BPredUnit.usedRAS                  785162                       # Number of times the RAS was used to get a target.
-system.cpu0.commit.COM:branches               7026012                       # Number of branches committed
-system.cpu0.commit.COM:bw_lim_events           938799                       # number cycles where commit BW limit reached
-system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
-system.cpu0.commit.COM:committed_per_cycle::samples     72953049                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::mean     0.644604                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::stdev     1.459058                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::0     53597246     73.47%     73.47% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::1      8417746     11.54%     85.01% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::2      4840163      6.63%     91.64% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::3      2111570      2.89%     94.54% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::4      1587453      2.18%     96.71% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::5       575078      0.79%     97.50% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::6       337488      0.46%     97.96% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::7       547506      0.75%     98.71% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::8       938799      1.29%    100.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::total     72953049                       # Number of insts commited each cycle
-system.cpu0.commit.COM:count                 47025846                       # Number of instructions committed
-system.cpu0.commit.COM:fp_insts                287589                       # Number of committed floating point instructions.
-system.cpu0.commit.COM:function_calls          606692                       # Number of function calls committed.
-system.cpu0.commit.COM:int_insts             43528406                       # Number of committed integer instructions.
-system.cpu0.commit.COM:loads                  7569996                       # Number of loads committed
-system.cpu0.commit.COM:membars                 198353                       # Number of memory barriers committed
-system.cpu0.commit.COM:refs                  12959088                       # Number of memory references committed
-system.cpu0.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
 system.cpu0.commit.branchMispredicts           606344                       # The number of times a branch was mispredicted
+system.cpu0.commit.branches                   7026012                       # Number of branches committed
+system.cpu0.commit.bw_lim_events               938799                       # number cycles where commit BW limit reached
+system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu0.commit.commitCommittedInsts      47025846                       # The number of committed instructions
 system.cpu0.commit.commitNonSpecStalls         585526                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu0.commit.commitSquashedInsts        5969393                       # The number of squashed insts skipped by commit
+system.cpu0.commit.committed_per_cycle::samples     72953049                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.644604                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.459058                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     53597246     73.47%     73.47% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      8417746     11.54%     85.01% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      4840163      6.63%     91.64% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2111570      2.89%     94.54% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1587453      2.18%     96.71% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       575078      0.79%     97.50% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       337488      0.46%     97.96% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       547506      0.75%     98.71% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8       938799      1.29%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::total     72953049                       # Number of insts commited each cycle
+system.cpu0.commit.count                     47025846                       # Number of instructions committed
+system.cpu0.commit.fp_insts                    287589                       # Number of committed floating point instructions.
+system.cpu0.commit.function_calls              606692                       # Number of function calls committed.
+system.cpu0.commit.int_insts                 43528406                       # Number of committed integer instructions.
+system.cpu0.commit.loads                      7569996                       # Number of loads committed
+system.cpu0.commit.membars                     198353                       # Number of memory barriers committed
+system.cpu0.commit.refs                      12959088                       # Number of memory references committed
+system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
 system.cpu0.committedInsts                   44336308                       # Number of Instructions Simulated
 system.cpu0.committedInsts_total             44336308                       # Number of Instructions Simulated
 system.cpu0.cpi                              2.365714                       # CPI: Cycles Per Instruction
@@ -161,10 +161,10 @@ system.cpu0.dcache.demand_mshr_misses         1044131                       # nu
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0                  0.956764                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_%::1                 -0.001953                       # Average percentage of cache occupancy
 system.cpu0.dcache.occ_blocks::0           489.863061                       # Average occupied blocks per context
 system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.956764                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::1           -0.001953                       # Average percentage of cache occupancy
 system.cpu0.dcache.overall_accesses::0       12748257                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::total     12748257                       # number of overall (read+write) accesses
@@ -198,15 +198,15 @@ system.cpu0.dcache.tagsinuse               488.863062                       # Cy
 system.cpu0.dcache.total_refs                10250942                       # Total number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu0.dcache.writebacks                  532971                       # number of writebacks
-system.cpu0.decode.DECODE:BlockedCycles      30335443                       # Number of cycles decode is blocked
-system.cpu0.decode.DECODE:BranchMispred         32433                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DECODE:BranchResolved       467445                       # Number of times decode resolved a branch
-system.cpu0.decode.DECODE:DecodedInsts       58302731                       # Number of instructions handled by decode
-system.cpu0.decode.DECODE:IdleCycles         31236137                       # Number of cycles decode is idle
-system.cpu0.decode.DECODE:RunCycles          10506640                       # Number of cycles decode is running
-system.cpu0.decode.DECODE:SquashCycles        1085015                       # Number of cycles decode is squashing
-system.cpu0.decode.DECODE:SquashedInsts         96992                       # Number of squashed instructions handled by decode
-system.cpu0.decode.DECODE:UnblockCycles        874828                       # Number of cycles decode is unblocking
+system.cpu0.decode.BlockedCycles             30335443                       # Number of cycles decode is blocked
+system.cpu0.decode.BranchMispred                32433                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.BranchResolved              467445                       # Number of times decode resolved a branch
+system.cpu0.decode.DecodedInsts              58302731                       # Number of instructions handled by decode
+system.cpu0.decode.IdleCycles                31236137                       # Number of cycles decode is idle
+system.cpu0.decode.RunCycles                 10506640                       # Number of cycles decode is running
+system.cpu0.decode.SquashCycles               1085015                       # Number of cycles decode is squashing
+system.cpu0.decode.SquashedInsts                96992                       # Number of squashed instructions handled by decode
+system.cpu0.decode.UnblockCycles               874828                       # Number of cycles decode is unblocking
 system.cpu0.dtb.data_accesses                  755162                       # DTB accesses
 system.cpu0.dtb.data_acv                          768                       # DTB access violations
 system.cpu0.dtb.data_hits                    13777358                       # DTB hits
@@ -305,8 +305,8 @@ system.cpu0.icache.demand_mshr_misses          839121                       # nu
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0                  0.995851                       # Average percentage of cache occupancy
 system.cpu0.icache.occ_blocks::0           509.875783                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.995851                       # Average percentage of cache occupancy
 system.cpu0.icache.overall_accesses::0        7276849                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::total      7276849                       # number of overall (read+write) accesses
@@ -341,21 +341,13 @@ system.cpu0.icache.total_refs                 6407354                       # To
 system.cpu0.icache.warmup_cycle           23816238000                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.writebacks                     147                       # number of writebacks
 system.cpu0.idleCycles                       30848962                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.iew.EXEC:branches                 7463719                       # Number of branches executed
-system.cpu0.iew.EXEC:nop                      2952874                       # number of nop insts executed
-system.cpu0.iew.EXEC:rate                    0.449724                       # Inst execution rate
-system.cpu0.iew.EXEC:refs                    13848442                       # number of memory reference insts executed
-system.cpu0.iew.EXEC:stores                   5542976                       # Number of stores executed
-system.cpu0.iew.EXEC:swp                            0                       # number of swp insts executed
-system.cpu0.iew.WB:consumers                 29600256                       # num instructions consuming a value
-system.cpu0.iew.WB:count                     46794498                       # cumulative count of insts written-back
-system.cpu0.iew.WB:fanout                    0.755402                       # average fanout of values written-back
-system.cpu0.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.iew.WB:producers                 22360092                       # num instructions producing a value
-system.cpu0.iew.WB:rate                      0.446142                       # insts written-back per cycle
-system.cpu0.iew.WB:sent                      46875004                       # cumulative count of insts sent to commit
 system.cpu0.iew.branchMispredicts              654991                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.exec_branches                 7463719                       # Number of branches executed
+system.cpu0.iew.exec_nop                      2952874                       # number of nop insts executed
+system.cpu0.iew.exec_rate                    0.449724                       # Inst execution rate
+system.cpu0.iew.exec_refs                    13848442                       # number of memory reference insts executed
+system.cpu0.iew.exec_stores                   5542976                       # Number of stores executed
+system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu0.iew.iewBlockCycles                7417251                       # Number of cycles IEW is blocking
 system.cpu0.iew.iewDispLoadInsts              8574378                       # Number of dispatched load instructions
 system.cpu0.iew.iewDispNonSpecInsts           1551984                       # Number of dispatched non-speculative instructions
@@ -383,103 +375,93 @@ system.cpu0.iew.lsq.thread.0.squashedStores       318301                       #
 system.cpu0.iew.memOrderViolationEvents         14768                       # Number of memory order violations
 system.cpu0.iew.predictedNotTakenIncorrect       331464                       # Number of branches that were predicted not taken incorrectly
 system.cpu0.iew.predictedTakenIncorrect        323527                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.wb_consumers                 29600256                       # num instructions consuming a value
+system.cpu0.iew.wb_count                     46794498                       # cumulative count of insts written-back
+system.cpu0.iew.wb_fanout                    0.755402                       # average fanout of values written-back
+system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu0.iew.wb_producers                 22360092                       # num instructions producing a value
+system.cpu0.iew.wb_rate                      0.446142                       # insts written-back per cycle
+system.cpu0.iew.wb_sent                      46875004                       # cumulative count of insts sent to commit
 system.cpu0.int_regfile_reads                61873527                       # number of integer regfile reads
 system.cpu0.int_regfile_writes               33807346                       # number of integer regfile writes
 system.cpu0.ipc                              0.422705                       # IPC: Instructions Per Cycle
 system.cpu0.ipc_total                        0.422705                       # IPC: Total IPC of All Threads
-system.cpu0.iq.ISSUE:FU_type_0::No_OpClass         3310      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntAlu       32518161     68.37%     68.38% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntMult         52150      0.11%     68.49% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     68.49% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatAdd        15557      0.03%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatDiv         1653      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     68.52% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemRead       8591465     18.06%     86.59% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemWrite      5582440     11.74%     98.32% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IprAccess       797481      1.68%    100.00% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::total        47562217                       # Type of FU issued
-system.cpu0.iq.ISSUE:fu_busy_cnt               465945                       # FU busy when requested
-system.cpu0.iq.ISSUE:fu_busy_rate            0.009797                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntAlu            32168      6.90%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntMult               0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntDiv                0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatAdd              0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatCmp              0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatCvt              0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatMult             0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatDiv              0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdAdd               0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdAlu               0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdCmp               0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdCvt               0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdMisc              0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdMult              0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdShift             0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      6.90% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemRead          239318     51.36%     58.27% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemWrite         194459     41.73%    100.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:issued_per_cycle::samples     74038064                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::mean     0.642402                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.245120                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::0     51535584     69.61%     69.61% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::1     10789742     14.57%     84.18% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::2      4855288      6.56%     90.74% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::3      3076859      4.16%     94.89% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::4      2068166      2.79%     97.69% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::5       951116      1.28%     98.97% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::6       576531      0.78%     99.75% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::7       134332      0.18%     99.93% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::8        50446      0.07%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::total     74038064                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:rate                    0.453461                       # Inst issue rate
+system.cpu0.iq.FU_type_0::No_OpClass             3310      0.01%      0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             32518161     68.37%     68.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               52150      0.11%     68.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              15557      0.03%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               1653      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             8591465     18.06%     86.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5582440     11.74%     98.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            797481      1.68%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::total              47562217                       # Type of FU issued
 system.cpu0.iq.fp_alu_accesses                 318343                       # Number of floating point alu accesses
 system.cpu0.iq.fp_inst_queue_reads             608219                       # Number of floating instruction queue reads
 system.cpu0.iq.fp_inst_queue_wakeup_accesses       289004                       # Number of floating instruction queue wakeup accesses
 system.cpu0.iq.fp_inst_queue_writes            292979                       # Number of floating instruction queue writes
+system.cpu0.iq.fu_busy_cnt                     465945                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.009797                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  32168      6.90%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      6.90% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                239318     51.36%     58.27% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               194459     41.73%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.int_alu_accesses              47706509                       # Number of integer alu accesses
 system.cpu0.iq.int_inst_queue_reads         169046393                       # Number of integer instruction queue reads
 system.cpu0.iq.int_inst_queue_wakeup_accesses     46505494                       # Number of integer instruction queue wakeup accesses
@@ -491,6 +473,24 @@ system.cpu0.iq.iqSquashedInstsExamined        5493402                       # Nu
 system.cpu0.iq.iqSquashedInstsIssued            26169                       # Number of squashed instructions issued
 system.cpu0.iq.iqSquashedNonSpecRemoved       1178887                       # Number of squashed non-spec instructions that were removed
 system.cpu0.iq.iqSquashedOperandsExamined      2580822                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.issued_per_cycle::samples     74038064                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.642402                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.245120                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           51535584     69.61%     69.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10789742     14.57%     84.18% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            4855288      6.56%     90.74% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            3076859      4.16%     94.89% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2068166      2.79%     97.69% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5             951116      1.28%     98.97% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             576531      0.78%     99.75% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             134332      0.18%     99.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              50446      0.07%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       74038064                       # Number of insts issued each cycle
+system.cpu0.iq.rate                          0.453461                       # Inst issue rate
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_hits                           0                       # DTB hits
@@ -604,25 +604,25 @@ system.cpu0.misc_regfile_writes                822223                       # nu
 system.cpu0.numCycles                       104887026                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.rename.RENAME:BlockCycles        10226952                       # Number of cycles rename is blocking
-system.cpu0.rename.RENAME:CommittedMaps      32010277                       # Number of HB maps that are committed
-system.cpu0.rename.RENAME:IQFullEvents         742771                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.RENAME:IdleCycles         32554760                       # Number of cycles rename is idle
-system.cpu0.rename.RENAME:LSQFullEvents       1133948                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RENAME:ROBFullEvents          1272                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.RENAME:RenameLookups      67011150                       # Number of register rename lookups that rename has made
-system.cpu0.rename.RENAME:RenamedInsts       55116446                       # Number of instructions processed by rename
-system.cpu0.rename.RENAME:RenamedOperands     36911598                       # Number of destination operands rename has renamed
-system.cpu0.rename.RENAME:RunCycles          10340148                       # Number of cycles rename is running
-system.cpu0.rename.RENAME:SquashCycles        1085015                       # Number of cycles rename is squashing
-system.cpu0.rename.RENAME:UnblockCycles       3374476                       # Number of cycles rename is unblocking
-system.cpu0.rename.RENAME:UndoneMaps          4901321                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.RENAME:fp_rename_lookups       420638                       # Number of floating rename lookups
-system.cpu0.rename.RENAME:int_rename_lookups     66590512                       # Number of integer rename lookups
-system.cpu0.rename.RENAME:serializeStallCycles     16456711                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RENAME:serializingInsts      1432211                       # count of serializing insts renamed
-system.cpu0.rename.RENAME:skidInsts           8924178                       # count of insts added to the skid buffer
-system.cpu0.rename.RENAME:tempSerializingInsts       217463                       # count of temporary serializing insts renamed
+system.cpu0.rename.BlockCycles               10226952                       # Number of cycles rename is blocking
+system.cpu0.rename.CommittedMaps             32010277                       # Number of HB maps that are committed
+system.cpu0.rename.IQFullEvents                742771                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.IdleCycles                32554760                       # Number of cycles rename is idle
+system.cpu0.rename.LSQFullEvents              1133948                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.ROBFullEvents                 1272                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.RenameLookups             67011150                       # Number of register rename lookups that rename has made
+system.cpu0.rename.RenamedInsts              55116446                       # Number of instructions processed by rename
+system.cpu0.rename.RenamedOperands           36911598                       # Number of destination operands rename has renamed
+system.cpu0.rename.RunCycles                 10340148                       # Number of cycles rename is running
+system.cpu0.rename.SquashCycles               1085015                       # Number of cycles rename is squashing
+system.cpu0.rename.UnblockCycles              3374476                       # Number of cycles rename is unblocking
+system.cpu0.rename.UndoneMaps                 4901321                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.fp_rename_lookups           420638                       # Number of floating rename lookups
+system.cpu0.rename.int_rename_lookups        66590512                       # Number of integer rename lookups
+system.cpu0.rename.serializeStallCycles      16456711                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.serializingInsts           1432211                       # count of serializing insts renamed
+system.cpu0.rename.skidInsts                  8924178                       # count of insts added to the skid buffer
+system.cpu0.rename.tempSerializingInsts        217463                       # count of temporary serializing insts renamed
 system.cpu0.rob.rob_reads                   124831913                       # The number of ROB reads
 system.cpu0.rob.rob_writes                  107074537                       # The number of ROB writes
 system.cpu0.timesIdled                        1083848                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -634,38 +634,38 @@ system.cpu1.BPredUnit.condIncorrect            156935                       # Nu
 system.cpu1.BPredUnit.condPredicted           2982175                       # Number of conditional branches predicted
 system.cpu1.BPredUnit.lookups                 3622579                       # Number of BP lookups
 system.cpu1.BPredUnit.usedRAS                  265553                       # Number of times the RAS was used to get a target.
-system.cpu1.commit.COM:branches               2030517                       # Number of branches committed
-system.cpu1.commit.COM:bw_lim_events           301379                       # number cycles where commit BW limit reached
-system.cpu1.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
-system.cpu1.commit.COM:committed_per_cycle::samples     21012360                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::mean     0.640018                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::stdev     1.474919                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::0     15563519     74.07%     74.07% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::1      2436778     11.60%     85.67% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::2      1200178      5.71%     91.38% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::3       640529      3.05%     94.43% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::4       421093      2.00%     96.43% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::5       209093      1.00%     97.42% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::6       129842      0.62%     98.04% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::7       109949      0.52%     98.57% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::8       301379      1.43%    100.00% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::total     21012360                       # Number of insts commited each cycle
-system.cpu1.commit.COM:count                 13448285                       # Number of instructions committed
-system.cpu1.commit.COM:fp_insts                 77652                       # Number of committed floating point instructions.
-system.cpu1.commit.COM:function_calls          196980                       # Number of function calls committed.
-system.cpu1.commit.COM:int_insts             12472477                       # Number of committed integer instructions.
-system.cpu1.commit.COM:loads                  2329401                       # Number of loads committed
-system.cpu1.commit.COM:membars                  46552                       # Number of memory barriers committed
-system.cpu1.commit.COM:refs                   3759357                       # Number of memory references committed
-system.cpu1.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
 system.cpu1.commit.branchMispredicts           207236                       # The number of times a branch was mispredicted
+system.cpu1.commit.branches                   2030517                       # Number of branches committed
+system.cpu1.commit.bw_lim_events               301379                       # number cycles where commit BW limit reached
+system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu1.commit.commitCommittedInsts      13448285                       # The number of committed instructions
 system.cpu1.commit.commitNonSpecStalls         143621                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu1.commit.commitSquashedInsts        2329974                       # The number of squashed insts skipped by commit
+system.cpu1.commit.committed_per_cycle::samples     21012360                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.640018                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.474919                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     15563519     74.07%     74.07% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      2436778     11.60%     85.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      1200178      5.71%     91.38% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       640529      3.05%     94.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       421093      2.00%     96.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       209093      1.00%     97.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       129842      0.62%     98.04% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       109949      0.52%     98.57% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       301379      1.43%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::total     21012360                       # Number of insts commited each cycle
+system.cpu1.commit.count                     13448285                       # Number of instructions committed
+system.cpu1.commit.fp_insts                     77652                       # Number of committed floating point instructions.
+system.cpu1.commit.function_calls              196980                       # Number of function calls committed.
+system.cpu1.commit.int_insts                 12472477                       # Number of committed integer instructions.
+system.cpu1.commit.loads                      2329401                       # Number of loads committed
+system.cpu1.commit.membars                      46552                       # Number of memory barriers committed
+system.cpu1.commit.refs                       3759357                       # Number of memory references committed
+system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
 system.cpu1.committedInsts                   12744286                       # Number of Instructions Simulated
 system.cpu1.committedInsts_total             12744286                       # Number of Instructions Simulated
 system.cpu1.cpi                              1.922547                       # CPI: Cycles Per Instruction
@@ -779,8 +779,8 @@ system.cpu1.dcache.demand_mshr_misses          332240                       # nu
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0                  0.934780                       # Average percentage of cache occupancy
 system.cpu1.dcache.occ_blocks::0           478.607338                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.934780                       # Average percentage of cache occupancy
 system.cpu1.dcache.overall_accesses::0        3867599                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total      3867599                       # number of overall (read+write) accesses
@@ -814,15 +814,15 @@ system.cpu1.dcache.tagsinuse               478.607338                       # Cy
 system.cpu1.dcache.total_refs                 3201172                       # Total number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle           38945924000                       # Cycle when the warmup percentage was hit.
 system.cpu1.dcache.writebacks                  258747                       # number of writebacks
-system.cpu1.decode.DECODE:BlockedCycles       8810954                       # Number of cycles decode is blocked
-system.cpu1.decode.DECODE:BranchMispred         10399                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DECODE:BranchResolved       165542                       # Number of times decode resolved a branch
-system.cpu1.decode.DECODE:DecodedInsts       17654641                       # Number of instructions handled by decode
-system.cpu1.decode.DECODE:IdleCycles          8825966                       # Number of cycles decode is idle
-system.cpu1.decode.DECODE:RunCycles           3267842                       # Number of cycles decode is running
-system.cpu1.decode.DECODE:SquashCycles         401676                       # Number of cycles decode is squashing
-system.cpu1.decode.DECODE:SquashedInsts         25654                       # Number of squashed instructions handled by decode
-system.cpu1.decode.DECODE:UnblockCycles        107597                       # Number of cycles decode is unblocking
+system.cpu1.decode.BlockedCycles              8810954                       # Number of cycles decode is blocked
+system.cpu1.decode.BranchMispred                10399                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.BranchResolved              165542                       # Number of times decode resolved a branch
+system.cpu1.decode.DecodedInsts              17654641                       # Number of instructions handled by decode
+system.cpu1.decode.IdleCycles                 8825966                       # Number of cycles decode is idle
+system.cpu1.decode.RunCycles                  3267842                       # Number of cycles decode is running
+system.cpu1.decode.SquashCycles                401676                       # Number of cycles decode is squashing
+system.cpu1.decode.SquashedInsts                25654                       # Number of squashed instructions handled by decode
+system.cpu1.decode.UnblockCycles               107597                       # Number of cycles decode is unblocking
 system.cpu1.dtb.data_accesses                  513633                       # DTB accesses
 system.cpu1.dtb.data_acv                          185                       # DTB access violations
 system.cpu1.dtb.data_hits                     4112878                       # DTB hits
@@ -921,8 +921,8 @@ system.cpu1.icache.demand_mshr_misses          233675                       # nu
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0                  0.980042                       # Average percentage of cache occupancy
 system.cpu1.icache.occ_blocks::0           501.781584                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.980042                       # Average percentage of cache occupancy
 system.cpu1.icache.overall_accesses::0        2099932                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::total      2099932                       # number of overall (read+write) accesses
@@ -957,21 +957,13 @@ system.cpu1.icache.total_refs                 1856598                       # To
 system.cpu1.icache.warmup_cycle          1710247615000                       # Cycle when the warmup percentage was hit.
 system.cpu1.icache.writebacks                      27                       # number of writebacks
 system.cpu1.idleCycles                        3087450                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.iew.EXEC:branches                 2215124                       # Number of branches executed
-system.cpu1.iew.EXEC:nop                       807214                       # number of nop insts executed
-system.cpu1.iew.EXEC:rate                    0.568172                       # Inst execution rate
-system.cpu1.iew.EXEC:refs                     4143059                       # number of memory reference insts executed
-system.cpu1.iew.EXEC:stores                   1503378                       # Number of stores executed
-system.cpu1.iew.EXEC:swp                            0                       # number of swp insts executed
-system.cpu1.iew.WB:consumers                  9185033                       # num instructions consuming a value
-system.cpu1.iew.WB:count                     13765716                       # cumulative count of insts written-back
-system.cpu1.iew.WB:fanout                    0.723664                       # average fanout of values written-back
-system.cpu1.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.iew.WB:producers                  6646874                       # num instructions producing a value
-system.cpu1.iew.WB:rate                      0.561832                       # insts written-back per cycle
-system.cpu1.iew.WB:sent                      13802747                       # cumulative count of insts sent to commit
 system.cpu1.iew.branchMispredicts              229368                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.exec_branches                 2215124                       # Number of branches executed
+system.cpu1.iew.exec_nop                       807214                       # number of nop insts executed
+system.cpu1.iew.exec_rate                    0.568172                       # Inst execution rate
+system.cpu1.iew.exec_refs                     4143059                       # number of memory reference insts executed
+system.cpu1.iew.exec_stores                   1503378                       # Number of stores executed
+system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu1.iew.iewBlockCycles                1971298                       # Number of cycles IEW is blocking
 system.cpu1.iew.iewDispLoadInsts              2745592                       # Number of dispatched load instructions
 system.cpu1.iew.iewDispNonSpecInsts            455487                       # Number of dispatched non-speculative instructions
@@ -999,103 +991,93 @@ system.cpu1.iew.lsq.thread.0.squashedStores       148395                       #
 system.cpu1.iew.memOrderViolationEvents          4299                       # Number of memory order violations
 system.cpu1.iew.predictedNotTakenIncorrect       105547                       # Number of branches that were predicted not taken incorrectly
 system.cpu1.iew.predictedTakenIncorrect        123821                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.wb_consumers                  9185033                       # num instructions consuming a value
+system.cpu1.iew.wb_count                     13765716                       # cumulative count of insts written-back
+system.cpu1.iew.wb_fanout                    0.723664                       # average fanout of values written-back
+system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu1.iew.wb_producers                  6646874                       # num instructions producing a value
+system.cpu1.iew.wb_rate                      0.561832                       # insts written-back per cycle
+system.cpu1.iew.wb_sent                      13802747                       # cumulative count of insts sent to commit
 system.cpu1.int_regfile_reads                18282773                       # number of integer regfile reads
 system.cpu1.int_regfile_writes                9947337                       # number of integer regfile writes
 system.cpu1.ipc                              0.520143                       # IPC: Instructions Per Cycle
 system.cpu1.ipc_total                        0.520143                       # IPC: Total IPC of All Threads
-system.cpu1.iq.ISSUE:FU_type_0::No_OpClass         3979      0.03%      0.03% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntAlu        9510353     67.51%     67.54% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntMult         21826      0.15%     67.69% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     67.69% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatAdd        11300      0.08%     67.77% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     67.77% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     67.77% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     67.77% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatDiv         1989      0.01%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     67.79% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemRead       2724274     19.34%     87.13% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemWrite      1523321     10.81%     97.94% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IprAccess       290281      2.06%    100.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::total        14087323                       # Type of FU issued
-system.cpu1.iq.ISSUE:fu_busy_cnt               199599                       # FU busy when requested
-system.cpu1.iq.ISSUE:fu_busy_rate            0.014169                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntAlu            10735      5.38%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntMult               0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntDiv                0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatAdd              0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCmp              0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCvt              0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatMult             0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatDiv              0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAdd               0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAlu               0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdCmp               0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdCvt               0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMisc              0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMult              0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdShift             0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      5.38% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemRead          110682     55.45%     60.83% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemWrite          78182     39.17%    100.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:issued_per_cycle::samples     21414036                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::mean     0.657855                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.314285                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::0     15246065     71.20%     71.20% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::1      2762432     12.90%     84.10% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::2      1149877      5.37%     89.47% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::3       942390      4.40%     93.87% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::4       699267      3.27%     97.13% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::5       379191      1.77%     98.90% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::6       160390      0.75%     99.65% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::7        52788      0.25%     99.90% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::8        21636      0.10%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::total     21414036                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:rate                    0.574958                       # Inst issue rate
+system.cpu1.iq.FU_type_0::No_OpClass             3979      0.03%      0.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              9510353     67.51%     67.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               21826      0.15%     67.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              11300      0.08%     67.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               1989      0.01%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             2724274     19.34%     87.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            1523321     10.81%     97.94% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            290281      2.06%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::total              14087323                       # Type of FU issued
 system.cpu1.iq.fp_alu_accesses                  84267                       # Number of floating point alu accesses
 system.cpu1.iq.fp_inst_queue_reads             163543                       # Number of floating instruction queue reads
 system.cpu1.iq.fp_inst_queue_wakeup_accesses        78913                       # Number of floating instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_writes             80927                       # Number of floating instruction queue writes
+system.cpu1.iq.fu_busy_cnt                     199599                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.014169                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  10735      5.38%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      5.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                110682     55.45%     60.83% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                78182     39.17%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.int_alu_accesses              14198676                       # Number of integer alu accesses
 system.cpu1.iq.int_inst_queue_reads          49640351                       # Number of integer instruction queue reads
 system.cpu1.iq.int_inst_queue_wakeup_accesses     13686803                       # Number of integer instruction queue wakeup accesses
@@ -1107,6 +1089,24 @@ system.cpu1.iq.iqSquashedInstsExamined        2199611                       # Nu
 system.cpu1.iq.iqSquashedInstsIssued            15615                       # Number of squashed instructions issued
 system.cpu1.iq.iqSquashedNonSpecRemoved        360700                       # Number of squashed non-spec instructions that were removed
 system.cpu1.iq.iqSquashedOperandsExamined      1165068                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.issued_per_cycle::samples     21414036                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.657855                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.314285                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           15246065     71.20%     71.20% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            2762432     12.90%     84.10% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            1149877      5.37%     89.47% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             942390      4.40%     93.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             699267      3.27%     97.13% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             379191      1.77%     98.90% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             160390      0.75%     99.65% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              52788      0.25%     99.90% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              21636      0.10%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       21414036                       # Number of insts issued each cycle
+system.cpu1.iq.rate                          0.574958                       # Inst issue rate
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_hits                           0                       # DTB hits
@@ -1209,25 +1209,25 @@ system.cpu1.misc_regfile_writes                221749                       # nu
 system.cpu1.numCycles                        24501486                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.rename.RENAME:BlockCycles         2575160                       # Number of cycles rename is blocking
-system.cpu1.rename.RENAME:CommittedMaps       9194083                       # Number of HB maps that are committed
-system.cpu1.rename.RENAME:IQFullEvents         253610                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.RENAME:IdleCycles          9125188                       # Number of cycles rename is idle
-system.cpu1.rename.RENAME:LSQFullEvents         96900                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RENAME:ROBFullEvents           103                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.RENAME:RenameLookups      20382349                       # Number of register rename lookups that rename has made
-system.cpu1.rename.RENAME:RenamedInsts       16583054                       # Number of instructions processed by rename
-system.cpu1.rename.RENAME:RenamedOperands     11154403                       # Number of destination operands rename has renamed
-system.cpu1.rename.RENAME:RunCycles           2970670                       # Number of cycles rename is running
-system.cpu1.rename.RENAME:SquashCycles         401676                       # Number of cycles rename is squashing
-system.cpu1.rename.RENAME:UnblockCycles        911632                       # Number of cycles rename is unblocking
-system.cpu1.rename.RENAME:UndoneMaps          1960318                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.RENAME:fp_rename_lookups       113596                       # Number of floating rename lookups
-system.cpu1.rename.RENAME:int_rename_lookups     20268753                       # Number of integer rename lookups
-system.cpu1.rename.RENAME:serializeStallCycles      5429708                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RENAME:serializingInsts       475094                       # count of serializing insts renamed
-system.cpu1.rename.RENAME:skidInsts           2839642                       # count of insts added to the skid buffer
-system.cpu1.rename.RENAME:tempSerializingInsts        40509                       # count of temporary serializing insts renamed
+system.cpu1.rename.BlockCycles                2575160                       # Number of cycles rename is blocking
+system.cpu1.rename.CommittedMaps              9194083                       # Number of HB maps that are committed
+system.cpu1.rename.IQFullEvents                253610                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.IdleCycles                 9125188                       # Number of cycles rename is idle
+system.cpu1.rename.LSQFullEvents                96900                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.ROBFullEvents                  103                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.RenameLookups             20382349                       # Number of register rename lookups that rename has made
+system.cpu1.rename.RenamedInsts              16583054                       # Number of instructions processed by rename
+system.cpu1.rename.RenamedOperands           11154403                       # Number of destination operands rename has renamed
+system.cpu1.rename.RunCycles                  2970670                       # Number of cycles rename is running
+system.cpu1.rename.SquashCycles                401676                       # Number of cycles rename is squashing
+system.cpu1.rename.UnblockCycles               911632                       # Number of cycles rename is unblocking
+system.cpu1.rename.UndoneMaps                 1960318                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.fp_rename_lookups           113596                       # Number of floating rename lookups
+system.cpu1.rename.int_rename_lookups        20268753                       # Number of integer rename lookups
+system.cpu1.rename.serializeStallCycles       5429708                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.serializingInsts            475094                       # count of serializing insts renamed
+system.cpu1.rename.skidInsts                  2839642                       # count of insts added to the skid buffer
+system.cpu1.rename.tempSerializingInsts         40509                       # count of temporary serializing insts renamed
 system.cpu1.rob.rob_reads                    36377887                       # The number of ROB reads
 system.cpu1.rob.rob_writes                   31956605                       # The number of ROB writes
 system.cpu1.timesIdled                         286877                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -1307,8 +1307,8 @@ system.iocache.demand_mshr_misses               41727                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.012954                       # Average percentage of cache occupancy
 system.iocache.occ_blocks::1                 0.207263                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.012954                       # Average percentage of cache occupancy
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              41727                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
@@ -1483,12 +1483,12 @@ system.l2c.demand_mshr_misses                  434897                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.158827                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.036596                       # Average percentage of cache occupancy
-system.l2c.occ_%::2                          0.351892                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                 10408.866153                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                  2398.359333                       # Average occupied blocks per context
 system.l2c.occ_blocks::2                 23061.577659                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.158827                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.036596                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.351892                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                1877438                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                 550694                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index 3773b1a35..2121232b8 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -50,6 +50,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index b2f6462f2..4d6dea231 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 22:48:41
-M5 started Mar 17 2011 22:50:11
-M5 executing on zizzer
+M5 compiled Apr 19 2011 12:17:36
+M5 started Apr 19 2011 12:17:43
+M5 executing on maize
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index dddaa888b..3f1d069d1 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 125213                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 294244                       # Number of bytes of host memory used
-host_seconds                                   424.00                       # Real time elapsed on the host
-host_tick_rate                             4395569700                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 247292                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 292024                       # Number of bytes of host memory used
+host_seconds                                   214.68                       # Real time elapsed on the host
+host_tick_rate                             8681128138                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    53089625                       # Number of instructions simulated
 sim_seconds                                  1.863702                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect             599479                       # Nu
 system.cpu.BPredUnit.condPredicted           11925971                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                 14248722                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                   975192                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches                8461745                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           1125976                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples     87254730                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.645057                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.459520                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     64129239     73.50%     73.50% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     10001511     11.46%     84.96% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2      5794569      6.64%     91.60% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      2584226      2.96%     94.56% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      1856466      2.13%     96.69% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5       706744      0.81%     97.50% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6       418456      0.48%     97.98% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       637543      0.73%     98.71% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      1125976      1.29%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total     87254730                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                  56284256                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                 324451                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls           744594                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts              52122555                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                   9113387                       # Number of loads committed
-system.cpu.commit.COM:membars                  227959                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   15505823                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts            769874                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                    8461745                       # Number of branches committed
+system.cpu.commit.bw_lim_events               1125976                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts       56284256                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls          667734                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts         8032073                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples     87254730                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.645057                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.459520                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     64129239     73.50%     73.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     10001511     11.46%     84.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      5794569      6.64%     91.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2584226      2.96%     94.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1856466      2.13%     96.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       706744      0.81%     97.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       418456      0.48%     97.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       637543      0.73%     98.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1125976      1.29%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     87254730                       # Number of insts commited each cycle
+system.cpu.commit.count                      56284256                       # Number of instructions committed
+system.cpu.commit.fp_insts                     324451                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls               744594                       # Number of function calls committed.
+system.cpu.commit.int_insts                  52122555                       # Number of committed integer instructions.
+system.cpu.commit.loads                       9113387                       # Number of loads committed
+system.cpu.commit.membars                      227959                       # Number of memory barriers committed
+system.cpu.commit.refs                       15505823                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                    53089625                       # Number of Instructions Simulated
 system.cpu.committedInsts_total              53089625                       # Number of Instructions Simulated
 system.cpu.cpi                               2.304358                       # CPI: Cycles Per Instruction
@@ -161,8 +161,8 @@ system.cpu.dcache.demand_mshr_misses          1384507                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999992                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            511.995879                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999992                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses::0        15419136                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     15419136                       # number of overall (read+write) accesses
@@ -196,15 +196,15 @@ system.cpu.dcache.tagsinuse                511.995879                       # Cy
 system.cpu.dcache.total_refs                 12121656                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               19670000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   833416                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       36259760                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          44553                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved        598925                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts        70789187                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          37160222                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           12840041                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         1435065                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts         134914                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles         994706                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles              36259760                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                 44553                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved               598925                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts               70789187                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                 37160222                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                  12840041                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                1435065                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                134914                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles                994706                       # Number of cycles decode is unblocking
 system.cpu.dtb.data_accesses                  1263492                       # DTB accesses
 system.cpu.dtb.data_acv                           894                       # DTB access violations
 system.cpu.dtb.data_hits                     16635681                       # DTB hits
@@ -303,8 +303,8 @@ system.cpu.icache.demand_mshr_misses           993440                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.995757                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            509.827441                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.995757                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses::0         8770990                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total      8770990                       # number of overall (read+write) accesses
@@ -339,21 +339,13 @@ system.cpu.icache.total_refs                  7733869                       # To
 system.cpu.icache.warmup_cycle            23815676000                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                      201                       # number of writebacks
 system.cpu.idleCycles                        33647698                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                  9077931                       # Number of branches executed
-system.cpu.iew.EXEC:nop                       3561617                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.466022                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     16730349                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                    6619936                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                  36206464                       # num instructions consuming a value
-system.cpu.iew.WB:count                      56518708                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.749991                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                  27154531                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.461990                       # insts written-back per cycle
-system.cpu.iew.WB:sent                       56632372                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts               834392                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                  9077931                       # Number of branches executed
+system.cpu.iew.exec_nop                       3561617                       # number of nop insts executed
+system.cpu.iew.exec_rate                     0.466022                       # Inst execution rate
+system.cpu.iew.exec_refs                     16730349                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                    6619936                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                 9479709                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts              10494692                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts            1785178                       # Number of dispatched non-speculative instructions
@@ -381,103 +373,93 @@ system.cpu.iew.lsq.thread.0.squashedStores       456751                       #
 system.cpu.iew.memOrderViolationEvents          18985                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       404859                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect         429533                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                  36206464                       # num instructions consuming a value
+system.cpu.iew.wb_count                      56518708                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.749991                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                  27154531                       # num instructions producing a value
+system.cpu.iew.wb_rate                       0.461990                       # insts written-back per cycle
+system.cpu.iew.wb_sent                       56632372                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                 74751539                       # number of integer regfile reads
 system.cpu.int_regfile_writes                40782350                       # number of integer regfile writes
 system.cpu.ipc                               0.433960                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.433960                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass         7281      0.01%      0.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu        39349401     68.40%     68.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult          62002      0.11%     68.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     68.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd         25611      0.04%     68.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     68.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     68.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     68.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv          3636      0.01%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     68.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       10457735     18.18%     86.75% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite       6670425     11.59%     98.34% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess       952735      1.66%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total         57528826                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                549270                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.009548                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu             45293      8.25%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                2      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      8.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead           291133     53.00%     61.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          212842     38.75%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples     88689795                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.648652                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.255048                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      61727681     69.60%     69.60% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      12782826     14.41%     84.01% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2       5739308      6.47%     90.48% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3       3779668      4.26%     94.75% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4       2566031      2.89%     97.64% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       1197199      1.35%     98.99% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6        667320      0.75%     99.74% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        163755      0.18%     99.93% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8         66007      0.07%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total     88689795                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.470247                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass              7281      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              39349401     68.40%     68.41% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                62002      0.11%     68.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd               25611      0.04%     68.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             10457735     18.18%     86.75% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6670425     11.59%     98.34% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             952735      1.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total               57528826                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                  358048                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads              686320                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses       327228                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes             333627                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                      549270                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009548                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   45293      8.25%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      2      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 291133     53.00%     61.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                212842     38.75%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses               57712767                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads          203646640                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses     56191480                       # Number of integer instruction queue wakeup accesses
@@ -489,6 +471,24 @@ system.cpu.iq.iqSquashedInstsExamined         7361535                       # Nu
 system.cpu.iq.iqSquashedInstsIssued             36245                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved        1361667                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined      3591759                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples      88689795                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.648652                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.255048                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            61727681     69.60%     69.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            12782826     14.41%     84.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5739308      6.47%     90.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3779668      4.26%     94.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2566031      2.89%     97.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1197199      1.35%     98.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6              667320      0.75%     99.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              163755      0.18%     99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               66007      0.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        88689795                       # Number of insts issued each cycle
+system.cpu.iq.rate                           0.470247                       # Inst issue rate
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
@@ -598,25 +598,25 @@ system.cpu.misc_regfile_writes                 949727                       # nu
 system.cpu.numCycles                        122337493                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         12932543                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps       38258765                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents         1039474                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          38708983                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        1241691                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents           1519                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups       81518808                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts        66985432                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands     44869849                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           12449033                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         1435065                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        4145083                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps           6611082                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups       474213                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups     81044595                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles     19019086                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts      1691185                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           11218533                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts       244825                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                12932543                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps              38258765                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                1039474                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                 38708983                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents               1241691                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                  1519                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups              81518808                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts               66985432                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands            44869849                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                  12449033                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                1435065                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles               4145083                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                  6611082                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups            474213                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups         81044595                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles       19019086                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts            1691185                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                  11218533                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts         244825                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                    150193940                       # The number of ROB reads
 system.cpu.rob.rob_writes                   130068170                       # The number of ROB writes
 system.cpu.timesIdled                         1318957                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -696,8 +696,8 @@ system.iocache.demand_mshr_misses               41725                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.080564                       # Average percentage of cache occupancy
 system.iocache.occ_blocks::1                 1.289021                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.080564                       # Average percentage of cache occupancy
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              41725                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
@@ -838,10 +838,10 @@ system.l2c.demand_mshr_misses                  424680                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.185866                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.343812                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                 12180.929780                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                 22532.084945                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.185866                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.343812                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                2395045                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2395045                       # number of overall (read+write) accesses
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index 083bb5627..98177ee67 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -11,7 +11,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t
 boot_cpu_frequency=500
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0 
 init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
+kernel=/dist/m5/system/binaries/vmlinux.arm
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
@@ -495,7 +495,7 @@ type=ExeTracer
 
 [system.diskmem]
 type=PhysicalMemory
-file=/chips/pd/randd/dist/disks/ael-arm.ext2
+file=/dist/m5/system/disks/ael-arm.ext2
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
index 83f702085..7cdd9066f 100755
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr  4 2011 11:17:23
-M5 started Apr  4 2011 11:17:27
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3
+M5 compiled Apr 19 2011 13:41:05
+M5 started Apr 19 2011 13:41:08
+M5 executing on maize
+command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 82662490500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index edd79728c..4fdec7dfb 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  92348                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 389996                       # Number of bytes of host memory used
-host_seconds                                   562.86                       # Real time elapsed on the host
-host_tick_rate                              146862568                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 182620                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 341656                       # Number of bytes of host memory used
+host_seconds                                   284.63                       # Real time elapsed on the host
+host_tick_rate                              290422658                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    51978682                       # Number of instructions simulated
 sim_seconds                                  0.082662                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect             665245                       # Nu
 system.cpu.BPredUnit.condPredicted           11246732                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                 13229511                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                   787550                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches                8445621                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events            801383                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples     93507712                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.557193                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.351787                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     71892468     76.88%     76.88% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     10568988     11.30%     88.19% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2      3427833      3.67%     91.85% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      1711600      1.83%     93.68% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      3527395      3.77%     97.46% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5       741726      0.79%     98.25% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6       541099      0.58%     98.83% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       295220      0.32%     99.14% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8       801383      0.86%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total     93507712                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                  52101862                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                   6017                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls           529734                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts              42509491                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                   9207015                       # Number of loads committed
-system.cpu.commit.COM:membars                       3                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   16293738                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts            641726                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                    8445621                       # Number of branches committed
+system.cpu.commit.bw_lim_events                801383                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts       52101862                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls         2963383                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts        16147201                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples     93507712                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.557193                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.351787                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     71892468     76.88%     76.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     10568988     11.30%     88.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3427833      3.67%     91.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1711600      1.83%     93.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3527395      3.77%     97.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       741726      0.79%     98.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       541099      0.58%     98.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       295220      0.32%     99.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8       801383      0.86%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     93507712                       # Number of insts commited each cycle
+system.cpu.commit.count                      52101862                       # Number of instructions committed
+system.cpu.commit.fp_insts                       6017                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls               529734                       # Number of function calls committed.
+system.cpu.commit.int_insts                  42509491                       # Number of committed integer instructions.
+system.cpu.commit.loads                       9207015                       # Number of loads committed
+system.cpu.commit.membars                           3                       # Number of memory barriers committed
+system.cpu.commit.refs                       16293738                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                    51978682                       # Number of Instructions Simulated
 system.cpu.committedInsts_total              51978682                       # Number of Instructions Simulated
 system.cpu.cpi                               3.180631                       # CPI: Cycles Per Instruction
@@ -148,8 +148,8 @@ system.cpu.dcache.demand_mshr_misses           419458                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999513                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            511.750765                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999513                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses::0        16095916                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     16095916                       # number of overall (read+write) accesses
@@ -183,15 +183,15 @@ system.cpu.dcache.tagsinuse                511.750765                       # Cy
 system.cpu.dcache.total_refs                 13775411                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               48224000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   391506                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       53936622                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          70601                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved       1224137                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts        76419738                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          23948605                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           14435253                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         2568567                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts         235986                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles        1187204                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles              53936622                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                 70601                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved              1224137                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts               76419738                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                 23948605                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                  14435253                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                2568567                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                235986                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles               1187204                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                      35246983                       # DTB accesses
 system.cpu.dtb.align_faults                      1461                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -299,8 +299,8 @@ system.cpu.icache.demand_mshr_misses           502982                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.970025                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            496.652768                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.970025                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses::0         6553557                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total      6553557                       # number of overall (read+write) accesses
@@ -335,21 +335,13 @@ system.cpu.icache.total_refs                  6005950                       # To
 system.cpu.icache.warmup_cycle             6210686000                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                    41369                       # number of writebacks
 system.cpu.idleCycles                        69248731                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 10230019                       # Number of branches executed
-system.cpu.iew.EXEC:nop                        166886                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.475904                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     35985354                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                    7801149                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                  62345618                       # num instructions consuming a value
-system.cpu.iew.WB:count                      60884415                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.509768                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                  31781773                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.368271                       # insts written-back per cycle
-system.cpu.iew.WB:sent                       78152559                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts               711242                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                 10230019                       # Number of branches executed
+system.cpu.iew.exec_nop                        166886                       # number of nop insts executed
+system.cpu.iew.exec_rate                     0.475904                       # Inst execution rate
+system.cpu.iew.exec_refs                     35985354                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                    7801149                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                21406073                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts              12848037                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts            4002488                       # Number of dispatched non-speculative instructions
@@ -377,103 +369,93 @@ system.cpu.iew.lsq.thread.0.squashedStores      1649637                       #
 system.cpu.iew.memOrderViolationEvents         280540                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       186102                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect         525140                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                  62345618                       # num instructions consuming a value
+system.cpu.iew.wb_count                      60884415                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.509768                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                  31781773                       # num instructions producing a value
+system.cpu.iew.wb_rate                       0.368271                       # insts written-back per cycle
+system.cpu.iew.wb_sent                       78152559                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                182840055                       # number of integer regfile reads
 system.cpu.int_regfile_writes                43911822                       # number of integer regfile writes
 system.cpu.ipc                               0.314403                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.314403                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass      2393207      3.00%      3.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu        40767716     51.13%     54.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult          71906      0.09%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc            10      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            6      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc          895      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            6      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     54.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       28538408     35.79%     90.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite       7966700      9.99%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total         79738854                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               4821847                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.060470                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu              5252      0.11%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                1      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          4503965     93.41%     93.52% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          312629      6.48%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples     96076251                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.829954                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.379344                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      59918658     62.37%     62.37% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      16598524     17.28%     79.64% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2       7253913      7.55%     87.19% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3       4126106      4.29%     91.49% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4       5947858      6.19%     97.68% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       1304063      1.36%     99.04% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6        619735      0.65%     99.68% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        235123      0.24%     99.92% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8         72271      0.08%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total     96076251                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.482316                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass           2393207      3.00%      3.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              40767716     51.13%     54.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                71906      0.09%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                  10      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               6      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc            895      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             28538408     35.79%     90.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7966700      9.99%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total               79738854                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                    8555                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads               16356                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses         6330                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes               9324                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                     4821847                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.060470                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                    5252      0.11%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      1      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                4503965     93.41%     93.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                312629      6.48%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses               82158939                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads          260560114                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses     60878085                       # Number of integer instruction queue wakeup accesses
@@ -485,6 +467,24 @@ system.cpu.iq.iqSquashedInstsExamined        17660461                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            127886                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved        1069030                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined     22275203                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples      96076251                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.829954                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.379344                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            59918658     62.37%     62.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            16598524     17.28%     79.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7253913      7.55%     87.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             4126106      4.29%     91.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             5947858      6.19%     97.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1304063      1.36%     99.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6              619735      0.65%     99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              235123      0.24%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               72271      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        96076251                       # Number of insts issued each cycle
+system.cpu.iq.rate                           0.482316                       # Inst issue rate
 system.cpu.itb.accesses                       6566505                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -517,25 +517,25 @@ system.cpu.misc_regfile_writes                 505947                       # nu
 system.cpu.numCycles                        165324982                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         33112132                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps       36741742                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents          775024                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          25585942                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        2464411                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents         439406                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups      190546426                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts        73652077                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands     53332963                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           13017560                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         2568567                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        5444932                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          16591220                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups        49319                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups    190497107                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles     16347118                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts       812559                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           14268469                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts       662925                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                33112132                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps              36741742                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                 775024                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                 25585942                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents               2464411                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                439406                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups             190546426                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts               73652077                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands            53332963                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                  13017560                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                2568567                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles               5444932                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                 16591220                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups             49319                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups        190497107                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles       16347118                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts             812559                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                  14268469                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts         662925                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                    160015001                       # The number of ROB reads
 system.cpu.rob.rob_writes                   139111158                       # The number of ROB writes
 system.cpu.timesIdled                         1092841                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -705,10 +705,10 @@ system.l2c.demand_mshr_misses                  128445                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.099470                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.481649                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                  6518.840874                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                 31565.358061                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.099470                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.481649                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                 923785                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                 102462                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            1026247                       # number of overall (read+write) accesses
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
index cffda2d37..f27ebe211 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
@@ -1 +1 @@
-build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 FAILED!
+build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 FAILED!
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
index f89b48399..049d7897c 100644
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -498,9 +498,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/arm/scratch/alisai01/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
index 9a7a71365..6a4d20d87 100755
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 17:54:33
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 12:49:23
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 365ff8ea3..9f9cc3407 100644
--- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 190258                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 391364                       # Number of bytes of host memory used
-host_seconds                                   479.61                       # Real time elapsed on the host
-host_tick_rate                               93397782                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 230945                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 347768                       # Number of bytes of host memory used
+host_seconds                                   395.11                       # Real time elapsed on the host
+host_tick_rate                              113371387                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91249905                       # Number of instructions simulated
 sim_seconds                                  0.044795                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect            1596208                       # Nu
 system.cpu.BPredUnit.condPredicted           23792873                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                 29586235                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                    63032                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               18722470                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events            671558                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples     84101876                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.085142                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.487392                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     39810013     47.34%     47.34% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     21942954     26.09%     73.43% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2      9544341     11.35%     84.77% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      7643789      9.09%     93.86% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      2702545      3.21%     97.08% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5       240327      0.29%     97.36% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6       909211      1.08%     98.44% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       637138      0.76%     99.20% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8       671558      0.80%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total     84101876                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                  91262514                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                     48                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls            56148                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts              72533318                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                  22575876                       # Number of loads committed
-system.cpu.commit.COM:membars                    3888                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   27322629                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts           1599456                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                   18722470                       # Number of branches committed
+system.cpu.commit.bw_lim_events                671558                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts       91262514                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls          554406                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts        37771309                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples     84101876                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.085142                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.487392                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     39810013     47.34%     47.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     21942954     26.09%     73.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      9544341     11.35%     84.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      7643789      9.09%     93.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2702545      3.21%     97.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       240327      0.29%     97.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       909211      1.08%     98.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       637138      0.76%     99.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8       671558      0.80%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     84101876                       # Number of insts commited each cycle
+system.cpu.commit.count                      91262514                       # Number of instructions committed
+system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls                56148                       # Number of function calls committed.
+system.cpu.commit.int_insts                  72533318                       # Number of committed integer instructions.
+system.cpu.commit.loads                      22575876                       # Number of loads committed
+system.cpu.commit.membars                        3888                       # Number of memory barriers committed
+system.cpu.commit.refs                       27322629                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                    91249905                       # Number of Instructions Simulated
 system.cpu.committedInsts_total              91249905                       # Number of Instructions Simulated
 system.cpu.cpi                               0.981803                       # CPI: Cycles Per Instruction
@@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses           950233                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.852828                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           3493.184851                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.852828                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           29231190                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency  8180.869220                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  3273.127173                       # average overall mshr miss latency
@@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse               3493.184851                       # Cy
 system.cpu.dcache.total_refs                 28069666                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle            18896443000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   943153                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       17588781                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred           9537                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved       4762375                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts       139874563                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          32956661                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           32742845                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         5457924                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts          30438                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles         813588                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles              17588781                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                  9537                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved              4762375                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts              139874563                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                 32956661                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                  32742845                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                5457924                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                 30438                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles                813588                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses              674                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.277518                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            568.356083                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.277518                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           15336543                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 35886.138614                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 34397.626113                       # average overall mshr miss latency
@@ -245,21 +245,13 @@ system.cpu.icache.total_refs                 15335735                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                           29674                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 20951910                       # Number of branches executed
-system.cpu.iew.EXEC:nop                         39919                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.157669                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     30258239                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                    5196792                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 127150055                       # num instructions consuming a value
-system.cpu.iew.WB:count                     102173263                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.489247                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                  62207806                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.140461                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      102563540                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts              1809783                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                 20951910                       # Number of branches executed
+system.cpu.iew.exec_nop                         39919                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.157669                       # Inst execution rate
+system.cpu.iew.exec_refs                     30258239                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                    5196792                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                  316819                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts              31496278                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts             689079                       # Number of dispatched non-speculative instructions
@@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores      1867594                       #
 system.cpu.iew.memOrderViolationEvents          14224                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       282853                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        1526930                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                 127150055                       # num instructions consuming a value
+system.cpu.iew.wb_count                     102173263                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.489247                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                  62207806                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.140461                       # insts written-back per cycle
+system.cpu.iew.wb_sent                      102563540                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                259728905                       # number of integer regfile reads
 system.cpu.int_regfile_writes                80595212                       # number of integer regfile writes
 system.cpu.ipc                               1.018534                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.018534                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu        74250134     70.21%     70.21% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult          10532      0.01%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            1      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt           27      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc           46      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            5      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     70.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       26236363     24.81%     95.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite       5264077      4.98%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        105761185                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                177153                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.001675                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu             40759     23.01%     23.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult               27      0.02%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     23.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead            78448     44.28%     67.31% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite           57919     32.69%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples     89559799                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.180900                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.457109                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      38412400     42.89%     42.89% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      23501864     26.24%     69.13% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      14299372     15.97%     85.10% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3       6452092      7.20%     92.30% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4       2377583      2.65%     94.96% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       2675567      2.99%     97.94% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       1597319      1.78%     99.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        116596      0.13%     99.86% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        127006      0.14%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total     89559799                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.180509                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              74250134     70.21%     70.21% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                10532      0.01%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              27      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc             46      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            5      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26236363     24.81%     95.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5264077      4.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              105761185                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                     110                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                 216                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           99                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                196                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                      177153                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.001675                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   40759     23.01%     23.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     27      0.02%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     23.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                  78448     44.28%     67.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                 57919     32.69%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses              105938228                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads          301287282                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses    102173164                       # Number of integer instruction queue wakeup accesses
@@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined        37472339                       # Nu
 system.cpu.iq.iqSquashedInstsIssued             28176                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved         139525                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined     69343981                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples      89559799                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.180900                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.457109                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            38412400     42.89%     42.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            23501864     26.24%     69.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            14299372     15.97%     85.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6452092      7.20%     92.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2377583      2.65%     94.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2675567      2.99%     97.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1597319      1.78%     99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              116596      0.13%     99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              127006      0.14%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        89559799                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.180509                       # Inst issue rate
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -468,10 +468,10 @@ system.cpu.l2cache.demand_mshr_misses           15537                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.012381                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.250026                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           405.690928                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1          8192.856570                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.012381                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.250026                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            950905                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34233.211115                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31042.833237                       # average overall mshr miss latency
@@ -502,28 +502,28 @@ system.cpu.misc_regfile_writes                  11602                       # nu
 system.cpu.numCycles                         89589473                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles          2558009                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps       71576967                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents         2891853                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          35560664                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        1952065                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents             58                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups      350271207                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       135568411                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    105865304                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           30904016                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         5457924                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        5891977                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          34288334                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups          787                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups    350270420                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles      9187209                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts       701223                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           13035103                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts       702184                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                 2558009                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps              71576967                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                2891853                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                 35560664                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents               1952065                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                    58                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups             350271207                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts              135568411                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands           105865304                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                  30904016                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                5457924                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles               5891977                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                 34288334                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups               787                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups        350270420                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles        9187209                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts             701223                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                  13035103                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts         702184                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                    212458407                       # The number of ROB reads
 system.cpu.rob.rob_writes                   263525841                       # The number of ROB writes
 system.cpu.timesIdled                            1433                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls             442                       # Number of system calls
+system.cpu.workload.num_syscalls                  442                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
index 2f887d410..a584d29ed 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -61,14 +61,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
index d4df9bd55..778a5635d 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 17:54:34
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 12:50:38
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index 4aa89302d..857cf86ba 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 950960                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 379668                       # Number of bytes of host memory used
-host_seconds                                    95.96                       # Real time elapsed on the host
-host_tick_rate                              565248287                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3623403                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 338784                       # Number of bytes of host memory used
+host_seconds                                    25.18                       # Real time elapsed on the host
+host_tick_rate                             2153732946                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91252969                       # Number of instructions simulated
 sim_seconds                                  0.054241                       # Number of seconds simulated
@@ -71,6 +71,6 @@ system.cpu.num_int_register_writes           70993656                       # nu
 system.cpu.num_load_insts                    22573967                       # Number of load instructions
 system.cpu.num_mem_refs                      27318811                       # number of memory refs
 system.cpu.num_store_insts                    4744844                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             442                       # Number of system calls
+system.cpu.workload.num_syscalls                  442                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
index 9fe66a752..b43580bea 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -164,14 +164,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
index 4622f4ee0..ce41a8bab 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 17:54:34
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 12:51:14
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 389bae1e3..6b71bf251 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 492863                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 387392                       # Number of bytes of host memory used
-host_seconds                                   185.09                       # Real time elapsed on the host
-host_tick_rate                              800055292                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2007081                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 346528                       # Number of bytes of host memory used
+host_seconds                                    45.45                       # Real time elapsed on the host
+host_tick_rate                             3258049978                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91226321                       # Number of instructions simulated
 sim_seconds                                  0.148086                       # Number of seconds simulated
@@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses           946798                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.871228                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           3568.549501                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.871228                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           27284389                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 14657.859438                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
@@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses              599                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.249187                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            510.335448                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.249187                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          107830780                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 54527.545910                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
@@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses           15408                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.009921                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.271918                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           325.097811                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1          8910.209882                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.009921                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.271918                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            947397                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -264,6 +264,6 @@ system.cpu.num_int_register_writes           70993656                       # nu
 system.cpu.num_load_insts                    22573967                       # Number of load instructions
 system.cpu.num_mem_refs                      27318811                       # number of memory refs
 system.cpu.num_store_insts                    4744844                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             442                       # Number of system calls
+system.cpu.workload.num_syscalls                  442                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
index a011c886e..a5435dfc1 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:14:01
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:20:18
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index 282686242..5f734ed46 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1159873                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 351876                       # Number of bytes of host memory used
-host_seconds                                   210.23                       # Real time elapsed on the host
-host_tick_rate                              581353978                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4484533                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 329760                       # Number of bytes of host memory used
+host_seconds                                    54.37                       # Real time elapsed on the host
+host_tick_rate                             2247743371                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   243835278                       # Number of instructions simulated
 sim_seconds                                  0.122216                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes          215451609                       # nu
 system.cpu.num_load_insts                    82803522                       # Number of load instructions
 system.cpu.num_mem_refs                     105711442                       # number of memory refs
 system.cpu.num_store_insts                   22907920                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             443                       # Number of system calls
+system.cpu.workload.num_syscalls                  443                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
index dd7acffe5..a1bafa0cb 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
index 280cd1a31..e8a8f1145 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:13:48
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:19:52
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 1b0d7fe21..3eb9bf1a6 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 483058                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 359588                       # Number of bytes of host memory used
-host_seconds                                   504.77                       # Real time elapsed on the host
-host_tick_rate                              718005180                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2305909                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 337512                       # Number of bytes of host memory used
+host_seconds                                   105.74                       # Real time elapsed on the host
+host_tick_rate                             3427441926                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   243835278                       # Number of instructions simulated
 sim_seconds                                  0.362431                       # Number of seconds simulated
@@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses           939567                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.870074                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           3563.824259                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.870074                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          105122385                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 14660.150899                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899                       # average overall mshr miss latency
@@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses              882                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.354281                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            725.567632                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.354281                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          244421512                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55857.142857                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857                       # average overall mshr miss latency
@@ -183,10 +183,10 @@ system.cpu.l2cache.demand_mshr_misses           15648                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.011460                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.270424                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           375.506440                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1          8861.245791                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.011460                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.270424                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            940453                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -228,6 +228,6 @@ system.cpu.num_int_register_writes          215451608                       # nu
 system.cpu.num_load_insts                    82803522                       # Number of load instructions
 system.cpu.num_mem_refs                     105711442                       # number of memory refs
 system.cpu.num_store_insts                   22907920                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             443                       # Number of system calls
+system.cpu.workload.num_syscalls                  443                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
index 1f2e75864..de48f92fd 100644
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
index 2b45d7376..c33237447 100755
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 18 2011 20:12:06
-M5 started Mar 18 2011 20:12:16
-M5 executing on zizzer
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:30:19
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 2d839c8d9..6bc8ba293 100644
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 173311                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 350460                       # Number of bytes of host memory used
-host_seconds                                  1605.16                       # Real time elapsed on the host
-host_tick_rate                               50708988                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 265187                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 346300                       # Number of bytes of host memory used
+host_seconds                                  1049.04                       # Real time elapsed on the host
+host_tick_rate                               77591071                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   278192519                       # Number of instructions simulated
 sim_seconds                                  0.081396                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect            2465320                       # Nu
 system.cpu.BPredUnit.condPredicted           43504790                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                 43504790                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               29309710                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          13548841                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    149131695                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.865415                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     2.481905                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     63516016     42.59%     42.59% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     27005826     18.11%     60.70% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     19486009     13.07%     73.77% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     13132636      8.81%     82.57% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      4245933      2.85%     85.42% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      3434891      2.30%     87.72% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6      3062949      2.05%     89.78% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      1698594      1.14%     90.91% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     13548841      9.09%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    149131695                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                 278192519                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                     40                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts             278186227                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                  90779388                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  122219139                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts           2465329                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                   29309710                       # Number of branches committed
+system.cpu.commit.bw_lim_events              13548841                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts      278192519                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls             446                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts        88842299                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples    149131695                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.865415                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.481905                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     63516016     42.59%     42.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     27005826     18.11%     60.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     19486009     13.07%     73.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     13132636      8.81%     82.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4245933      2.85%     85.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      3434891      2.30%     87.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3062949      2.05%     89.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1698594      1.14%     90.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     13548841      9.09%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    149131695                       # Number of insts commited each cycle
+system.cpu.commit.count                     278192519                       # Number of instructions committed
+system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.int_insts                 278186227                       # Number of committed integer instructions.
+system.cpu.commit.loads                      90779388                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                      122219139                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                   278192519                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             278192519                       # Number of Instructions Simulated
 system.cpu.cpi                               0.585179                       # CPI: Cycles Per Instruction
@@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses          2078004                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.994940                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4075.274681                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.994940                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           94785588                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency  7490.439865                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  3562.354617                       # average overall mshr miss latency
@@ -119,12 +119,12 @@ system.cpu.dcache.tagsinuse               4075.274681                       # Cy
 system.cpu.dcache.total_refs                 92329423                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle            30396735000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                  1448011                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       13645155                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts       390459172                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          68124952                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           66154578                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        12492114                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles        1207010                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles              13645155                       # Number of cycles decode is blocked
+system.cpu.decode.DecodedInsts              390459172                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                 68124952                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                  66154578                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles               12492114                       # Number of cycles decode is squashing
+system.cpu.decode.UnblockCycles               1207010                       # Number of cycles decode is unblocking
 system.cpu.fetch.Branches                    43504790                       # Number of branches that fetch encountered
 system.cpu.fetch.CacheLines                  30855910                       # Number of cache lines fetched
 system.cpu.fetch.Cycles                      71218247                       # Number of cycles fetch has run and was not squashing or blocked
@@ -188,8 +188,8 @@ system.cpu.icache.demand_mshr_misses             1013                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.396500                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            812.031019                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.396500                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           30855910                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 36182.458888                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 35209.772952                       # average overall mshr miss latency
@@ -212,21 +212,13 @@ system.cpu.icache.total_refs                 30854633                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                         1168640                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 32808514                       # Number of branches executed
-system.cpu.iew.EXEC:nop                             0                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     2.009454                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    141715314                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   34352421                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 330470543                       # num instructions consuming a value
-system.cpu.iew.WB:count                     324204287                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.735351                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                 243011799                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.991519                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      325408414                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts              2866285                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                 32808514                       # Number of branches executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_rate                     2.009454                       # Inst execution rate
+system.cpu.iew.exec_refs                    141715314                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                   34352421                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                  739357                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts             121527888                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                465                       # Number of dispatched non-speculative instructions
@@ -254,103 +246,93 @@ system.cpu.iew.lsq.thread.0.squashedStores      8203432                       #
 system.cpu.iew.memOrderViolationEvents         237293                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       582972                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        2283313                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                 330470543                       # num instructions consuming a value
+system.cpu.iew.wb_count                     324204287                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.735351                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                 243011799                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.991519                       # insts written-back per cycle
+system.cpu.iew.wb_sent                      325408414                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                572686347                       # number of integer regfile reads
 system.cpu.int_regfile_writes               291536884                       # number of integer regfile writes
 system.cpu.ipc                               1.708879                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.708879                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass        16703      0.01%      0.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       188329198     56.76%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd            16      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      108641887     32.74%     89.51% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      34821337     10.49%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        331809141                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               1744992                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.005259                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu             20475      1.17%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          1576903     90.37%     91.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          147614      8.46%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    161623809                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     2.052972                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.792191                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      44438080     27.49%     27.49% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      26560474     16.43%     43.93% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      27560184     17.05%     60.98% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3      26726118     16.54%     77.52% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      19530475     12.08%     89.60% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      11104171      6.87%     96.47% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       3863575      2.39%     98.86% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       1600116      0.99%     99.85% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        240616      0.15%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    161623809                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     2.038234                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass             16703      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             188329198     56.76%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  16      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            108641887     32.74%     89.51% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            34821337     10.49%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              331809141                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                     101                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                 208                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           80                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                238                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                     1744992                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.005259                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   20475      1.17%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1576903     90.37%     91.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                147614      8.46%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses              333537329                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads          827162429                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses    324204207                       # Number of integer instruction queue wakeup accesses
@@ -362,6 +344,24 @@ system.cpu.iq.iqSquashedInstsExamined        88592670                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            175554                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             19                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined    124945161                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples     161623809                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.052972                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.792191                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            44438080     27.49%     27.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            26560474     16.43%     43.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            27560184     17.05%     60.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            26726118     16.54%     77.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            19530475     12.08%     89.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            11104171      6.87%     96.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             3863575      2.39%     98.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1600116      0.99%     99.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              240616      0.15%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       161623809                       # Number of insts issued each cycle
+system.cpu.iq.rate                           2.038234                       # Inst issue rate
 system.cpu.l2cache.ReadExReq_accesses          106011                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34192.017786                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31115.893095                       # average ReadExReq mshr miss latency
@@ -413,10 +413,10 @@ system.cpu.l2cache.demand_mshr_misses           76519                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.196368                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.354446                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          6434.571377                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         11614.477696                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.196368                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.354446                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           2079015                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34202.596741                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31074.223395                       # average overall mshr miss latency
@@ -446,28 +446,28 @@ system.cpu.misc_regfile_reads               211169577                       # nu
 system.cpu.numCycles                        162792449                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles          3023364                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps      248344192                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents          130274                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          72054036                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        9710787                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents             12                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups      941229334                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       383108308                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    343773743                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           63044913                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        12492114                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       11002939                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          95429551                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups          586                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups    941228748                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles         6443                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts          468                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           25868384                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts          462                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                 3023364                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps             248344192                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                 130274                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                 72054036                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents               9710787                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                    12                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups             941229334                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts              383108308                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands           343773743                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                  63044913                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles               12492114                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles              11002939                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                 95429551                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups               586                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups        941228748                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles           6443                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts                468                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                  25868384                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts            462                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                    502617672                       # The number of ROB reads
 system.cpu.rob.rob_writes                   746575877                       # The number of ROB writes
 system.cpu.timesIdled                           40062                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls             444                       # Number of system calls
+system.cpu.workload.num_syscalls                  444                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
index 2aa2852be..0d61b002c 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb  8 2011 00:58:34
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:39:34
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index aacdb2309..ed3183ec3 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1568972                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 358500                       # Number of bytes of host memory used
-host_seconds                                   177.31                       # Real time elapsed on the host
-host_tick_rate                              952856596                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3107267                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 337076                       # Number of bytes of host memory used
+host_seconds                                    89.53                       # Real time elapsed on the host
+host_tick_rate                             1887081425                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   278192520                       # Number of instructions simulated
 sim_seconds                                  0.168950                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes          248344166                       # nu
 system.cpu.num_load_insts                    90779388                       # Number of load instructions
 system.cpu.num_mem_refs                     122219139                       # number of memory refs
 system.cpu.num_store_insts                   31439751                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             444                       # Number of system calls
+system.cpu.workload.num_syscalls                  444                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
index 12f3ad44d..2184f1531 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
index 56b5fe9df..1d6e35c6c 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb  8 2011 00:58:34
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:41:14
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
index e90dea7b7..e994cf670 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1018906                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 366224                       # Number of bytes of host memory used
-host_seconds                                   273.03                       # Real time elapsed on the host
-host_tick_rate                             1355197592                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1776708                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 344820                       # Number of bytes of host memory used
+host_seconds                                   156.58                       # Real time elapsed on the host
+host_tick_rate                             2363113199                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   278192520                       # Number of instructions simulated
 sim_seconds                                  0.370011                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses          2066829                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.995279                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4076.661903                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995279                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          122219201                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 15539.675029                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303                       # average overall mshr miss latency
@@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses              808                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.325289                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            666.191948                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.325289                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          217696209                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses           76575                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.199945                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.368128                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          6551.798271                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         12062.804989                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.199945                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.368128                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           2067637                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 52000.385243                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -218,6 +218,6 @@ system.cpu.num_int_register_writes          248344166                       # nu
 system.cpu.num_load_insts                    90779388                       # Number of load instructions
 system.cpu.num_mem_refs                     122219139                       # number of memory refs
 system.cpu.num_store_insts                   31439751                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             444                       # Number of system calls
+system.cpu.workload.num_syscalls                  444                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
index 4b915cedf..91e8c0469 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -498,9 +498,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/arm/scratch/alisai01/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
index ce3065a66..092b47dee 100755
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 17:54:34
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 12:52:10
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
index a263a0962..8a2f1e243 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 134709                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 264692                       # Number of bytes of host memory used
-host_seconds                                  4256.17                       # Real time elapsed on the host
-host_tick_rate                               78176241                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 191028                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 221120                       # Number of bytes of host memory used
+host_seconds                                  3001.36                       # Real time elapsed on the host
+host_tick_rate                              110860138                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   573342397                       # Number of instructions simulated
 sim_seconds                                  0.332731                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect           18809964                       # Nu
 system.cpu.BPredUnit.condPredicted          186338321                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                233659814                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                 11860569                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches              120192362                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           6858146                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    603587786                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.952117                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.448029                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    310030081     51.36%     51.36% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    161983498     26.84%     78.20% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     68757792     11.39%     89.59% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     25709435      4.26%     93.85% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     17326011      2.87%     96.72% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      5210197      0.86%     97.59% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6      6149685      1.02%     98.60% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      1562941      0.26%     98.86% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      6858146      1.14%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    603587786                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                 574686281                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                     16                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls          9757362                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts             473702185                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                 126773177                       # Number of loads committed
-system.cpu.commit.COM:membars                 1488542                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  184377275                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts          20926821                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                  120192362                       # Number of branches committed
+system.cpu.commit.bw_lim_events               6858146                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts      574686281                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls         3877893                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts       381923221                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples    603587786                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.952117                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.448029                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    310030081     51.36%     51.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    161983498     26.84%     78.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     68757792     11.39%     89.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     25709435      4.26%     93.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     17326011      2.87%     96.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      5210197      0.86%     97.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      6149685      1.02%     98.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1562941      0.26%     98.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6858146      1.14%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    603587786                       # Number of insts commited each cycle
+system.cpu.commit.count                     574686281                       # Number of instructions committed
+system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
+system.cpu.commit.int_insts                 473702185                       # Number of committed integer instructions.
+system.cpu.commit.loads                     126773177                       # Number of loads committed
+system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
+system.cpu.commit.refs                      184377275                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                   573342397                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             573342397                       # Number of Instructions Simulated
 system.cpu.cpi                               1.160672                       # CPI: Cycles Per Instruction
@@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses          1195995                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.991470                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4061.060335                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.991470                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          197693380                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 13396.562604                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  8735.502239                       # average overall mshr miss latency
@@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse               4061.060335                       # Cy
 system.cpu.dcache.total_refs                200083704                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             6358781000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                  1064793                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       85842380                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          76871                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved      34367828                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts      1126968144                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         277630014                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          236143765                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        57332647                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts         218235                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles        3971626                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles              85842380                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                 76871                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved             34367828                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts             1126968144                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                277630014                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                 236143765                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles               57332647                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                218235                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles               3971626                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -220,8 +220,8 @@ system.cpu.icache.demand_mshr_misses            13895                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.514415                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1053.520934                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.514415                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          132169265                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 14331.781024                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 10612.450522                       # average overall mshr miss latency
@@ -244,21 +244,13 @@ system.cpu.icache.total_refs                132154335                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        4                       # number of writebacks
 system.cpu.idleCycles                         4542007                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                142399885                       # Number of branches executed
-system.cpu.iew.EXEC:nop                       9420990                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.051214                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    220838036                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   66554903                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 782273717                       # num instructions consuming a value
-system.cpu.iew.WB:count                     680637923                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.486169                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                 380317186                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.022804                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      691183006                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts             25100140                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                142399885                       # Number of branches executed
+system.cpu.iew.exec_nop                       9420990                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.051214                       # Inst execution rate
+system.cpu.iew.exec_refs                    220838036                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                   66554903                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                 2947924                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts             196892006                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts            2816035                       # Number of dispatched non-speculative instructions
@@ -286,103 +278,93 @@ system.cpu.iew.lsq.thread.0.squashedStores     56769769                       #
 system.cpu.iew.memOrderViolationEvents         241250                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      6965983                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect       18134157                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                 782273717                       # num instructions consuming a value
+system.cpu.iew.wb_count                     680637923                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.486169                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                 380317186                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.022804                       # insts written-back per cycle
+system.cpu.iew.wb_sent                      691183006                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads               1609052037                       # number of integer regfile reads
 system.cpu.int_regfile_writes               524399004                       # number of integer regfile writes
 system.cpu.ipc                               0.861570                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.861570                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       491156775     67.76%     67.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult         386013      0.05%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd           106      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            3      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      162458896     22.41%     90.23% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      70842385      9.77%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        724844178                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               8619148                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.011891                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu             25536      0.30%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          5445227     63.18%     63.47% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite         3148385     36.53%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    660920432                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.096719                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.355430                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     305964281     46.29%     46.29% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     148313904     22.44%     68.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2     112740957     17.06%     85.79% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3      49799071      7.53%     93.33% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      29063149      4.40%     97.72% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       8262993      1.25%     98.97% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       4169807      0.63%     99.61% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       1785416      0.27%     99.88% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        820854      0.12%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    660920432                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.089234                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             491156775     67.76%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               386013      0.05%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 106      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            162458896     22.41%     90.23% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            70842385      9.77%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              724844178                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                     126                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                 248                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                340                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                     8619148                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.011891                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   25536      0.30%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5445227     63.18%     63.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3148385     36.53%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses              733463200                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads         2121563604                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses    680637907                       # Number of integer instruction queue wakeup accesses
@@ -394,6 +376,24 @@ system.cpu.iq.iqSquashedInstsExamined       371760121                       # Nu
 system.cpu.iq.iqSquashedInstsIssued           2335916                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved         799068                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined    680735331                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples     660920432                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.096719                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.355430                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           305964281     46.29%     46.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           148313904     22.44%     68.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           112740957     17.06%     85.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            49799071      7.53%     93.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            29063149      4.40%     97.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             8262993      1.25%     98.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             4169807      0.63%     99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1785416      0.27%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              820854      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       660920432                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.089234                       # Inst issue rate
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -470,10 +470,10 @@ system.cpu.l2cache.demand_mshr_misses          236073                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.216648                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.421153                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          7099.133966                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         13800.334539                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.216648                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.421153                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           1209222                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34216.723072                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31016.778708                       # average overall mshr miss latency
@@ -504,28 +504,28 @@ system.cpu.misc_regfile_writes                4464326                       # nu
 system.cpu.numCycles                        665462439                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         11783884                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps      448493735                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents         9081964                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         293899856                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents       10512591                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents            133                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     2673538298                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      1068521543                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    798521782                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          223635059                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        57332647                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       24492193                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps         350028044                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups         1141                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups   2673537157                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles     49776793                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts      2837350                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           62579735                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts      2837280                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                11783884                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps             448493735                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                9081964                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                293899856                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents              10512591                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                   133                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups            2673538298                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts             1068521543                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands           798521782                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                 223635059                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles               57332647                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles              24492193                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                350028044                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups              1141                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups       2673537157                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles       49776793                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts            2837350                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                  62579735                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts        2837280                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                   1553332004                       # The number of ROB reads
 system.cpu.rob.rob_writes                  1970603439                       # The number of ROB writes
 system.cpu.timesIdled                          108463                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls             548                       # Number of system calls
+system.cpu.workload.num_syscalls                  548                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
index 2b400c946..8b55eca4f 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -61,14 +61,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
index 1ad3a878c..7da122073 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 17:56:20
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 12:53:21
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
index 818f8fd56..0d8c76b6a 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1096990                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 250472                       # Number of bytes of host memory used
-host_seconds                                   520.49                       # Real time elapsed on the host
-host_tick_rate                              558129819                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4059400                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209588                       # Number of bytes of host memory used
+host_seconds                                   140.65                       # Real time elapsed on the host
+host_tick_rate                             2065351773                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   570968176                       # Number of instructions simulated
 sim_seconds                                  0.290499                       # Number of seconds simulated
@@ -71,6 +71,6 @@ system.cpu.num_int_register_writes          425113002                       # nu
 system.cpu.num_load_insts                   126029556                       # Number of load instructions
 system.cpu.num_mem_refs                     182890035                       # number of memory refs
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             548                       # Number of system calls
+system.cpu.workload.num_syscalls                  548                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
index 75a3e24c1..1771ad8e9 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -164,14 +164,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
index 697084dd6..3ee3b4f05 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 17:57:49
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 12:55:52
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
index 3b54b12a7..218238666 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 577686                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 258200                       # Number of bytes of host memory used
-host_seconds                                   985.02                       # Real time elapsed on the host
-host_tick_rate                              733214267                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2210994                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 217324                       # Number of bytes of host memory used
+host_seconds                                   257.37                       # Real time elapsed on the host
+host_tick_rate                             2806251427                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   569034848                       # Number of instructions simulated
 sim_seconds                                  0.722234                       # Number of seconds simulated
@@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses          1138918                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.992551                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4065.490059                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.992551                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          177979623                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 22417.457622                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622                       # average overall mshr miss latency
@@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses            11521                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.480677                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            984.426148                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.480677                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          516611385                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 24743.338252                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252                       # average overall mshr miss latency
@@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses          231204                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.178502                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.445374                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          5849.157602                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         14594.006011                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.178502                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.445374                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           1150439                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -264,6 +264,6 @@ system.cpu.num_int_register_writes          425113002                       # nu
 system.cpu.num_load_insts                   126029556                       # Number of load instructions
 system.cpu.num_mem_refs                     182890035                       # number of memory refs
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             548                       # Number of system calls
+system.cpu.workload.num_syscalls                  548                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
index e87680710..523530b80 100644
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout
index 06f1587f3..22653279f 100755
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 18 2011 20:12:06
-M5 started Mar 18 2011 20:27:45
-M5 executing on zizzer
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:32:37
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
index 0fc55f229..6f1b3f3b0 100644
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 135575                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 259672                       # Number of bytes of host memory used
-host_seconds                                 11277.84                       # Real time elapsed on the host
-host_tick_rate                               51792019                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 233996                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 255168                       # Number of bytes of host memory used
+host_seconds                                  6534.25                       # Real time elapsed on the host
+host_tick_rate                               89390880                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1528988756                       # Number of instructions simulated
 sim_seconds                                  0.584102                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect           16731555                       # Nu
 system.cpu.BPredUnit.condPredicted          252612909                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                252612909                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches              149758588                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          41097639                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples   1035309655                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.476842                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.993609                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    433213212     41.84%     41.84% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    271303976     26.21%     68.05% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2    102660477      9.92%     77.96% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3    102477093      9.90%     87.86% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     38291141      3.70%     91.56% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5     25044351      2.42%     93.98% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6     10787246      1.04%     95.02% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7     10434520      1.01%     96.03% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     41097639      3.97%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total   1035309655                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                1528988756                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                      0                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts            1528317614                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                 384102160                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  533262345                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts          16763223                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                  149758588                       # Number of branches committed
+system.cpu.commit.bw_lim_events              41097639                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts     1528988756                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls             553                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts       795955462                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples   1035309655                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.476842                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.993609                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    433213212     41.84%     41.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    271303976     26.21%     68.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    102660477      9.92%     77.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3    102477093      9.90%     87.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     38291141      3.70%     91.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     25044351      2.42%     93.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     10787246      1.04%     95.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     10434520      1.01%     96.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     41097639      3.97%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1035309655                       # Number of insts commited each cycle
+system.cpu.commit.count                    1528988756                       # Number of instructions committed
+system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.int_insts                1528317614                       # Number of committed integer instructions.
+system.cpu.commit.loads                     384102160                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                      533262345                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                  1528988756                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1528988756                       # Number of Instructions Simulated
 system.cpu.cpi                               0.764037                       # CPI: Cycles Per Instruction
@@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses          2775377                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.998173                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4088.515779                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.998173                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          472799393                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 18648.960228                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 11951.477943                       # average overall mshr miss latency
@@ -119,12 +119,12 @@ system.cpu.dcache.tagsinuse               4088.515779                       # Cy
 system.cpu.dcache.total_refs                469490463                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             2268948000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                  2231104                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles      187291575                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts      2489806075                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         422005844                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          404270583                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles       108207267                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles       21741653                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles             187291575                       # Number of cycles decode is blocked
+system.cpu.decode.DecodedInsts             2489806075                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                422005844                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                 404270583                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles              108207267                       # Number of cycles decode is squashing
+system.cpu.decode.UnblockCycles              21741653                       # Number of cycles decode is unblocking
 system.cpu.fetch.Branches                   252612909                       # Number of branches that fetch encountered
 system.cpu.fetch.CacheLines                 188594062                       # Number of cache lines fetched
 system.cpu.fetch.Cycles                     440470513                       # Number of cycles fetch has run and was not squashing or blocked
@@ -187,8 +187,8 @@ system.cpu.icache.demand_mshr_misses           256130                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.469099                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            960.715295                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.469099                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          188594062                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency  6510.591789                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  3406.338578                       # average overall mshr miss latency
@@ -211,21 +211,13 @@ system.cpu.icache.total_refs                188329447                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        6                       # number of writebacks
 system.cpu.idleCycles                        24687157                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                173444431                       # Number of branches executed
-system.cpu.iew.EXEC:nop                             0                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.602205                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    612750445                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                  165978925                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                2110704618                       # num instructions consuming a value
-system.cpu.iew.WB:count                    1858331416                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.678632                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                1432391344                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.590759                       # insts written-back per cycle
-system.cpu.iew.WB:sent                     1864643959                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts             18167511                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                173444431                       # Number of branches executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.602205                       # Inst execution rate
+system.cpu.iew.exec_refs                    612750445                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                  165978925                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                 9685611                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts             586119276                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts               9659                       # Number of dispatched non-speculative instructions
@@ -253,103 +245,93 @@ system.cpu.iew.lsq.thread.0.squashedStores     73925179                       #
 system.cpu.iew.memOrderViolationEvents        2443893                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      2771097                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect       15396414                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                2110704618                       # num instructions consuming a value
+system.cpu.iew.wb_count                    1858331416                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.678632                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                1432391344                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.590759                       # insts written-back per cycle
+system.cpu.iew.wb_sent                     1864643959                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads               3111234049                       # number of integer regfile reads
 system.cpu.int_regfile_writes              1733847214                       # number of integer regfile writes
 system.cpu.ipc                               1.308837                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.308837                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass      2348064      0.12%      0.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu      1272739342     66.91%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     67.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      456676516     24.01%     91.05% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite     170264562      8.95%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total       1902028484                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt              11137895                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.005856                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu           1120921     10.06%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     10.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          7318318     65.71%     75.77% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite         2698656     24.23%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples   1143516922                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.663315                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.649679                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     363234856     31.76%     31.76% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     268152711     23.45%     55.21% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2     190268701     16.64%     71.85% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3     150184864     13.13%     84.99% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      96042571      8.40%     93.39% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      45507451      3.98%     97.37% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6      20662852      1.81%     99.17% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       8604200      0.75%     99.92% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        858716      0.08%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total   1143516922                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.628165                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass           2348064      0.12%      0.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1272739342     66.91%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.04% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            456676516     24.01%     91.05% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           170264562      8.95%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             1902028484                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                      77                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                 156                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           40                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes               7351                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                    11137895                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.005856                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1120921     10.06%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                7318318     65.71%     75.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2698656     24.23%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses             1910818238                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads         4959453857                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses   1858331376                       # Number of integer instruction queue wakeup accesses
@@ -361,6 +343,24 @@ system.cpu.iq.iqSquashedInstsExamined       793159883                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            742228                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved           9106                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined   1353359987                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples    1143516922                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.663315                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.649679                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           363234856     31.76%     31.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           268152711     23.45%     55.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           190268701     16.64%     71.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           150184864     13.13%     84.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            96042571      8.40%     93.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            45507451      3.98%     97.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            20662852      1.81%     99.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             8604200      0.75%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              858716      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1143516922                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.628165                       # Inst issue rate
 system.cpu.l2cache.ReadExReq_accesses          775816                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34258.394889                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.535640                       # average ReadExReq mshr miss latency
@@ -415,10 +415,10 @@ system.cpu.l2cache.demand_mshr_misses          586530                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.236559                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.418198                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          7751.549385                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         13703.522900                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.236559                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.418198                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           2544473                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34201.394643                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.134486                       # average overall mshr miss latency
@@ -448,28 +448,28 @@ system.cpu.misc_regfile_reads              1024751398                       # nu
 system.cpu.numCycles                       1168204079                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         50725953                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps     1427299027                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents        53866080                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         461056510                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents       71664979                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents           8215                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     5693696762                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      2424853504                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands   2263021553                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          385257729                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles       108207267                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles      138255029                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps         835722526                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups        18042                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups   5693678720                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles        14434                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts         2322                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts          301380597                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts         2286                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                50725953                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps            1427299027                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents               53866080                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                461056510                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents              71664979                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                  8215                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups            5693696762                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts             2424853504                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands          2263021553                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                 385257729                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles              108207267                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles             138255029                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                835722526                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups             18042                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups       5693678720                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles          14434                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts               2322                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                 301380597                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts           2286                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                   3319156234                       # The number of ROB reads
 system.cpu.rob.rob_writes                  4758159890                       # The number of ROB writes
 system.cpu.timesIdled                          639156                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls             551                       # Number of system calls
+system.cpu.workload.num_syscalls                  551                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
index adfcd9b98..fdc891c59 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -61,7 +61,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
index e27ac87ea..190029619 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 11 2011 23:35:10
-M5 revision c3deaa585dd3 7949 default qtip resforflagsstats.patch tip
-M5 started Feb 11 2011 23:35:13
-M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:30:34
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
index afe5ef235..3cf669902 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1866600                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 231212                       # Number of bytes of host memory used
-host_seconds                                   819.13                       # Real time elapsed on the host
-host_tick_rate                             1080693863                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3416660                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206360                       # Number of bytes of host memory used
+host_seconds                                   447.51                       # Real time elapsed on the host
+host_tick_rate                             1978121798                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1528988757                       # Number of instructions simulated
 sim_seconds                                  0.885229                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes         1427299027                       # nu
 system.cpu.num_load_insts                   384102160                       # Number of load instructions
 system.cpu.num_mem_refs                     533262345                       # number of memory refs
 system.cpu.num_store_insts                  149160185                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             551                       # Number of system calls
+system.cpu.workload.num_syscalls                  551                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
index 00b5b00f6..330cf56d3 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
@@ -161,7 +164,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
+cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
index 1e739aa16..b7abf2775 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 11 2011 23:35:10
-M5 revision c3deaa585dd3 7949 default qtip resforflagsstats.patch tip
-M5 started Feb 11 2011 23:35:13
-M5 executing on burrito
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:27:05
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
index dbe8c165b..9224e99d3 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1188316                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 238940                       # Number of bytes of host memory used
-host_seconds                                  1286.69                       # Real time elapsed on the host
-host_tick_rate                             1289149200                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2070048                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214112                       # Number of bytes of host memory used
+host_seconds                                   738.62                       # Real time elapsed on the host
+host_tick_rate                             2245699490                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1528988757                       # Number of instructions simulated
 sim_seconds                                  1.658730                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses          2518458                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997674                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4086.472055                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997674                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          533262390                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 23627.363053                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075                       # average overall mshr miss latency
@@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses             2814                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.430777                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            882.231489                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.430777                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses         1068347110                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 48641.791045                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045                       # average overall mshr miss latency
@@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses          579609                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.230381                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.417452                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          7549.128601                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         13679.064710                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.230381                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.417452                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           2521272                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 52000.010352                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -218,6 +218,6 @@ system.cpu.num_int_register_writes         1427299027                       # nu
 system.cpu.num_load_insts                   384102160                       # Number of load instructions
 system.cpu.num_mem_refs                     533262345                       # number of memory refs
 system.cpu.num_store_insts                  149160185                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             551                       # Number of system calls
+system.cpu.workload.num_syscalls                  551                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 26196c984..b5728d762 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
index 3643d6c6d..caf1c0c92 100755
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 21:44:37
-M5 started Mar 17 2011 21:58:43
-M5 executing on zizzer
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:24
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 388ace0a5..4140bf39e 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 169900                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215004                       # Number of bytes of host memory used
-host_seconds                                  2210.56                       # Real time elapsed on the host
-host_tick_rate                               51124064                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 334419                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 210864                       # Number of bytes of host memory used
+host_seconds                                  1123.07                       # Real time elapsed on the host
+host_tick_rate                              100628798                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   375574812                       # Number of instructions simulated
 sim_seconds                                  0.113013                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect            5223677                       # Nu
 system.cpu.BPredUnit.condPredicted           31927422                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                 56786170                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                 11422526                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               44587533                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          16035403                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    216073988                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.845037                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     2.480996                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     99774969     46.18%     46.18% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     35667629     16.51%     62.68% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     19281907      8.92%     71.61% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     16238513      7.52%     79.12% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     11569134      5.35%     84.48% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      7732170      3.58%     88.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6      5922846      2.74%     90.80% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      3851417      1.78%     92.58% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     16035403      7.42%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    216073988                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                 398664587                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts              155295106                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls          8007752                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts             316365844                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                  94754489                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  168275218                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts           5219312                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                   44587533                       # Number of branches committed
+system.cpu.commit.bw_lim_events              16035403                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts      398664587                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts        56265161                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples    216073988                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.845037                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.480996                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     99774969     46.18%     46.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     35667629     16.51%     62.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     19281907      8.92%     71.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     16238513      7.52%     79.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     11569134      5.35%     84.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7732170      3.58%     88.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      5922846      2.74%     90.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3851417      1.78%     92.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     16035403      7.42%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    216073988                       # Number of insts commited each cycle
+system.cpu.commit.count                     398664587                       # Number of instructions committed
+system.cpu.commit.fp_insts                  155295106                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls              8007752                       # Number of function calls committed.
+system.cpu.commit.int_insts                 316365844                       # Number of committed integer instructions.
+system.cpu.commit.loads                      94754489                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                      168275218                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                   375574812                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             375574812                       # Number of Instructions Simulated
 system.cpu.cpi                               0.601812                       # CPI: Cycles Per Instruction
@@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses             4182                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.803985                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           3293.121210                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.803985                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          166720564                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 30468.976321                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 34627.570540                       # average overall mshr miss latency
@@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse               3293.121210                       # Cy
 system.cpu.dcache.total_refs                166701099                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                      664                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles        5613634                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred           4438                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved      10679460                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts       490538381                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         118863884                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           90994213                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         9813191                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts          13275                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles         602257                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles               5613634                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                  4438                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved             10679460                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts              490538381                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                118863884                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                  90994213                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                9813191                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                 13275                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles                602257                       # Number of cycles decode is unblocking
 system.cpu.dtb.data_accesses                183645342                       # DTB accesses
 system.cpu.dtb.data_acv                         48603                       # DTB access violations
 system.cpu.dtb.data_hits                    183566296                       # DTB hits
@@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses             3907                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.890605                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1823.959859                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.890605                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           58423687                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 32309.424084                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 30830.816483                       # average overall mshr miss latency
@@ -233,21 +233,13 @@ system.cpu.icache.total_refs                 58418912                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                          138291                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 48687009                       # Number of branches executed
-system.cpu.iew.EXEC:nop                      26082950                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.805331                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    183693980                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   79967080                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 258989364                       # num instructions consuming a value
-system.cpu.iew.WB:count                     404042671                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.726642                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                 188192474                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.787598                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      405020447                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts              5625617                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                 48687009                       # Number of branches executed
+system.cpu.iew.exec_nop                      26082950                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.805331                       # Inst execution rate
+system.cpu.iew.exec_refs                    183693980                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                   79967080                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                 1911401                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts             106982646                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                239                       # Number of dispatched non-speculative instructions
@@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores     12856211                       #
 system.cpu.iew.memOrderViolationEvents           5629                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       886790                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        4738827                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                 258989364                       # num instructions consuming a value
+system.cpu.iew.wb_count                     404042671                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.726642                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                 188192474                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.787598                       # insts written-back per cycle
+system.cpu.iew.wb_sent                      405020447                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                406883956                       # number of integer regfile reads
 system.cpu.int_regfile_writes               173490032                       # number of integer regfile writes
 system.cpu.ipc                               1.661648                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.661648                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass        33581      0.01%      0.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       165161738     39.53%     39.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult        2124398      0.51%     40.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     40.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd      33524704      8.02%     48.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp       7711996      1.85%     49.91% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt       2967896      0.71%     50.62% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult     16674434      3.99%     54.61% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv       1571336      0.38%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     54.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      105669831     25.29%     80.28% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      82413056     19.72%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        417852970                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt              10358398                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.024790                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu              4298      0.04%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd             768      0.01%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               7      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt           10130      0.10%      0.15% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult        1743113     16.83%     16.97% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv          627758      6.06%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     23.04% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          5427565     52.40%     75.43% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite         2544759     24.57%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    225887179                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.849830                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.928832                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      80384230     35.59%     35.59% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      40475639     17.92%     53.50% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      30160734     13.35%     66.86% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3      26305410     11.65%     78.50% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      21278104      9.42%     87.92% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      14868616      6.58%     94.50% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       9130443      4.04%     98.55% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       2370545      1.05%     99.60% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        913458      0.40%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    225887179                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.848699                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass             33581      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             165161738     39.53%     39.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2124398      0.51%     40.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     40.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            33524704      8.02%     48.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             7711996      1.85%     49.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2967896      0.71%     50.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult           16674434      3.99%     54.61% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv             1571336      0.38%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.99% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            105669831     25.29%     80.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            82413056     19.72%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              417852970                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses               175354000                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads           344883249                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses    164390765                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes          192579711                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                    10358398                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.024790                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                    4298      0.04%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                   768      0.01%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     7      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                 10130      0.10%      0.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult              1743113     16.83%     16.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                627758      6.06%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     23.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5427565     52.40%     75.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2544759     24.57%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses              252823787                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads          727796795                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses    239651906                       # Number of integer instruction queue wakeup accesses
@@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined        47599271                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            728527                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             24                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined     28893091                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples     225887179                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.849830                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.928832                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            80384230     35.59%     35.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            40475639     17.92%     53.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            30160734     13.35%     66.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            26305410     11.65%     78.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            21278104      9.42%     87.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            14868616      6.58%     94.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             9130443      4.04%     98.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             2370545      1.05%     99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              913458      0.40%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       225887179                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.848699                       # Inst issue rate
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
@@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses            7364                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.108576                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.011590                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          3557.826949                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1           379.777727                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.108576                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.011590                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses              8089                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34457.903313                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31289.109180                       # average overall mshr miss latency
@@ -477,28 +477,28 @@ system.cpu.misc_regfile_writes                      1                       # nu
 system.cpu.numCycles                        226025470                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles          3360184                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps      259532333                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents             311                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         122116498                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        1529212                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents              2                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups      625408393                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       477751875                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    306658733                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           88296359                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         9813191                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        1960754                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          47126400                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups    292973848                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups    332434545                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles       340193                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts        36156                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts            5383709                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts          253                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                 3360184                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps             259532333                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                    311                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                122116498                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents               1529212                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                     2                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups             625408393                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts              477751875                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands           306658733                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                  88296359                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                9813191                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles               1960754                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                 47126400                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups         292973848                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups        332434545                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles         340193                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts              36156                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                   5383709                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts            253                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                    654965356                       # The number of ROB reads
 system.cpu.rob.rob_writes                   919674888                       # The number of ROB writes
 system.cpu.timesIdled                            3011                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls
+system.cpu.workload.num_syscalls                  215                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
index 96b5bf3c9..0fd1f360f 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:38
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:03:34
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index 6fcc67a34..6655c3650 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1382202                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 224632                       # Number of bytes of host memory used
-host_seconds                                   288.43                       # Real time elapsed on the host
-host_tick_rate                              691100750                       # Simulator tick rate (ticks/s)
+host_inst_rate                                5567399                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202284                       # Number of bytes of host memory used
+host_seconds                                    71.61                       # Real time elapsed on the host
+host_tick_rate                             2783694716                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_seconds                                  0.199332                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes          159335860                       # nu
 system.cpu.num_load_insts                    94754510                       # Number of load instructions
 system.cpu.num_mem_refs                     168275274                       # number of memory refs
 system.cpu.num_store_insts                   73520764                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls
+system.cpu.workload.num_syscalls                  215                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
index 91f994c0c..c222d6133 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
index 4f3149cad..2be6be9ef 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:38
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:04:03
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 31ad19d58..94a73b71f 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 531142                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 232344                       # Number of bytes of host memory used
-host_seconds                                   750.58                       # Real time elapsed on the host
-host_tick_rate                              755872580                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2583171                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 210032                       # Number of bytes of host memory used
+host_seconds                                   154.33                       # Real time elapsed on the host
+host_tick_rate                             3676130341                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_seconds                                  0.567343                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses             4152                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.802957                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           3288.912598                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.802957                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          168275220                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 54209.537572                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572                       # average overall mshr miss latency
@@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses             3673                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.876529                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1795.131074                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.876529                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          398664666                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 50648.516199                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199                       # average overall mshr miss latency
@@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses            7180                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.103674                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.011338                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          3397.175455                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1           371.536808                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.103674                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.011338                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses              7825                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -250,6 +250,6 @@ system.cpu.num_int_register_writes          159335870                       # nu
 system.cpu.num_load_insts                    94754511                       # Number of load instructions
 system.cpu.num_mem_refs                     168275276                       # number of memory refs
 system.cpu.num_store_insts                   73520765                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls
+system.cpu.workload.num_syscalls                  215                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
index a7fea3c2e..b2f50f12f 100644
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -498,7 +498,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout
index 556348771..09bb8bdda 100755
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 18:04:19
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 12:56:09
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
index 1de34b9ef..22fc80d01 100644
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 203026                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 267492                       # Number of bytes of host memory used
-host_seconds                                  1719.32                       # Real time elapsed on the host
-host_tick_rate                               88254289                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 250845                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 223896                       # Number of bytes of host memory used
+host_seconds                                  1391.56                       # Real time elapsed on the host
+host_tick_rate                              109041329                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   349065985                       # Number of instructions simulated
 sim_seconds                                  0.151737                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect            3421912                       # Nu
 system.cpu.BPredUnit.condPredicted           20033400                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                 36581771                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                  7288333                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               30521887                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           7594485                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    297396946                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.173740                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.829368                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    153798947     51.72%     51.72% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     68683080     23.09%     74.81% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     27481761      9.24%     84.05% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     16045950      5.40%     89.45% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     11196284      3.76%     93.21% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      6591467      2.22%     95.43% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6      3251010      1.09%     96.52% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      2753962      0.93%     97.45% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      7594485      2.55%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    297396946                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                 349066597                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts              114216705                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls          6225112                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts             287529375                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                  94648997                       # Number of loads committed
-system.cpu.commit.COM:membars                   11033                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  177024839                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts           3392850                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                   30521887                       # Number of branches committed
+system.cpu.commit.bw_lim_events               7594485                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts      349066597                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls         3555476                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts        29812251                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples    297396946                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.173740                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.829368                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    153798947     51.72%     51.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     68683080     23.09%     74.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     27481761      9.24%     84.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     16045950      5.40%     89.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     11196284      3.76%     93.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      6591467      2.22%     95.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3251010      1.09%     96.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2753962      0.93%     97.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      7594485      2.55%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    297396946                       # Number of insts commited each cycle
+system.cpu.commit.count                     349066597                       # Number of instructions committed
+system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls              6225112                       # Number of function calls committed.
+system.cpu.commit.int_insts                 287529375                       # Number of committed integer instructions.
+system.cpu.commit.loads                      94648997                       # Number of loads committed
+system.cpu.commit.membars                       11033                       # Number of memory barriers committed
+system.cpu.commit.refs                      177024839                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                   349065985                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             349065985                       # Number of Instructions Simulated
 system.cpu.cpi                               0.869391                       # CPI: Cycles Per Instruction
@@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses             4561                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.753211                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           3085.152893                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.753211                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          177564090                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 32354.475913                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 33694.694146                       # average overall mshr miss latency
@@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse               3085.152893                       # Cy
 system.cpu.dcache.total_refs                177564704                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                     1021                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles      139649394                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          71446                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved       7239931                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts       408881420                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          85142692                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           69995506                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         5956648                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts         202337                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles        2609353                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles             139649394                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                 71446                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved              7239931                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts              408881420                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                 85142692                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                  69995506                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                5956648                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                202337                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles               2609353                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses            15647                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.891809                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1826.425729                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.891809                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           38750811                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 11739.616414                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  8345.912955                       # average overall mshr miss latency
@@ -245,21 +245,13 @@ system.cpu.icache.total_refs                 38734752                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                          121166                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 31598497                       # Number of branches executed
-system.cpu.iew.EXEC:nop                         47916                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.198862                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    183613240                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   84389722                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 302337892                       # num instructions consuming a value
-system.cpu.iew.WB:count                     361679600                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.513512                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                 155254133                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.191795                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      362096434                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts              3575174                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                 31598497                       # Number of branches executed
+system.cpu.iew.exec_nop                         47916                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.198862                       # Inst execution rate
+system.cpu.iew.exec_refs                    183613240                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                   84389722                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                    6232                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts             104118233                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts            3634513                       # Number of dispatched non-speculative instructions
@@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores      6767279                       #
 system.cpu.iew.memOrderViolationEvents         165832                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       360118                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        3215056                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                 302337892                       # num instructions consuming a value
+system.cpu.iew.wb_count                     361679600                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.513512                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                 155254133                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.191795                       # insts written-back per cycle
+system.cpu.iew.wb_sent                      362096434                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                845155916                       # number of integer regfile reads
 system.cpu.int_regfile_writes               184404886                       # number of integer regfile writes
 system.cpu.ipc                               1.150231                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.150231                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       125135876     34.07%     34.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult        2147375      0.58%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             3      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     34.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd      6684118      1.82%     36.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     36.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp      8302383      2.26%     38.73% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt      3402331      0.93%     39.66% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv      1567187      0.43%     40.09% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc     20210889      5.50%     45.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult      7197544      1.96%     47.55% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc      7077346      1.93%     49.48% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt       175286      0.05%     49.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      100106815     27.25%     76.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      85290782     23.22%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        367297935                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt              12277552                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.033427                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu              1371      0.01%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult             5040      0.04%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd           66      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.05% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt         1306      0.01%      0.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            3      0.00%      0.06% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc       233643      1.90%      1.97% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult          626      0.01%      1.97% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc       321940      2.62%      4.59% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      4.59% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          7517293     61.23%     65.82% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite         4196264     34.18%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    303353593                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.210791                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.640692                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     151157606     49.83%     49.83% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      63646504     20.98%     70.81% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      27917034      9.20%     80.01% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3      21656943      7.14%     87.15% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      21437631      7.07%     94.22% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      10744150      3.54%     97.76% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       4648214      1.53%     99.29% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       1678112      0.55%     99.85% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        467399      0.15%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    303353593                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.210308                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             125135876     34.07%     34.07% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2147375      0.58%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     34.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6684118      1.82%     36.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8302383      2.26%     38.73% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3402331      0.93%     39.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv         1567187      0.43%     40.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       20210889      5.50%     45.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult        7197544      1.96%     47.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc      7077346      1.93%     49.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     49.52% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            100106815     27.25%     76.78% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            85290782     23.22%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              367297935                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses               125160042                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads           243629757                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses    116471069                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes          124289037                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                    12277552                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.033427                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                    1371      0.01%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   5040      0.04%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                66      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt              1306      0.01%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 3      0.00%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc           233643      1.90%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult              626      0.01%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        321940      2.62%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                7517293     61.23%     65.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4196264     34.18%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses              254415445                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads          807801978                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses    245208531                       # Number of integer instruction queue wakeup accesses
@@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined        27882412                       # Nu
 system.cpu.iq.iqSquashedInstsIssued           1204720                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved          90285                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined     56560737                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples     303353593                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.210791                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.640692                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           151157606     49.83%     49.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            63646504     20.98%     70.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            27917034      9.20%     80.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            21656943      7.14%     87.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            21437631      7.07%     94.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            10744150      3.54%     97.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             4648214      1.53%     99.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1678112      0.55%     99.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              467399      0.15%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       303353593                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.210308                       # Inst issue rate
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -468,10 +468,10 @@ system.cpu.l2cache.demand_mshr_misses            7094                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.103738                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.011318                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          3399.287353                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1           370.862974                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.103738                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.011318                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses             20201                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34371.098670                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.530589                       # average overall mshr miss latency
@@ -502,28 +502,28 @@ system.cpu.misc_regfile_writes               34422259                       # nu
 system.cpu.numCycles                        303474759                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles           833030                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps      340927172                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents           47966                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          92085018                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        4772387                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents              1                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     1568873073                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       396996902                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    382623172                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           66169446                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         5956648                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       17891726                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          41695997                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups    798025803                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups    770847270                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles    120417725                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts     12413036                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           58729283                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts      3692499                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                  833030                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps             340927172                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                  47966                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                 92085018                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents               4772387                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                     1                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups            1568873073                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts              396996902                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands           382623172                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                  66169446                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                5956648                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles              17891726                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                 41695997                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups         798025803                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups        770847270                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles      120417725                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts           12413036                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                  58729283                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts        3692499                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                    668678786                       # The number of ROB reads
 system.cpu.rob.rob_writes                   763715026                       # The number of ROB writes
 system.cpu.timesIdled                            2617                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls             191                       # Number of system calls
+system.cpu.workload.num_syscalls                  191                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
index 50c83e5cc..a5b41f00b 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -61,12 +61,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
index 6a6041ffa..e711f37f2 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 18:05:11
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 12:58:30
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
index 9bfaf4046..20eb7fdea 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 854402                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 255368                       # Number of bytes of host memory used
-host_seconds                                   408.55                       # Real time elapsed on the host
-host_tick_rate                              519751077                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3277679                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214524                       # Number of bytes of host memory used
+host_seconds                                   106.50                       # Real time elapsed on the host
+host_tick_rate                             1993879698                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   349065408                       # Number of instructions simulated
 sim_seconds                                  0.212344                       # Number of seconds simulated
@@ -71,6 +71,6 @@ system.cpu.num_int_register_writes          207564016                       # nu
 system.cpu.num_load_insts                    94648758                       # Number of load instructions
 system.cpu.num_mem_refs                     177024357                       # number of memory refs
 system.cpu.num_store_insts                   82375599                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             191                       # Number of system calls
+system.cpu.workload.num_syscalls                  191                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
index 52b5d655c..aed18b872 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -164,12 +164,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
index b2eb72faf..daf6c8759 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 18:11:41
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:00:20
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
index 91b489221..b979341f1 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 469608                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 263124                       # Number of bytes of host memory used
-host_seconds                                   742.51                       # Real time elapsed on the host
-host_tick_rate                              708215535                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1789233                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 222228                       # Number of bytes of host memory used
+host_seconds                                   194.88                       # Real time elapsed on the host
+host_tick_rate                             2698337573                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   348687131                       # Number of instructions simulated
 sim_seconds                                  0.525854                       # Number of seconds simulated
@@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses             4478                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.751562                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           3078.396238                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.751562                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          176624288                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 53608.307280                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 50608.307280                       # average overall mshr miss latency
@@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses            15603                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.862297                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1765.984158                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.862297                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          348660359                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 21025.572005                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005                       # average overall mshr miss latency
@@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses            6833                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.095644                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.010425                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          3134.059650                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1           341.613272                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.095644                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.010425                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses             20081                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -264,6 +264,6 @@ system.cpu.num_int_register_writes          207564015                       # nu
 system.cpu.num_load_insts                    94648758                       # Number of load instructions
 system.cpu.num_mem_refs                     177024357                       # number of memory refs
 system.cpu.num_store_insts                   82375599                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             191                       # Number of system calls
+system.cpu.workload.num_syscalls                  191                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index d7298148c..f5ffa5534 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index 4c38c001d..2316b9142 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 21:44:37
-M5 started Mar 17 2011 21:45:13
-M5 executing on zizzer
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:35
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 870c3ba76..c6cbb8474 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 161084                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215416                       # Number of bytes of host memory used
-host_seconds                                 11317.35                       # Real time elapsed on the host
-host_tick_rate                               60889223                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 299190                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211252                       # Number of bytes of host memory used
+host_seconds                                  6093.26                       # Real time elapsed on the host
+host_tick_rate                              113092899                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1823043370                       # Number of instructions simulated
 sim_seconds                                  0.689105                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect           28355376                       # Nu
 system.cpu.BPredUnit.condPredicted          229155282                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                342127414                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                 49327534                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches              266706457                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          71745000                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples   1283484985                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.565260                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     2.221446                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    584328523     45.53%     45.53% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    266282466     20.75%     66.27% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2    167965913     13.09%     79.36% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     72752284      5.67%     85.03% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     49726595      3.87%     88.90% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5     31709768      2.47%     91.37% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6     15719812      1.22%     92.60% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7     23254624      1.81%     94.41% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     71745000      5.59%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total   1283484985                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                2008987604                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts               71824891                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls         39955347                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts            1778941351                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                 511070026                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  721864922                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts          28343556                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                  266706457                       # Number of branches committed
+system.cpu.commit.bw_lim_events              71745000                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts     2008987604                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls              39                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts       649535600                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples   1283484985                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.565260                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.221446                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    584328523     45.53%     45.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    266282466     20.75%     66.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    167965913     13.09%     79.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     72752284      5.67%     85.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     49726595      3.87%     88.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     31709768      2.47%     91.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     15719812      1.22%     92.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     23254624      1.81%     94.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     71745000      5.59%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1283484985                       # Number of insts commited each cycle
+system.cpu.commit.count                    2008987604                       # Number of instructions committed
+system.cpu.commit.fp_insts                   71824891                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls             39955347                       # Number of function calls committed.
+system.cpu.commit.int_insts                1778941351                       # Number of committed integer instructions.
+system.cpu.commit.loads                     511070026                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                      721864922                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                  1823043370                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1823043370                       # Number of Instructions Simulated
 system.cpu.cpi                               0.755994                       # CPI: Cycles Per Instruction
@@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses          1530600                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999779                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4095.093805                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999779                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          672939834                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 37287.441089                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 34206.572586                       # average overall mshr miss latency
@@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse               4095.093805                       # Cy
 system.cpu.dcache.total_refs                670466697                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              272263000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   107391                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       27367471                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          11874                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved      29084935                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts      2889732822                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         703418574                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          551446436                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        94589845                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts          45736                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles        1252504                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles              27367471                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                 11874                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved             29084935                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts             2889732822                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                703418574                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                 551446436                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles               94589845                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                 45736                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles               1252504                       # Number of cycles decode is unblocking
 system.cpu.dtb.data_accesses                766409541                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                    765750752                       # DTB hits
@@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses             9774                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.787641                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1613.087790                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.787641                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          343698672                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 15692.605534                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 11569.674647                       # average overall mshr miss latency
@@ -233,21 +233,13 @@ system.cpu.icache.total_refs                343688083                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                          134338                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                273848647                       # Number of branches executed
-system.cpu.iew.EXEC:nop                     323098610                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.444031                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    766410290                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                  251723816                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                1598918223                       # num instructions consuming a value
-system.cpu.iew.WB:count                    1989129822                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.699683                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                1118735591                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.443271                       # insts written-back per cycle
-system.cpu.iew.WB:sent                     1990119861                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts             30877415                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                273848647                       # Number of branches executed
+system.cpu.iew.exec_nop                     323098610                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.444031                       # Inst execution rate
+system.cpu.iew.exec_refs                    766410290                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                  251723816                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                 3355843                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts             641174032                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                 62                       # Number of dispatched non-speculative instructions
@@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores     84105156                       #
 system.cpu.iew.memOrderViolationEvents           1647                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       787925                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect       30089490                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                1598918223                       # num instructions consuming a value
+system.cpu.iew.wb_count                    1989129822                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.699683                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                1118735591                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.443271                       # insts written-back per cycle
+system.cpu.iew.wb_sent                     1990119861                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads               2524191182                       # number of integer regfile reads
 system.cpu.int_regfile_writes              1452780579                       # number of integer regfile writes
 system.cpu.ipc                               1.322762                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.322762                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass         2752      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu      1197059589     57.90%     57.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult          18404      0.00%     57.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     57.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd      27850873      1.35%     59.24% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp       8254690      0.40%     59.64% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt       7204648      0.35%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            4      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     59.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      550666151     26.63%     86.62% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite     276547322     13.38%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total       2067604433                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt              36218004                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.017517                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu              5127      0.01%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead         27845547     76.88%     76.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite         8367330     23.10%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples   1378074830                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.500357                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.637561                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     509079016     36.94%     36.94% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     296362701     21.51%     58.45% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2     259221008     18.81%     77.26% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3     152505049     11.07%     88.32% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      67550622      4.90%     93.23% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      50043003      3.63%     96.86% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6      31234899      2.27%     99.12% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       9170584      0.67%     99.79% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8       2907948      0.21%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total   1378074830                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.500211                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass              2752      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1197059589     57.90%     57.90% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                18404      0.00%     57.90% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            27850873      1.35%     59.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             8254690      0.40%     59.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             7204648      0.35%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.99% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            550666151     26.63%     86.62% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           276547322     13.38%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             2067604433                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                75415887                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads           148066359                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses     72617602                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes           74982161                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                    36218004                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.017517                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                    5127      0.01%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               27845547     76.88%     76.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               8367330     23.10%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses             2028403798                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads         5422106783                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses   1916512220                       # Number of integer instruction queue wakeup accesses
@@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined       522645709                       # Nu
 system.cpu.iq.iqSquashedInstsIssued          20671442                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             23                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined    487946872                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples    1378074830                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.500357                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.637561                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           509079016     36.94%     36.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           296362701     21.51%     58.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           259221008     18.81%     77.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           152505049     11.07%     88.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            67550622      4.90%     93.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            50043003      3.63%     96.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            31234899      2.27%     99.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             9170584      0.67%     99.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             2907948      0.21%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1378074830                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.500211                       # Inst issue rate
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
@@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses         1480593                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.881563                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.093197                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0         28887.056134                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1          3053.875830                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.881563                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.093197                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           1540374                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34301.836494                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.797489                       # average overall mshr miss latency
@@ -477,28 +477,28 @@ system.cpu.misc_regfile_writes                      1                       # nu
 system.cpu.numCycles                       1378209168                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         17364773                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps     1384969070                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents          667601                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         717318588                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        9756545                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents              7                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     3251110860                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      2789102688                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands   1858404761                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          538784806                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        94589845                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        9995832                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps         473435691                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups    109436331                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups   3141674529                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles        20986                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts         2820                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           26060288                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts           67                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                17364773                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps            1384969070                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                 667601                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                717318588                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents               9756545                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                     7                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups            3251110860                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts             2789102688                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands          1858404761                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                 538784806                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles               94589845                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles               9995832                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                473435691                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups         109436331                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups       3141674529                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles          20986                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts               2820                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                  26060288                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts             67                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                   3864626779                       # The number of ROB reads
 system.cpu.rob.rob_writes                  5411636382                       # The number of ROB writes
 system.cpu.timesIdled                            3611                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls
+system.cpu.workload.num_syscalls                   39                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index b7ecd550d..01eff331e 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:37
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:05:07
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index 855c5964e..f1d866c8d 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1477901                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 224424                       # Number of bytes of host memory used
-host_seconds                                  1359.35                       # Real time elapsed on the host
-host_tick_rate                              739109964                       # Simulator tick rate (ticks/s)
+host_inst_rate                                5736498                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202144                       # Number of bytes of host memory used
+host_seconds                                   350.21                       # Real time elapsed on the host
+host_tick_rate                             2868866718                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_seconds                                  1.004711                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes         1332688300                       # nu
 system.cpu.num_load_insts                   511488910                       # Number of load instructions
 system.cpu.num_mem_refs                     722298387                       # number of memory refs
 system.cpu.num_store_insts                  210809477                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls
+system.cpu.workload.num_syscalls                   39                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 9be1cb679..d0df4a5be 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index 03731b56d..fd9623671 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:38
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:00:30
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index c88cbd8f6..0966bdbb1 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 584935                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 232204                       # Number of bytes of host memory used
-host_seconds                                  3434.55                       # Real time elapsed on the host
-host_tick_rate                              819166202                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2647820                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209816                       # Number of bytes of host memory used
+host_seconds                                   758.73                       # Real time elapsed on the host
+host_tick_rate                             3708113045                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_seconds                                  2.813468                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses          1530144                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999806                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4095.204626                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999806                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          721864922                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 54553.304787                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787                       # average overall mshr miss latency
@@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses            10596                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.721886                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1478.423269                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.721886                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses         2009421071                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 23421.857305                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305                       # average overall mshr miss latency
@@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses         1479815                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.880371                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.094050                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0         28848.012979                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1          3081.828747                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.880371                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.094050                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           1540740                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -250,6 +250,6 @@ system.cpu.num_int_register_writes         1332688300                       # nu
 system.cpu.num_load_insts                   511488910                       # Number of load instructions
 system.cpu.num_mem_refs                     722298387                       # number of memory refs
 system.cpu.num_store_insts                  210809477                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls
+system.cpu.workload.num_syscalls                   39                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 21ecdfc08..410b12d67 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -498,7 +498,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
index 166a55741..ef09fb549 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 18:12:10
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:00:27
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 6525e4aa7..d75eda4b1 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 140843                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 264636                       # Number of bytes of host memory used
-host_seconds                                 13386.13                       # Real time elapsed on the host
-host_tick_rate                               64927108                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 198311                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 221048                       # Number of bytes of host memory used
+host_seconds                                  9507.00                       # Real time elapsed on the host
+host_tick_rate                               91419245                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1885343131                       # Number of instructions simulated
 sim_seconds                                  0.869123                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect           38509304                       # Nu
 system.cpu.BPredUnit.condPredicted          414146262                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                547821195                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                 52353944                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches              291352101                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          58391194                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples   1569639960                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.201138                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.832019                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    741490044     47.24%     47.24% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    428382990     27.29%     74.53% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2    179836279     11.46%     85.99% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     75300710      4.80%     90.79% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     51350508      3.27%     94.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5     14363186      0.92%     94.97% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6     16626388      1.06%     96.03% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      3898661      0.25%     96.28% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     58391194      3.72%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total   1569639960                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                1885354147                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts               52289415                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls         41577833                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts            1660589568                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                 631390738                       # Number of loads committed
-system.cpu.commit.COM:membars                    9986                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  908389591                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts          44034324                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                  291352101                       # Number of branches committed
+system.cpu.commit.bw_lim_events              58391194                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts     1885354147                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls          211788                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts      1159545124                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples   1569639960                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.201138                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.832019                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    741490044     47.24%     47.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    428382990     27.29%     74.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    179836279     11.46%     85.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     75300710      4.80%     90.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     51350508      3.27%     94.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14363186      0.92%     94.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     16626388      1.06%     96.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3898661      0.25%     96.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     58391194      3.72%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1569639960                       # Number of insts commited each cycle
+system.cpu.commit.count                    1885354147                       # Number of instructions committed
+system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
+system.cpu.commit.int_insts                1660589568                       # Number of committed integer instructions.
+system.cpu.commit.loads                     631390738                       # Number of loads committed
+system.cpu.commit.membars                        9986                       # Number of memory barriers committed
+system.cpu.commit.refs                      908389591                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                  1885343131                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1885343131                       # Number of Instructions Simulated
 system.cpu.cpi                               0.921978                       # CPI: Cycles Per Instruction
@@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses          1535477                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999735                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4094.913997                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999735                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          996679005                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 34625.216763                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 34030.134935                       # average overall mshr miss latency
@@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse               4094.913997                       # Cy
 system.cpu.dcache.total_refs                993970537                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              333433000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   106994                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles      146923379                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          10558                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved      87779592                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts      3387651447                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         772293047                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          647864668                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles       162682073                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts          19702                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles        2558864                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles             146923379                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                 10558                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved             87779592                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts             3387651447                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                772293047                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                 647864668                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles              162682073                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                 19702                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles               2558864                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses            24392                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.752702                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1541.532802                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.752702                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          367105078                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency  9381.938291                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  6050.959331                       # average overall mshr miss latency
@@ -245,21 +245,13 @@ system.cpu.icache.total_refs                367080251                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                         5923199                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                358605233                       # Number of branches executed
-system.cpu.iew.EXEC:nop                       1350849                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.388402                       # Inst execution rate
-system.cpu.iew.EXEC:refs                   1176236253                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                  407328146                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                2464876715                       # num instructions consuming a value
-system.cpu.iew.WB:count                    2378604713                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.531444                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                1309943730                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.368394                       # insts written-back per cycle
-system.cpu.iew.WB:sent                     2386121679                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts             46494560                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                358605233                       # Number of branches executed
+system.cpu.iew.exec_nop                       1350849                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.388402                       # Inst execution rate
+system.cpu.iew.exec_refs                   1176236253                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                  407328146                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                11036637                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts             946299703                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts             229756                       # Number of dispatched non-speculative instructions
@@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores    201953747                       #
 system.cpu.iew.memOrderViolationEvents        2659902                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      7823566                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect       38670994                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                2464876715                       # num instructions consuming a value
+system.cpu.iew.wb_count                    2378604713                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.531444                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                1309943730                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.368394                       # insts written-back per cycle
+system.cpu.iew.wb_sent                     2386121679                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads               5694776843                       # number of integer regfile reads
 system.cpu.int_regfile_writes              1751148886                       # number of integer regfile writes
 system.cpu.ipc                               1.084624                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.084624                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu      1205851764     48.37%     48.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult       11238449      0.45%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd           8633      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     48.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd      1375289      0.06%     48.87% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     48.87% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp      6876474      0.28%     49.15% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt      5501201      0.22%     49.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     49.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc     23385525      0.94%     50.31% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     50.31% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     50.31% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     50.31% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      797167964     31.97%     82.28% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite     441731367     17.72%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total       2493136666                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt              86890569                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.034852                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu               482      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult            24113      0.03%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      0.03% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead         55140629     63.46%     63.49% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite        31725345     36.51%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples   1732322031                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.439188                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.577350                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     668978981     38.62%     38.62% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     360959007     20.84%     59.45% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2     315091353     18.19%     77.64% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3     182075740     10.51%     88.15% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4     118045462      6.81%     94.97% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      56433729      3.26%     98.23% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6      19322035      1.12%     99.34% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       5840762      0.34%     99.68% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8       5574962      0.32%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total   1732322031                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.434284                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1205851764     48.37%     48.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult             11238449      0.45%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                 8633      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     48.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.06%     48.87% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     48.87% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         6876474      0.28%     49.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         5501201      0.22%     49.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     49.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       23385525      0.94%     50.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     50.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     50.31% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            797167964     31.97%     82.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           441731367     17.72%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             2493136666                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                66051736                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads           126602345                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses     59166260                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes           83365842                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                    86890569                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.034852                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     482      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  24113      0.03%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               55140629     63.46%     63.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              31725345     36.51%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses             2513975499                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads         6687198013                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses   2319438453                       # Number of integer instruction queue wakeup accesses
@@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined      1158104053                       # Nu
 system.cpu.iq.iqSquashedInstsIssued           8314426                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved          30366                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined   1709199023                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples    1732322031                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.439188                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.577350                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           668978981     38.62%     38.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           360959007     20.84%     59.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           315091353     18.19%     77.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           182075740     10.51%     88.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           118045462      6.81%     94.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            56433729      3.26%     98.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            19322035      1.12%     99.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             5840762      0.34%     99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             5574962      0.32%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1732322031                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.434284                       # Inst issue rate
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -469,10 +469,10 @@ system.cpu.l2cache.demand_mshr_misses         1480664                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.884291                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.091352                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0         28976.452018                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1          2993.413242                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.884291                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.091352                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           1559863                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34267.085819                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.382261                       # average overall mshr miss latency
@@ -503,28 +503,28 @@ system.cpu.misc_regfile_writes               13780014                       # nu
 system.cpu.numCycles                       1738245230                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         26815429                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps     1523726473                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents        13358705                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         804669593                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents       12419294                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents              3                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     8858159876                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      3258876297                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands   2595747724                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          616670755                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles       162682073                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       32941123                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps        1072021248                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups    417025150                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups   8441134726                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles     88543058                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts      8500262                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           93807403                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts       250407                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                26815429                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps            1523726473                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents               13358705                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                804669593                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents              12419294                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups            8858159876                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts             3258876297                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands          2595747724                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                 616670755                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles              162682073                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles              32941123                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps               1072021248                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups         417025150                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups       8441134726                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles       88543058                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts            8500262                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                  93807403                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts         250407                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                   4556129692                       # The number of ROB reads
 system.cpu.rob.rob_writes                  6252480772                       # The number of ROB writes
 system.cpu.timesIdled                         1346475                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls            1411                       # Number of system calls
+system.cpu.workload.num_syscalls                 1411                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index 4c80bccfd..97cb6c6e4 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -61,12 +61,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
index 47a67193a..343cd2a25 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 18:14:25
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:03:45
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index a5bf8162c..fa8e0bd4e 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1065231                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 252312                       # Number of bytes of host memory used
-host_seconds                                  1769.89                       # Real time elapsed on the host
-host_tick_rate                              534279231                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3903299                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211416                       # Number of bytes of host memory used
+host_seconds                                   483.01                       # Real time elapsed on the host
+host_tick_rate                             1957745790                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1885336367                       # Number of instructions simulated
 sim_seconds                                  0.945613                       # Number of seconds simulated
@@ -71,6 +71,6 @@ system.cpu.num_int_register_writes         1404936302                       # nu
 system.cpu.num_load_insts                   631387182                       # Number of load instructions
 system.cpu.num_mem_refs                     908382480                       # number of memory refs
 system.cpu.num_store_insts                  276995298                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls            1411                       # Number of system calls
+system.cpu.workload.num_syscalls                 1411                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index 53d197f66..f566d5f40 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -164,12 +164,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
index 5f6cb9527..5a9581642 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 18:18:27
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:11:59
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 3345b6b66..064048304 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 561445                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 260040                       # Number of bytes of host memory used
-host_seconds                                  3338.25                       # Real time elapsed on the host
-host_tick_rate                              709922934                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2093812                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 219156                       # Number of bytes of host memory used
+host_seconds                                   895.14                       # Real time elapsed on the host
+host_tick_rate                             2647534553                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1874244950                       # Number of instructions simulated
 sim_seconds                                  2.369902                       # Number of seconds simulated
@@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses          1533653                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999746                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4094.960333                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999746                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          897271092                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 54458.738711                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711                       # average overall mshr miss latency
@@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses            19803                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.679846                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1392.324437                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.679846                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses         1390271511                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 18786.850477                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477                       # average overall mshr miss latency
@@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses         1479630                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.881757                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.092817                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0         28893.420796                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1          3041.423322                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.881757                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.092817                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           1553456                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -264,6 +264,6 @@ system.cpu.num_int_register_writes         1404936302                       # nu
 system.cpu.num_load_insts                   631387182                       # Number of load instructions
 system.cpu.num_mem_refs                     908382480                       # number of memory refs
 system.cpu.num_store_insts                  276995298                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls            1411                       # Number of system calls
+system.cpu.workload.num_syscalls                 1411                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index 46d47f481..2452e8b3b 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -86,6 +86,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +122,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -156,6 +158,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
index 55fcb321a..124e9408d 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 18 2011 15:40:30
-M5 revision Unknown
-M5 started Feb 18 2011 18:53:22
-M5 executing on m55-001.pool
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:35
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index 883ec05af..e986b9b66 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,37 +1,25 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 140237                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 237028                       # Number of bytes of host memory used
-host_seconds                                   629.94                       # Real time elapsed on the host
-host_tick_rate                               69352666                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 198512                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 241900                       # Number of bytes of host memory used
+host_seconds                                   445.02                       # Real time elapsed on the host
+host_tick_rate                               98171525                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_seconds                                  0.043688                       # Number of seconds simulated
 sim_ticks                                 43687852500                       # Number of ticks simulated
-system.cpu.AGEN-Unit.agens                   35033051                       # Number of Address Generations
-system.cpu.Branch-Predictor.BTBHitPct       40.125186                       # BTB Hit Percentage
-system.cpu.Branch-Predictor.BTBHits           4678520                       # Number of BTB hits
-system.cpu.Branch-Predictor.BTBLookups       11659809                       # Number of BTB lookups
-system.cpu.Branch-Predictor.RASInCorrect         1539                       # Number of incorrect RAS predictions.
-system.cpu.Branch-Predictor.condIncorrect       753993                       # Number of conditional branches incorrect
-system.cpu.Branch-Predictor.condPredicted      9173160                       # Number of conditional branches predicted
-system.cpu.Branch-Predictor.lookups          14237671                       # Number of BP lookups
-system.cpu.Branch-Predictor.predictedNotTaken      6139595                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken      8098076                       # Number of Branches Predicted As Taken (True).
-system.cpu.Branch-Predictor.usedRAS           1660495                       # Number of times the RAS was used to get a target.
-system.cpu.Execution-Unit.executions         44841137                       # Number of Instructions Executed.
-system.cpu.Execution-Unit.mispredictPct      5.481801                       # Percentage of Incorrect Branches Predicts
-system.cpu.Execution-Unit.mispredicted         753993                       # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predicted          13000484                       # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predictedNotTakenIncorrect       550902                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.Execution-Unit.predictedTakenIncorrect       203091                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.Mult-Div-Unit.divides                    0                       # Number of Divide Operations Executed
-system.cpu.Mult-Div-Unit.multiplies             41101                       # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses    145605009                       # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads      93058128                       # Number of Reads from Register File
-system.cpu.RegFile-Manager.regFileWrites     52546881                       # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards       13517276                       # Number of Registers Read Through Forwarding Logic
 system.cpu.activity                         70.715162                       # Percentage of cycles cpu is active
+system.cpu.agen_unit.agens                   35033051                       # Number of Address Generations
+system.cpu.branch_predictor.BTBHitPct       40.125186                       # BTB Hit Percentage
+system.cpu.branch_predictor.BTBHits           4678520                       # Number of BTB hits
+system.cpu.branch_predictor.BTBLookups       11659809                       # Number of BTB lookups
+system.cpu.branch_predictor.RASInCorrect         1539                       # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.condIncorrect       753993                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.condPredicted      9173160                       # Number of conditional branches predicted
+system.cpu.branch_predictor.lookups          14237671                       # Number of BP lookups
+system.cpu.branch_predictor.predictedNotTaken      6139595                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.branch_predictor.predictedTaken      8098076                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.usedRAS           1660495                       # Number of times the RAS was used to get a target.
 system.cpu.comBranches                       13754477                       # Number of Branches instructions committed
 system.cpu.comFloats                           151453                       # Number of Floating Point instructions committed
 system.cpu.comInts                           30791227                       # Number of Integer instructions committed
@@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses           204344                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.994103                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4071.844772                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.994103                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           34890015                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 48047.843576                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 45018.459069                       # average overall mshr miss latency
@@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses                14620629                       # DT
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_hits                    14613377                       # DTB write hits
 system.cpu.dtb.write_misses                      7252                       # DTB write misses
+system.cpu.execution_unit.executions         44841137                       # Number of Instructions Executed.
+system.cpu.execution_unit.mispredictPct      5.481801                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.mispredicted         753993                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted          13000484                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predictedNotTakenIncorrect       550902                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.predictedTakenIncorrect       203091                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.icache.ReadReq_accesses           11384439                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 18620.927639                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 15557.720286                       # average ReadReq mshr miss latency
@@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses            88669                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.918759                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1881.619179                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.918759                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           11384439                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 18620.927639                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 15557.720286                       # average overall mshr miss latency
@@ -246,10 +240,10 @@ system.cpu.l2cache.demand_mshr_misses          174462                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.093044                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.476016                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          3048.873160                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         15598.097053                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.093044                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.476016                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            293012                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 52103.234515                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 40007.007257                       # average overall mshr miss latency
@@ -271,31 +265,37 @@ system.cpu.l2cache.tagsinuse             18646.970214                       # Cy
 system.cpu.l2cache.total_refs                  134496                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                  120516                       # number of writebacks
+system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.mult_div_unit.multiplies             41101                       # Number of Multipy Operations Executed
 system.cpu.numCycles                         87375706                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.regfile_manager.regFileAccesses    145605009                       # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.regfile_manager.regFileReads      93058128                       # Number of Reads from Register File
+system.cpu.regfile_manager.regFileWrites     52546881                       # Number of Writes to Register File
+system.cpu.regfile_manager.regForwards       13517276                       # Number of Registers Read Through Forwarding Logic
 system.cpu.runCycles                         61787872                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles                42493951                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-0.runCycles                 44881755                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization              51.366400                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles                48181868                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles                 39193838                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization              44.856677                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles                46079607                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-2.runCycles                 41296099                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization              47.262678                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles                63477269                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-3.runCycles                 23898437                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization              27.351352                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles                39338499                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-4.runCycles                 48037207                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization              54.977761                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage0.idleCycles                 42493951                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                  44881755                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               51.366400                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                 48181868                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                  39193838                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               44.856677                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                 46079607                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                  41296099                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               47.262678                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                 63477269                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                  23898437                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               27.351352                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                 39338499                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                  48037207                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               54.977761                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.threadCycles                      69007682                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.timesIdled                          289197                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls            4583                       # Number of system calls
+system.cpu.workload.num_syscalls                 4583                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 22a45b8cb..c10dc5f2b 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
index 78849816e..0e04160b4 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 21:44:37
-M5 started Mar 17 2011 21:45:41
-M5 executing on zizzer
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:35
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 2c566c667..2aed2a2e0 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 229170                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 217968                       # Number of bytes of host memory used
-host_seconds                                   347.30                       # Real time elapsed on the host
-host_tick_rate                               73616120                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 329538                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213968                       # Number of bytes of host memory used
+host_seconds                                   241.53                       # Real time elapsed on the host
+host_tick_rate                              105857368                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_seconds                                  0.025567                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect             450273                       # Nu
 system.cpu.BPredUnit.condPredicted           10401089                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                 16008370                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                  1909965                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               13754477                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           3841167                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples     49654357                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.779112                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     2.457508                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     22596462     45.51%     45.51% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1      9701520     19.54%     65.05% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2      4636863      9.34%     74.38% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      2945074      5.93%     80.32% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      2498358      5.03%     85.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      1627223      3.28%     88.62% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6       982509      1.98%     90.60% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       825181      1.66%     92.26% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      3841167      7.74%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total     49654357                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                  88340672                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                 267754                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls          1661057                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts              77942044                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                  20276638                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   34890015                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts            354109                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                   13754477                       # Number of branches committed
+system.cpu.commit.bw_lim_events               3841167                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts       88340672                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts         6568373                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples     49654357                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.779112                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.457508                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     22596462     45.51%     45.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      9701520     19.54%     65.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4636863      9.34%     74.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2945074      5.93%     80.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2498358      5.03%     85.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1627223      3.28%     88.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       982509      1.98%     90.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       825181      1.66%     92.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3841167      7.74%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     49654357                       # Number of insts commited each cycle
+system.cpu.commit.count                      88340672                       # Number of instructions committed
+system.cpu.commit.fp_insts                     267754                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls              1661057                       # Number of function calls committed.
+system.cpu.commit.int_insts                  77942044                       # Number of committed integer instructions.
+system.cpu.commit.loads                      20276638                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                       34890015                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
 system.cpu.committedInsts_total              79591756                       # Number of Instructions Simulated
 system.cpu.cpi                               0.642459                       # CPI: Cycles Per Instruction
@@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses           205151                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.995275                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4076.644885                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995275                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           35172985                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 31791.373703                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 29357.307544                       # average overall mshr miss latency
@@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse               4076.644885                       # Cy
 system.cpu.dcache.total_refs                 33980616                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              177876000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   161514                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles        2460997                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          97681                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved       3594435                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts       100084760                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          27762644                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           19396266                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         1063649                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts         276834                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles          34450                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles               2460997                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                 97681                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved              3594435                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts              100084760                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                 27762644                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                  19396266                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                1063649                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                276834                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles                 34450                       # Number of cycles decode is unblocking
 system.cpu.dtb.data_accesses                 36973918                       # DTB accesses
 system.cpu.dtb.data_acv                            20                       # DTB access violations
 system.cpu.dtb.data_hits                     36772232                       # DTB hits
@@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses            85058                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.935566                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1916.040169                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.935566                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           13158718                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency  9582.065520                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  6079.057819                       # average overall mshr miss latency
@@ -233,21 +233,13 @@ system.cpu.icache.total_refs                 13070837                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                          416464                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 14700654                       # Number of branches executed
-system.cpu.iew.EXEC:nop                       9311504                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.660486                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     36975872                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   15225695                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                  40429267                       # num instructions consuming a value
-system.cpu.iew.WB:count                      84366668                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.767758                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                  31039892                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.649898                       # insts written-back per cycle
-system.cpu.iew.WB:sent                       84634554                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts               395795                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                 14700654                       # Number of branches executed
+system.cpu.iew.exec_nop                       9311504                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.660486                       # Inst execution rate
+system.cpu.iew.exec_refs                     36975872                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                   15225695                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                  429488                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts              22491432                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts               4739                       # Number of dispatched non-speculative instructions
@@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores      1168217                       #
 system.cpu.iew.memOrderViolationEvents           6217                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       133065                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect         262730                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                  40429267                       # num instructions consuming a value
+system.cpu.iew.wb_count                      84366668                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.767758                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                  31039892                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.649898                       # insts written-back per cycle
+system.cpu.iew.wb_sent                       84634554                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                112360564                       # number of integer regfile reads
 system.cpu.int_regfile_writes                55786710                       # number of integer regfile writes
 system.cpu.ipc                               1.556519                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.556519                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu        47939957     56.08%     56.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult          43473      0.05%     56.14% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     56.14% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd        122672      0.14%     56.28% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp            87      0.00%     56.28% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt        123541      0.14%     56.42% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult           52      0.00%     56.42% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv         38558      0.05%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     56.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       21877865     25.59%     82.06% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      15331781     17.94%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total         85477986                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               1052413                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.012312                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu             99607      9.46%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      9.46% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead           509872     48.45%     57.91% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          442934     42.09%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples     50718006                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.685358                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.886898                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      18797586     37.06%     37.06% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      10551252     20.80%     57.87% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2       7740515     15.26%     73.13% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3       3878311      7.65%     80.78% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4       5219123     10.29%     91.07% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       1973435      3.89%     94.96% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       1302970      2.57%     97.53% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        789228      1.56%     99.08% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        465586      0.92%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total     50718006                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.671631                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              47939957     56.08%     56.08% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                43473      0.05%     56.14% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     56.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              122672      0.14%     56.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  87      0.00%     56.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt              123541      0.14%     56.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 52      0.00%     56.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv               38558      0.05%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.47% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             21877865     25.59%     82.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            15331781     17.94%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total               85477986                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                  297653                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads              595198                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses       282834                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes             410179                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                     1052413                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012312                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   99607      9.46%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 509872     48.45%     57.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                442934     42.09%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses               86232746                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads          222155982                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses     84083834                       # Number of integer instruction queue wakeup accesses
@@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined         8137764                       # Nu
 system.cpu.iq.iqSquashedInstsIssued             24789                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved            156                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined      4541669                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples      50718006                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.685358                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.886898                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            18797586     37.06%     37.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            10551252     20.80%     57.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7740515     15.26%     73.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3878311      7.65%     80.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             5219123     10.29%     91.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1973435      3.89%     94.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1302970      2.57%     97.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              789228      1.56%     99.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              465586      0.92%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        50718006                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.671631                       # Inst issue rate
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
@@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses          175063                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.091039                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.482420                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          2983.162459                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         15807.936259                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.091039                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.482420                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            290209                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34335.524925                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31214.302851                       # average overall mshr miss latency
@@ -477,28 +477,28 @@ system.cpu.misc_regfile_writes                      1                       # nu
 system.cpu.numCycles                         51134470                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles          1389160                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps       52546881                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents           11049                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          28153155                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents         921609                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents             39                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups      119490611                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts        99297358                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands     59691366                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           19024050                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         1063649                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        1018413                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps           7144485                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups       428893                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups    119061718                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles        69579                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts         5023                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts            2212492                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts         5020                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                 1389160                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                  11049                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                 28153155                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents                921609                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                    39                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups             119490611                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts               99297358                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands            59691366                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                  19024050                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                1063649                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles               1018413                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                  7144485                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups            428893                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups        119061718                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles          69579                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts               5023                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                   2212492                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts           5020                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                    139404893                       # The number of ROB reads
 system.cpu.rob.rob_writes                   190882895                       # The number of ROB writes
 system.cpu.timesIdled                           12185                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls            4583                       # Number of system calls
+system.cpu.workload.num_syscalls                 4583                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
index 47e63ab68..01b718e71 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:38
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:24
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index 1ad0b8bf6..cf38a10a9 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1614429                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 226740                       # Number of bytes of host memory used
-host_seconds                                    54.72                       # Real time elapsed on the host
-host_tick_rate                              808136192                       # Simulator tick rate (ticks/s)
+host_inst_rate                                5661046                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204384                       # Number of bytes of host memory used
+host_seconds                                    15.61                       # Real time elapsed on the host
+host_tick_rate                             2833734985                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_seconds                                  0.044221                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes           52319251                       # nu
 system.cpu.num_load_insts                    20366786                       # Number of load instructions
 system.cpu.num_mem_refs                      34987415                       # number of memory refs
 system.cpu.num_store_insts                   14620629                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls            4583                       # Number of system calls
+system.cpu.workload.num_syscalls                 4583                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 6f171a7fa..7e8e19e97 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
index 4f3f97870..c65ed7989 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:37
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:02:47
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 4a3fdb24c..d459892f5 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 599191                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 234452                       # Number of bytes of host memory used
-host_seconds                                   147.43                       # Real time elapsed on the host
-host_tick_rate                              910763031                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2375162                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 212132                       # Number of bytes of host memory used
+host_seconds                                    37.19                       # Real time elapsed on the host
+host_tick_rate                             3610204318                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_seconds                                  0.134277                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses           204344                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.995815                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4078.858373                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995815                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           34890015                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 47925.116470                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 44925.116470                       # average overall mshr miss latency
@@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses            76436                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.913772                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1871.404551                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.913772                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           88438074                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 18793.107960                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 15793.107960                       # average overall mshr miss latency
@@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses          173780                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.085649                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.482430                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          2806.549776                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         15808.263557                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.085649                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.482430                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            280780                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -250,6 +250,6 @@ system.cpu.num_int_register_writes           52319251                       # nu
 system.cpu.num_load_insts                    20366786                       # Number of load instructions
 system.cpu.num_mem_refs                      34987415                       # number of memory refs
 system.cpu.num_store_insts                   14620629                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls            4583                       # Number of system calls
+system.cpu.workload.num_syscalls                 4583                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
index 6767fc19c..2426ff257 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -498,7 +498,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
index 3d6783bda..8381f7581 100755
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 18:24:14
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:18:26
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 2c7e07f74..50e06cc2a 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 216149                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 267340                       # Number of bytes of host memory used
-host_seconds                                   465.57                       # Real time elapsed on the host
-host_tick_rate                               85683012                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 252526                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 223792                       # Number of bytes of host memory used
+host_seconds                                   398.51                       # Real time elapsed on the host
+host_tick_rate                              100102950                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   100633305                       # Number of instructions simulated
 sim_seconds                                  0.039892                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect             830445                       # Nu
 system.cpu.BPredUnit.condPredicted           11914381                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                 18227498                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                  1851553                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               13669912                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           2877364                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples     76617428                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.313524                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.896154                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     34018334     44.40%     44.40% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     22269182     29.07%     73.47% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2      6570057      8.58%     82.04% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      4759391      6.21%     88.25% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      3903161      5.09%     93.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      1377879      1.80%     95.15% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6       463983      0.61%     95.75% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       378077      0.49%     96.24% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      2877364      3.76%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total     76617428                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                 100638857                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                     56                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls          1679850                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts              91477923                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                  27308393                       # Number of loads committed
-system.cpu.commit.COM:membars                   15920                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   47865415                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts            800437                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                   13669912                       # Number of branches committed
+system.cpu.commit.bw_lim_events               2877364                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts      100638857                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls          700914                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts        13588852                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples     76617428                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.313524                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.896154                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     34018334     44.40%     44.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     22269182     29.07%     73.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      6570057      8.58%     82.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4759391      6.21%     88.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3903161      5.09%     93.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1377879      1.80%     95.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       463983      0.61%     95.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       378077      0.49%     96.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2877364      3.76%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     76617428                       # Number of insts commited each cycle
+system.cpu.commit.count                     100638857                       # Number of instructions committed
+system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
+system.cpu.commit.int_insts                  91477923                       # Number of committed integer instructions.
+system.cpu.commit.loads                      27308393                       # Number of loads committed
+system.cpu.commit.membars                       15920                       # Number of memory barriers committed
+system.cpu.commit.refs                       47865415                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                   100633305                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             100633305                       # Number of Instructions Simulated
 system.cpu.cpi                               0.792814                       # CPI: Cycles Per Instruction
@@ -109,8 +109,8 @@ system.cpu.dcache.demand_mshr_misses           161560                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.994984                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4075.453819                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.994984                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           46799358                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 31971.352710                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 28987.939465                       # average overall mshr miss latency
@@ -132,15 +132,15 @@ system.cpu.dcache.tagsinuse               4075.453819                       # Cy
 system.cpu.dcache.total_refs                 45185537                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              327416000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   123381                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       28767889                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          93628                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved       3727749                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts       120621461                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          25476849                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           21756774                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         2130394                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts         323992                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles         615915                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles              28767889                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                 93628                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved              3727749                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts              120621461                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                 25476849                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                  21756774                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                2130394                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                323992                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles                615915                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -225,8 +225,8 @@ system.cpu.icache.demand_mshr_misses            24591                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.875696                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1793.424749                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.875696                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           11770565                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 12757.129371                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  9282.013745                       # average overall mshr miss latency
@@ -249,21 +249,13 @@ system.cpu.icache.total_refs                 11745142                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                         1035652                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 14732348                       # Number of branches executed
-system.cpu.iew.EXEC:nop                         77233                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.323750                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     49299625                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   21011299                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 107738460                       # num instructions consuming a value
-system.cpu.iew.WB:count                     105037825                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.490563                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                  52852456                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.316536                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      105209239                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts               874742                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                 14732348                       # Number of branches executed
+system.cpu.iew.exec_nop                         77233                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.323750                       # Inst execution rate
+system.cpu.iew.exec_refs                     49299625                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                   21011299                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                  976865                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts              29744817                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts             738677                       # Number of dispatched non-speculative instructions
@@ -291,103 +283,93 @@ system.cpu.iew.lsq.thread.0.squashedStores      1650781                       #
 system.cpu.iew.memOrderViolationEvents           8523                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       227397                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect         647345                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                 107738460                       # num instructions consuming a value
+system.cpu.iew.wb_count                     105037825                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.490563                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                  52852456                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.316536                       # insts written-back per cycle
+system.cpu.iew.wb_sent                      105209239                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                252839831                       # number of integer regfile reads
 system.cpu.int_regfile_writes                78127703                       # number of integer regfile writes
 system.cpu.ipc                               1.261330                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.261330                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu        56712642     53.23%     53.23% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult          95301      0.09%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd            11      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              1      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            8      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     53.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       28583241     26.83%     80.15% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      21153285     19.85%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        106544489                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               1792992                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.016829                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu             49061      2.74%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      2.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          1439096     80.26%     83.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          304835     17.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples     78747821                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.352983                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.550711                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      30449549     38.67%     38.67% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      20272773     25.74%     64.41% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      12837785     16.30%     80.71% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3       6496976      8.25%     88.96% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4       4874072      6.19%     95.15% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       2197331      2.79%     97.94% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6        925872      1.18%     99.12% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        480661      0.61%     99.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        212802      0.27%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total     78747821                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.335421                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              56712642     53.23%     53.23% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                95301      0.09%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  11      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    1      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              8      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     53.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             28583241     26.83%     80.15% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21153285     19.85%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              106544489                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                      82                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                 160                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           68                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                144                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                     1792992                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.016829                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   49061      2.74%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1439096     80.26%     83.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                304835     17.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses              108337399                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads          293735316                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses    105037757                       # Number of integer instruction queue wakeup accesses
@@ -399,6 +381,24 @@ system.cpu.iq.iqSquashedInstsExamined        13400232                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            105692                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved          54866                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined     21923544                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples      78747821                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.352983                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.550711                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            30449549     38.67%     38.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            20272773     25.74%     64.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            12837785     16.30%     80.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6496976      8.25%     88.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4874072      6.19%     95.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2197331      2.79%     97.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6              925872      1.18%     99.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              480661      0.61%     99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              212802      0.27%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        78747821                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.335421                       # Inst issue rate
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -473,10 +473,10 @@ system.cpu.l2cache.demand_mshr_misses          134835                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.070082                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.488463                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          2296.436358                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         16005.968558                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.070082                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.488463                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            186127                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34374.638605                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31202.784885                       # average overall mshr miss latency
@@ -507,28 +507,28 @@ system.cpu.misc_regfile_writes                  34408                       # nu
 system.cpu.numCycles                         79783473                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles          2921057                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps       75878617                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents          205954                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          27124909                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        2993782                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents              3                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups      315599119                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       118180992                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands     90551096                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           20607135                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         2130394                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        4279204                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          14672443                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups        83429                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups    315515690                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles     21685122                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts       759000                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           12013897                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts       759711                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                 2921057                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps              75878617                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                 205954                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                 27124909                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents               2993782                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups             315599119                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts              118180992                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands            90551096                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                  20607135                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                2130394                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles               4279204                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                 14672443                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups             83429                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups        315515690                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles       21685122                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts             759000                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                  12013897                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts         759711                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                    187942474                       # The number of ROB reads
 system.cpu.rob.rob_writes                   230588533                       # The number of ROB writes
 system.cpu.timesIdled                           60808                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
index 262e03017..d284ed163 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -61,12 +61,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
index 66dafc4ae..6efadf55b 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 18:44:05
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:19:31
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index c99f59463..a40e03286 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1067183                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 254708                       # Number of bytes of host memory used
-host_seconds                                    94.30                       # Real time elapsed on the host
-host_tick_rate                              571936208                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3930429                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213832                       # Number of bytes of host memory used
+host_seconds                                    25.60                       # Real time elapsed on the host
+host_tick_rate                             2106429498                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   100632437                       # Number of instructions simulated
 sim_seconds                                  0.053932                       # Number of seconds simulated
@@ -71,6 +71,6 @@ system.cpu.num_int_register_writes           73126599                       # nu
 system.cpu.num_load_insts                    27307109                       # Number of load instructions
 system.cpu.num_mem_refs                      47862848                       # number of memory refs
 system.cpu.num_store_insts                   20555739                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
index c681e2402..8d849c15a 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -164,12 +164,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
index b08e3aaf1..7b793d7b7 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 18:45:50
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:20:07
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 0bdccd82b..4142f5d9a 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 558313                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 262448                       # Number of bytes of host memory used
-host_seconds                                   178.74                       # Real time elapsed on the host
-host_tick_rate                              744762819                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2031292                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 221580                       # Number of bytes of host memory used
+host_seconds                                    49.13                       # Real time elapsed on the host
+host_tick_rate                             2709639216                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    99791663                       # Number of instructions simulated
 sim_seconds                                  0.133117                       # Number of seconds simulated
@@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses           159998                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.995345                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4076.934010                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995345                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           46990235                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 47946.924337                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337                       # average overall mshr miss latency
@@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses            18908                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.847746                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1736.182852                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.847746                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           78145078                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 24211.233340                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
@@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses          133917                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.066099                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.489066                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          2165.921088                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         16025.699940                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.066099                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.489066                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            178906                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -264,6 +264,6 @@ system.cpu.num_int_register_writes           73126599                       # nu
 system.cpu.num_load_insts                    27307109                       # Number of load instructions
 system.cpu.num_mem_refs                      47862848                       # number of memory refs
 system.cpu.num_store_insts                   20555739                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
index 7f5789393..8359194cf 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:14:11
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:19:52
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index d6bfda298..25cfa073d 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1204089                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 228576                       # Number of bytes of host memory used
-host_seconds                                   113.06                       # Real time elapsed on the host
-host_tick_rate                              602742669                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4754404                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206464                       # Number of bytes of host memory used
+host_seconds                                    28.63                       # Real time elapsed on the host
+host_tick_rate                             2379947985                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136139203                       # Number of instructions simulated
 sim_seconds                                  0.068149                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes          113225733                       # nu
 system.cpu.num_load_insts                    37275868                       # Number of load instructions
 system.cpu.num_mem_refs                      58160249                       # number of memory refs
 system.cpu.num_store_insts                   20884381                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 8ec9f75ef..4d41b9cb9 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
index b27952d03..0a7053375 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:13:39
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:21:09
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index eb6eca0bd..f75c53329 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 463084                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 236284                       # Number of bytes of host memory used
-host_seconds                                   293.98                       # Real time elapsed on the host
-host_tick_rate                              690315679                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2437881                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214216                       # Number of bytes of host memory used
+host_seconds                                    55.84                       # Real time elapsed on the host
+host_tick_rate                             3634125508                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136139203                       # Number of instructions simulated
 sim_seconds                                  0.202942                       # Number of seconds simulated
@@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses           150663                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997953                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4087.617150                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997953                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           58095605                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 49432.508313                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 46432.508313                       # average overall mshr miss latency
@@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses           187024                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.978868                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           2004.721102                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.978868                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          134553584                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 16930.864488                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 13930.864488                       # average overall mshr miss latency
@@ -183,10 +183,10 @@ system.cpu.l2cache.demand_mshr_misses          140161                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.121030                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.481204                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          3965.924560                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         15768.107062                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.121030                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.481204                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses            337702                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -228,6 +228,6 @@ system.cpu.num_int_register_writes          113225732                       # nu
 system.cpu.num_load_insts                    37275868                       # Number of load instructions
 system.cpu.num_mem_refs                      58160249                       # number of memory refs
 system.cpu.num_store_insts                   20884381                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
index 95d2d20dc..6cb2c5232 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
@@ -86,6 +86,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +122,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -156,6 +158,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout
index febae9611..6c62eaee3 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 27 2011 03:06:45
-M5 revision baf4b5f6782e 8094 default tip
-M5 started Feb 27 2011 03:13:10
-M5 executing on zizzer
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:24
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index 68c508b83..3b06d5b45 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,37 +1,25 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 121455                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1130520                       # Number of bytes of host memory used
-host_seconds                                 14983.11                       # Real time elapsed on the host
-host_tick_rate                               65403738                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 191712                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1122860                       # Number of bytes of host memory used
+host_seconds                                  9492.28                       # Real time elapsed on the host
+host_tick_rate                              103236678                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_seconds                                  0.979951                       # Number of seconds simulated
 sim_ticks                                979951369500                       # Number of ticks simulated
-system.cpu.AGEN-Unit.agens                  614316005                       # Number of Address Generations
-system.cpu.Branch-Predictor.BTBHitPct       69.872947                       # BTB Hit Percentage
-system.cpu.Branch-Predictor.BTBHits          82064192                       # Number of BTB hits
-system.cpu.Branch-Predictor.BTBLookups      117447733                       # Number of BTB lookups
-system.cpu.Branch-Predictor.RASInCorrect            6                       # Number of incorrect RAS predictions.
-system.cpu.Branch-Predictor.condIncorrect     79224651                       # Number of conditional branches incorrect
-system.cpu.Branch-Predictor.condPredicted    175157411                       # Number of conditional branches predicted
-system.cpu.Branch-Predictor.lookups         253574750                       # Number of BP lookups
-system.cpu.Branch-Predictor.predictedNotTaken    124923988                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken    128650762                       # Number of Branches Predicted As Taken (True).
-system.cpu.Branch-Predictor.usedRAS          16767439                       # Number of times the RAS was used to get a target.
-system.cpu.Execution-Unit.executions       1162207758                       # Number of Instructions Executed.
-system.cpu.Execution-Unit.mispredictPct     36.911759                       # Percentage of Incorrect Branches Predicts
-system.cpu.Execution-Unit.mispredicted       79224651                       # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predicted         135407901                       # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predictedNotTakenIncorrect     71572967                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.Execution-Unit.predictedTakenIncorrect      7651684                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.Mult-Div-Unit.divides                    0                       # Number of Divide Operations Executed
-system.cpu.Mult-Div-Unit.multiplies                75                       # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses   3178023708                       # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads    1801820745                       # Number of Reads from Register File
-system.cpu.RegFile-Manager.regFileWrites   1376202963                       # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards      604786987                       # Number of Registers Read Through Forwarding Logic
 system.cpu.activity                         74.309805                       # Percentage of cycles cpu is active
+system.cpu.agen_unit.agens                  614316005                       # Number of Address Generations
+system.cpu.branch_predictor.BTBHitPct       69.872947                       # BTB Hit Percentage
+system.cpu.branch_predictor.BTBHits          82064192                       # Number of BTB hits
+system.cpu.branch_predictor.BTBLookups      117447733                       # Number of BTB lookups
+system.cpu.branch_predictor.RASInCorrect            6                       # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.condIncorrect     79224651                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.condPredicted    175157411                       # Number of conditional branches predicted
+system.cpu.branch_predictor.lookups         253574750                       # Number of BP lookups
+system.cpu.branch_predictor.predictedNotTaken    124923988                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.branch_predictor.predictedTaken    128650762                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.usedRAS          16767439                       # Number of times the RAS was used to get a target.
 system.cpu.comBranches                      214632552                       # Number of Branches instructions committed
 system.cpu.comFloats                              190                       # Number of Floating Point instructions committed
 system.cpu.comInts                          916086844                       # Number of Integer instructions committed
@@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses          9111643                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.996505                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4081.685602                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.996505                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          605324165                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 27335.708502                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 23594.611641                       # average overall mshr miss latency
@@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses               162429806                       # DT
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_hits                   160728502                       # DTB write hits
 system.cpu.dtb.write_misses                   1701304                       # DTB write misses
+system.cpu.execution_unit.executions       1162207758                       # Number of Instructions Executed.
+system.cpu.execution_unit.mispredictPct     36.911759                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.mispredicted       79224651                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted         135407901                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predictedNotTakenIncorrect     71572967                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.predictedTakenIncorrect      7651684                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.icache.ReadReq_accesses          207004701                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 54777.453839                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 53438.372093                       # average ReadReq mshr miss latency
@@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses              860                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.324416                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            664.403935                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.324416                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          207004701                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 54777.453839                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 53438.372093                       # average overall mshr miss latency
@@ -246,10 +240,10 @@ system.cpu.l2cache.demand_mshr_misses         2697152                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.458476                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.337280                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0         15023.339345                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         11052.003329                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.458476                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.337280                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           9112503                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 52212.225711                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 40035.092201                       # average overall mshr miss latency
@@ -271,31 +265,37 @@ system.cpu.l2cache.tagsinuse             26075.342674                       # Cy
 system.cpu.l2cache.total_refs                 7565242                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          230207194000                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                 1170923                       # number of writebacks
+system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.mult_div_unit.multiplies                75                       # Number of Multipy Operations Executed
 system.cpu.numCycles                       1959902740                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.regfile_manager.regFileAccesses   3178023708                       # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.regfile_manager.regFileReads    1801820745                       # Number of Reads from Register File
+system.cpu.regfile_manager.regFileWrites   1376202963                       # Number of Writes to Register File
+system.cpu.regfile_manager.regForwards      604786987                       # Number of Registers Read Through Forwarding Logic
 system.cpu.runCycles                       1456399909                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles               902142172                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-0.runCycles               1057760568                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization              53.970054                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles              1064240534                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles                895662206                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization              45.699319                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles              1036315285                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-2.runCycles                923587455                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization              47.124147                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles              1537492347                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-3.runCycles                422410393                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization              21.552620                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles               932643705                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-4.runCycles               1027259035                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization              52.413776                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage0.idleCycles                902142172                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                1057760568                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               53.970054                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles               1064240534                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                 895662206                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               45.699319                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles               1036315285                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                 923587455                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               47.124147                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles               1537492347                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                 422410393                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               21.552620                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                932643705                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                1027259035                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               52.413776                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.threadCycles                    1619523667                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.timesIdled                         8517352                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
+system.cpu.workload.num_syscalls                   29                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 2659460cd..73cbafb08 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 141143bd2..489ef9061 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 21:44:37
-M5 started Mar 17 2011 21:44:53
-M5 executing on zizzer
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:02:34
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 5851c27dd..bd83aa84a 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 172436                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 208600                       # Number of bytes of host memory used
-host_seconds                                 10067.76                       # Real time elapsed on the host
-host_tick_rate                               69724149                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 279473                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204448                       # Number of bytes of host memory used
+host_seconds                                  6211.84                       # Real time elapsed on the host
+host_tick_rate                              113004567                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_seconds                                  0.701966                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect           19849428                       # Nu
 system.cpu.BPredUnit.condPredicted          261227143                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                338874509                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                 23706003                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches              214632552                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          64109829                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples   1311318680                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.387748                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     2.144873                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    679377178     51.81%     51.81% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    251802247     19.20%     71.01% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2    122784402      9.36%     80.37% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     79744679      6.08%     86.46% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     49330681      3.76%     90.22% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5     25797964      1.97%     92.18% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6     24618038      1.88%     94.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7     13753662      1.05%     95.11% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     64109829      4.89%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total   1311318680                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                1819780126                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                 805525                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls         16767440                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts            1718967519                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                 444595663                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  605324165                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts          19848912                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                  214632552                       # Number of branches committed
+system.cpu.commit.bw_lim_events              64109829                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts     1819780126                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts       560481052                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples   1311318680                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.387748                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.144873                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    679377178     51.81%     51.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    251802247     19.20%     71.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    122784402      9.36%     80.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     79744679      6.08%     86.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     49330681      3.76%     90.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     25797964      1.97%     92.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     24618038      1.88%     94.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     13753662      1.05%     95.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     64109829      4.89%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1311318680                       # Number of insts commited each cycle
+system.cpu.commit.count                    1819780126                       # Number of instructions committed
+system.cpu.commit.fp_insts                     805525                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls             16767440                       # Number of function calls committed.
+system.cpu.commit.int_insts                1718967519                       # Number of committed integer instructions.
+system.cpu.commit.loads                     444595663                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                      605324165                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1736043781                       # Number of Instructions Simulated
 system.cpu.cpi                               0.808697                       # CPI: Cycles Per Instruction
@@ -106,8 +106,8 @@ system.cpu.dcache.demand_mshr_misses          9161274                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997370                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4085.228479                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997370                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          684893373                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 19952.876714                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 12930.225374                       # average overall mshr miss latency
@@ -129,15 +129,15 @@ system.cpu.dcache.tagsinuse               4085.228479                       # Cy
 system.cpu.dcache.total_refs                670151457                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             7052593000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                  3077964                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       69300100                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred            734                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved      53326576                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts      2753583044                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         704925020                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          533426665                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        83930076                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts           1732                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles        3666895                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles              69300100                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                   734                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved             53326576                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts             2753583044                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                704925020                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                 533426665                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles               83930076                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                  1732                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles               3666895                       # Number of cycles decode is unblocking
 system.cpu.dtb.data_accesses                776927298                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                    761318004                       # DTB hits
@@ -217,8 +217,8 @@ system.cpu.icache.demand_mshr_misses              913                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.349808                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            716.407669                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.349808                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          346935606                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 35242.436306                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 35438.663746                       # average overall mshr miss latency
@@ -241,21 +241,13 @@ system.cpu.icache.total_refs                346934350                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                         8683896                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                278210520                       # Number of branches executed
-system.cpu.iew.EXEC:nop                     128264130                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.613458                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    776927311                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                  203625107                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                1505740839                       # num instructions consuming a value
-system.cpu.iew.WB:count                    2224607717                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.814091                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                1225810379                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.584554                       # insts written-back per cycle
-system.cpu.iew.WB:sent                     2246216503                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts             21671278                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                278210520                       # Number of branches executed
+system.cpu.iew.exec_nop                     128264130                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.613458                       # Inst execution rate
+system.cpu.iew.exec_refs                    776927311                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                  203625107                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                12833645                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts             610412990                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                 45                       # Number of dispatched non-speculative instructions
@@ -283,103 +275,93 @@ system.cpu.iew.lsq.thread.0.squashedStores     66687540                       #
 system.cpu.iew.memOrderViolationEvents         198174                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      3374280                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect       18296998                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                1505740839                       # num instructions consuming a value
+system.cpu.iew.wb_count                    2224607717                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.814091                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                1225810379                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.584554                       # insts written-back per cycle
+system.cpu.iew.wb_sent                     2246216503                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads               3052265091                       # number of integer regfile reads
 system.cpu.int_regfile_writes              1775418368                       # number of integer regfile writes
 system.cpu.ipc                               1.236558                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.236558                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu      1511867682     65.65%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult             94      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd           234      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp            19      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt           136      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult           16      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv            24      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     65.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      584171534     25.37%     91.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite     206823272      8.98%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total       2302863011                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt              12654324                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.005495                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu           2979112     23.54%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     23.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          7017383     55.45%     79.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite         2657829     21.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples   1395248756                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.650504                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.793673                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     526952247     37.77%     37.77% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     258740979     18.54%     56.31% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2     229473715     16.45%     72.76% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3     137779252      9.87%     82.63% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4     109981774      7.88%     90.52% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      76286512      5.47%     95.98% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6      43503715      3.12%     99.10% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7      10789596      0.77%     99.88% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8       1740966      0.12%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total   1395248756                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.640295                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1511867682     65.65%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                   94      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 234      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  19      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                 136      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 16      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                  24      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.65% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            584171534     25.37%     91.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           206823272      8.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             2302863011                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                  821696                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads             1643378                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses       816998                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes             858249                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                    12654324                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.005495                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2979112     23.54%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     23.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                7017383     55.45%     79.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2657829     21.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses             2314695639                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads         6012429707                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses   2223790719                       # Number of integer instruction queue wakeup accesses
@@ -391,6 +373,24 @@ system.cpu.iq.iqSquashedInstsExamined       686898644                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            443983                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined    276282436                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples    1395248756                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.650504                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.793673                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           526952247     37.77%     37.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           258740979     18.54%     56.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           229473715     16.45%     72.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           137779252      9.87%     82.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           109981774      7.88%     90.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            76286512      5.47%     95.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            43503715      3.12%     99.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            10789596      0.77%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1740966      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1395248756                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.640295                       # Inst issue rate
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
@@ -451,10 +451,10 @@ system.cpu.l2cache.demand_mshr_misses         2703837                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.482747                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.327799                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0         15818.650272                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         10741.307183                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.482747                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.327799                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           9162188                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34369.172587                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31180.345746                       # average overall mshr miss latency
@@ -485,28 +485,28 @@ system.cpu.misc_regfile_writes                      1                       # nu
 system.cpu.numCycles                       1403932652                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         45015493                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps     1376202963                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents         2058465                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         721970868                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents       19605286                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents         493414                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     3482054752                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      2693944594                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands   2019690549                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          519735088                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        83930076                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       24596395                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps         643487586                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups       875387                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups   3481179365                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles          836                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts           50                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           51588618                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts           48                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                45015493                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                2058465                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                721970868                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents              19605286                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                493414                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups            3482054752                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts             2693944594                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands          2019690549                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                 519735088                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles               83930076                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles              24596395                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                643487586                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups            875387                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups       3481179365                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles            836                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts                 50                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                  51588618                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts             48                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                   3541690829                       # The number of ROB reads
 system.cpu.rob.rob_writes                  4844528665                       # The number of ROB writes
 system.cpu.timesIdled                          283673                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
+system.cpu.workload.num_syscalls                   29                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
index 56c0d3893..5e9a97c65 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:37
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:59:33
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index 7812c0d15..c03fa7e28 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1468260                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 218108                       # Number of bytes of host memory used
-host_seconds                                  1239.41                       # Real time elapsed on the host
-host_tick_rate                              736791940                       # Simulator tick rate (ticks/s)
+host_inst_rate                                6003103                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195756                       # Number of bytes of host memory used
+host_seconds                                   303.14                       # Real time elapsed on the host
+host_tick_rate                             3012433327                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_seconds                                  0.913189                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes         1376202618                       # nu
 system.cpu.num_load_insts                   449492741                       # Number of load instructions
 system.cpu.num_mem_refs                     611922547                       # number of memory refs
 system.cpu.num_store_insts                  162429806                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
+system.cpu.workload.num_syscalls                   29                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 6d6374beb..6ccdf7868 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
index b361f245f..6c70cf5a2 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:37
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:59:01
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index f893b334a..315c5ad86 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 590383                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 225824                       # Number of bytes of host memory used
-host_seconds                                  3082.37                       # Real time elapsed on the host
-host_tick_rate                              864089077                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2523486                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203508                       # Number of bytes of host memory used
+host_seconds                                   721.14                       # Real time elapsed on the host
+host_tick_rate                             3693391340                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_seconds                                  2.663444                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses          9111734                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.995973                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4079.504248                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995973                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          605324165                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 26428.412638                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638                       # average overall mshr miss latency
@@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses              802                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.299002                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            612.356766                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.299002                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses         1826378510                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses         2697097                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.467301                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.327380                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0         15312.508302                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         10727.578894                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.467301                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.327380                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           9112536                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -250,6 +250,6 @@ system.cpu.num_int_register_writes         1376202618                       # nu
 system.cpu.num_load_insts                   449492741                       # Number of load instructions
 system.cpu.num_mem_refs                     611922547                       # number of memory refs
 system.cpu.num_store_insts                  162429806                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
+system.cpu.workload.num_syscalls                   29                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 5d9a2313d..2386e9fa4 100644
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -498,7 +498,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
index cc554e99a..dc1adbfd8 100755
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 18:48:59
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:21:07
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index a38ba9b9e..5a7da6a72 100644
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 189685                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 258720                       # Number of bytes of host memory used
-host_seconds                                  9083.85                       # Real time elapsed on the host
-host_tick_rate                               70772893                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 253143                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 215164                       # Number of bytes of host memory used
+host_seconds                                  6806.72                       # Real time elapsed on the host
+host_tick_rate                               94449374                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1723073854                       # Number of instructions simulated
 sim_seconds                                  0.642891                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect           18005065                       # Nu
 system.cpu.BPredUnit.condPredicted          242843937                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                296310364                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                 17771313                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches              213462366                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          57604302                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples   1166659925                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.476929                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     2.106061                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    510754561     43.78%     43.78% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    303447125     26.01%     69.79% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2    123940356     10.62%     80.41% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     73811223      6.33%     86.74% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     36743344      3.15%     89.89% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5     32005168      2.74%     92.63% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6     15998188      1.37%     94.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7     12355658      1.06%     95.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     57604302      4.94%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total   1166659925                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                1723073872                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                     36                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls         13665177                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts            1536941857                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                 485926772                       # Number of loads committed
-system.cpu.commit.COM:membars                      62                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  660773819                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts          18004568                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                  213462366                       # Number of branches committed
+system.cpu.commit.bw_lim_events              57604302                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts     1723073872                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls             458                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts       488146148                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples   1166659925                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.476929                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.106061                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    510754561     43.78%     43.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    303447125     26.01%     69.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    123940356     10.62%     80.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     73811223      6.33%     86.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     36743344      3.15%     89.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     32005168      2.74%     92.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     15998188      1.37%     94.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     12355658      1.06%     95.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     57604302      4.94%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1166659925                       # Number of insts commited each cycle
+system.cpu.commit.count                    1723073872                       # Number of instructions committed
+system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
+system.cpu.commit.int_insts                1536941857                       # Number of committed integer instructions.
+system.cpu.commit.loads                     485926772                       # Number of loads committed
+system.cpu.commit.membars                          62                       # Number of memory barriers committed
+system.cpu.commit.refs                      660773819                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                  1723073854                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1723073854                       # Number of Instructions Simulated
 system.cpu.cpi                               0.746214                       # CPI: Cycles Per Instruction
@@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses          9541290                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997826                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4087.096656                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997826                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          674170659                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 18251.409094                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 13363.406222                       # average overall mshr miss latency
@@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse               4087.096656                       # Cy
 system.cpu.dcache.total_refs                661474732                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             5035189000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                  3122149                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles      127119222                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred            630                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved      46145837                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts      2344585205                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         578307676                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          449658106                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        70439042                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts           2261                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles       11574920                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles             127119222                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                   630                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved             46145837                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts             2344585205                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                578307676                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                 449658106                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles               70439042                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                  2261                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles              11574920                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses              713                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.281945                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            577.423416                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.281945                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          276394619                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 34658.288770                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 34406.030856                       # average overall mshr miss latency
@@ -245,21 +245,13 @@ system.cpu.icache.total_refs                276393684                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                        48682141                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                233410057                       # Number of branches executed
-system.cpu.iew.EXEC:nop                           371                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.517006                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    747857641                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                  187754946                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                2256424150                       # num instructions consuming a value
-system.cpu.iew.WB:count                    1928710637                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.551017                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                1243327288                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.500030                       # insts written-back per cycle
-system.cpu.iew.WB:sent                     1934940770                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts             19351943                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                233410057                       # Number of branches executed
+system.cpu.iew.exec_nop                           371                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.517006                       # Inst execution rate
+system.cpu.iew.exec_refs                    747857641                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                  187754946                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                24201668                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts             626078428                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                573                       # Number of dispatched non-speculative instructions
@@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores     50405377                       #
 system.cpu.iew.memOrderViolationEvents         734835                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      3232685                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect       16119258                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                2256424150                       # num instructions consuming a value
+system.cpu.iew.wb_count                    1928710637                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.551017                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                1243327288                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.500030                       # insts written-back per cycle
+system.cpu.iew.wb_sent                     1934940770                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads               5040549881                       # number of integer regfile reads
 system.cpu.int_regfile_writes              1533135927                       # number of integer regfile writes
 system.cpu.ipc                               1.340099                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.340099                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu      1212590834     61.50%     61.50% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult        1140241      0.06%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             2      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            6      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            1      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            7      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     61.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      568540639     28.84%     90.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite     189395216      9.61%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total       1971666946                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt              20875026                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.010588                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu            491210      2.35%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                2      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      2.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead         19087912     91.44%     93.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite         1295902      6.21%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples   1237098966                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.593783                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.635374                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     418606363     33.84%     33.84% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     277983689     22.47%     56.31% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2     220653980     17.84%     74.14% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3     149807025     12.11%     86.25% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      89527255      7.24%     93.49% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      51723580      4.18%     97.67% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6      17902939      1.45%     99.12% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       8343412      0.67%     99.79% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8       2550723      0.21%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total   1237098966                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.533439                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1212590834     61.50%     61.50% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              1140241      0.06%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               6      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            568540639     28.84%     90.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           189395216      9.61%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total             1971666946                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                      63                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                 120                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           51                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                 94                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                    20875026                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010588                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  491210      2.35%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      2      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               19087912     91.44%     93.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               1295902      6.21%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses             1992541909                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads         5201971393                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses   1928710586                       # Number of integer instruction queue wakeup accesses
@@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined       484979968                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            663629                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved            179                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined    843902514                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples    1237098966                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.593783                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.635374                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           418606363     33.84%     33.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           277983689     22.47%     56.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           220653980     17.84%     74.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           149807025     12.11%     86.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            89527255      7.24%     93.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            51723580      4.18%     97.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            17902939      1.45%     99.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             8343412      0.67%     99.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             2550723      0.21%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1237098966                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.533439                       # Inst issue rate
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -461,10 +461,10 @@ system.cpu.l2cache.demand_mshr_misses         2931748                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.487988                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.329914                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0         15990.396178                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         10810.627507                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.487988                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.329914                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           9542003                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34375.299564                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.683001                       # average overall mshr miss latency
@@ -495,28 +495,28 @@ system.cpu.misc_regfile_writes                    128                       # nu
 system.cpu.numCycles                       1285781107                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         67172415                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps     1360917377                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents        14851346                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         600335413                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents       40774846                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents          10242                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     6331353991                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      2292668273                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands   1803116545                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          438383597                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        70439042                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       60752889                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps         442199165                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups          393                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups   6331353598                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles        15610                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts          650                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts          118137729                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts          645                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                67172415                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps            1360917377                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents               14851346                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                600335413                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents              40774846                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                 10242                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups            6331353991                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts             2292668273                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands          1803116545                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                 438383597                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles               70439042                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles              60752889                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                442199165                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups               393                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups       6331353598                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles          15610                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts                650                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                 118137729                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts            645                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                   3320275044                       # The number of ROB reads
 system.cpu.rob.rob_writes                  4492885352                       # The number of ROB writes
 system.cpu.timesIdled                         1544733                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
+system.cpu.workload.num_syscalls                   46                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index b27b25e6d..8d90d74d0 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -61,12 +61,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
index d37b6d85d..4e09f0c47 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 18:50:12
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:22:49
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index 0c882577d..bd13defc5 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1075067                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 247128                       # Number of bytes of host memory used
-host_seconds                                  1602.76                       # Real time elapsed on the host
-host_tick_rate                              537533999                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4004296                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206252                       # Number of bytes of host memory used
+host_seconds                                   430.31                       # Real time elapsed on the host
+host_tick_rate                             2002150173                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1723073862                       # Number of instructions simulated
 sim_seconds                                  0.861538                       # Number of seconds simulated
@@ -71,6 +71,6 @@ system.cpu.num_int_register_writes         1329729952                       # nu
 system.cpu.num_load_insts                   485926770                       # Number of load instructions
 system.cpu.num_mem_refs                     660773816                       # number of memory refs
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
+system.cpu.workload.num_syscalls                   46                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
index b26c9b5f5..00bc540f8 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -164,12 +164,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
index 50181b6ce..88386aeb5 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 19:14:16
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:25:15
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index b09cdeb30..1dcb25e1c 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 536583                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 254860                       # Number of bytes of host memory used
-host_seconds                                  3200.38                       # Real time elapsed on the host
-host_tick_rate                              759728459                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2103726                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213996                       # Number of bytes of host memory used
+host_seconds                                   816.30                       # Real time elapsed on the host
+host_tick_rate                             2978588238                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1717270343                       # Number of instructions simulated
 sim_seconds                                  2.431420                       # Number of seconds simulated
@@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses          9115236                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997002                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4083.719979                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997002                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses          654970174                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 26435.424162                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 23435.424162                       # average overall mshr miss latency
@@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses              638                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.251403                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            514.872896                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.251403                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses         1544565599                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 54551.724138                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138                       # average overall mshr miss latency
@@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses         2699469                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.458607                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.338956                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0         15027.621217                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         11106.896016                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.458607                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.338956                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           9115874                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -264,6 +264,6 @@ system.cpu.num_int_register_writes         1329729952                       # nu
 system.cpu.num_load_insts                   485926770                       # Number of load instructions
 system.cpu.num_mem_refs                     660773816                       # number of memory refs
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
+system.cpu.workload.num_syscalls                   46                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
index 403cb4d0b..fd345ce8f 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb  8 2011 00:58:34
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:22:46
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index 9e70ccdd1..3863ba265 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2540540                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 223860                       # Number of bytes of host memory used
-host_seconds                                  1844.83                       # Real time elapsed on the host
-host_tick_rate                             1542694185                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2952357                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202444                       # Number of bytes of host memory used
+host_seconds                                  1587.50                       # Real time elapsed on the host
+host_tick_rate                             1792761763                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  4686862651                       # Number of instructions simulated
 sim_seconds                                  2.846007                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes         4679057393                       # nu
 system.cpu.num_load_insts                  1239184749                       # Number of load instructions
 system.cpu.num_mem_refs                    1677713086                       # number of memory refs
 system.cpu.num_store_insts                  438528337                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
+system.cpu.workload.num_syscalls                   46                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
index a92ea4a1d..c75881c3f 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
index 65c0a8840..60300fa55 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb  8 2011 00:58:34
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:36:40
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index 59534c87e..e9ae83f48 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1546064                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 231584                       # Number of bytes of host memory used
-host_seconds                                  3031.48                       # Real time elapsed on the host
-host_tick_rate                             1954011316                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1878760                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 210192                       # Number of bytes of host memory used
+host_seconds                                  2494.66                       # Real time elapsed on the host
+host_tick_rate                             2374493636                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  4686862651                       # Number of instructions simulated
 sim_seconds                                  5.923548                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses          9112677                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997232                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           4084.662246                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997232                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses         1677713086                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 26521.034159                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159                       # average overall mshr miss latency
@@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses              675                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.271344                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            555.713137                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.271344                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses         4013232927                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses         2717345                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.472376                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.336564                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0         15478.805498                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1         11028.544571                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.472376                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.336564                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses           9113352                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -218,6 +218,6 @@ system.cpu.num_int_register_writes         4679057393                       # nu
 system.cpu.num_load_insts                  1239184749                       # Number of load instructions
 system.cpu.num_mem_refs                    1677713086                       # number of memory refs
 system.cpu.num_store_insts                  438528337                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
+system.cpu.workload.num_syscalls                   46                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
index 8ab14c5fa..84850f694 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
@@ -86,6 +86,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +122,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -156,6 +158,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
index d80de6314..21f9ae246 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 18 2011 15:40:30
-M5 revision Unknown
-M5 started Feb 18 2011 19:04:15
-M5 executing on m55-001.pool
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:01:01
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
 Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
 Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index b78683303..53d449590 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,37 +1,25 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 137731                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 254052                       # Number of bytes of host memory used
-host_seconds                                   667.27                       # Real time elapsed on the host
-host_tick_rate                               60742348                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 197293                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 267004                       # Number of bytes of host memory used
+host_seconds                                   465.82                       # Real time elapsed on the host
+host_tick_rate                               87010339                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_seconds                                  0.040531                       # Number of seconds simulated
 sim_ticks                                 40531279000                       # Number of ticks simulated
-system.cpu.AGEN-Unit.agens                   27308571                       # Number of Address Generations
-system.cpu.Branch-Predictor.BTBHitPct       59.146483                       # BTB Hit Percentage
-system.cpu.Branch-Predictor.BTBHits           4489525                       # Number of BTB hits
-system.cpu.Branch-Predictor.BTBLookups        7590519                       # Number of BTB lookups
-system.cpu.Branch-Predictor.RASInCorrect          138                       # Number of incorrect RAS predictions.
-system.cpu.Branch-Predictor.condIncorrect      2806970                       # Number of conditional branches incorrect
-system.cpu.Branch-Predictor.condPredicted      7883251                       # Number of conditional branches predicted
-system.cpu.Branch-Predictor.lookups          11539980                       # Number of BP lookups
-system.cpu.Branch-Predictor.predictedNotTaken      4913265                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken      6626715                       # Number of Branches Predicted As Taken (True).
-system.cpu.Branch-Predictor.usedRAS           1029619                       # Number of times the RAS was used to get a target.
-system.cpu.Execution-Unit.executions         57928840                       # Number of Instructions Executed.
-system.cpu.Execution-Unit.mispredictPct     27.409983                       # Percentage of Incorrect Branches Predicts
-system.cpu.Execution-Unit.mispredicted        2806970                       # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predicted           7433715                       # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predictedNotTakenIncorrect      1384945                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.Execution-Unit.predictedTakenIncorrect      1422025                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.Mult-Div-Unit.divides                    0                       # Number of Divide Operations Executed
-system.cpu.Mult-Div-Unit.multiplies            458252                       # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses    152685930                       # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads      84258569                       # Number of Reads from Register File
-system.cpu.RegFile-Manager.regFileWrites     68427361                       # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards       38185928                       # Number of Registers Read Through Forwarding Logic
 system.cpu.activity                         91.670040                       # Percentage of cycles cpu is active
+system.cpu.agen_unit.agens                   27308571                       # Number of Address Generations
+system.cpu.branch_predictor.BTBHitPct       59.146483                       # BTB Hit Percentage
+system.cpu.branch_predictor.BTBHits           4489525                       # Number of BTB hits
+system.cpu.branch_predictor.BTBLookups        7590519                       # Number of BTB lookups
+system.cpu.branch_predictor.RASInCorrect          138                       # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.condIncorrect      2806970                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.condPredicted      7883251                       # Number of conditional branches predicted
+system.cpu.branch_predictor.lookups          11539980                       # Number of BP lookups
+system.cpu.branch_predictor.predictedNotTaken      4913265                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.branch_predictor.predictedTaken      6626715                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.usedRAS           1029619                       # Number of times the RAS was used to get a target.
 system.cpu.comBranches                       10240685                       # Number of Branches instructions committed
 system.cpu.comFloats                          3775974                       # Number of Floating Point instructions committed
 system.cpu.comInts                           43665352                       # Number of Integer instructions committed
@@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses             2223                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.351931                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           1441.508051                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.351931                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 55469.292673                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 51941.745389                       # average overall mshr miss latency
@@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses                 6501126                       # DT
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_hits                     6501103                       # DTB write hits
 system.cpu.dtb.write_misses                        23                       # DTB write misses
+system.cpu.execution_unit.executions         57928840                       # Number of Instructions Executed.
+system.cpu.execution_unit.mispredictPct     27.409983                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.mispredicted        2806970                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted           7433715                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predictedNotTakenIncorrect      1384945                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.predictedTakenIncorrect      1422025                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.icache.ReadReq_accesses            9759564                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 26779.967317                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 23139.993880                       # average ReadReq mshr miss latency
@@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses             9804                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.729171                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1493.341252                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.729171                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses            9759564                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 26779.967317                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 23139.993880                       # average overall mshr miss latency
@@ -246,10 +240,10 @@ system.cpu.l2cache.demand_mshr_misses            4938                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.066327                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.000542                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          2173.408531                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1            17.762817                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.066327                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000542                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses             12027                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 52334.244633                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 40121.709194                       # average overall mshr miss latency
@@ -271,31 +265,37 @@ system.cpu.l2cache.tagsinuse              2191.171348                       # Cy
 system.cpu.l2cache.total_refs                    7072                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.mult_div_unit.multiplies            458252                       # Number of Multipy Operations Executed
 system.cpu.numCycles                         81062559                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.regfile_manager.regFileAccesses    152685930                       # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.regfile_manager.regFileReads      84258569                       # Number of Reads from Register File
+system.cpu.regfile_manager.regFileWrites     68427361                       # Number of Writes to Register File
+system.cpu.regfile_manager.regForwards       38185928                       # Number of Registers Read Through Forwarding Logic
 system.cpu.runCycles                         74310080                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles                27951091                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-0.runCycles                 53111468                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization              65.519111                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles                33262621                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles                 47799938                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization              58.966727                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles                32674404                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-2.runCycles                 48388155                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization              59.692361                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles                63236282                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-3.runCycles                 17826277                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization              21.990765                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles                26883065                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-4.runCycles                 54179494                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization              66.836644                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage0.idleCycles                 27951091                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                  53111468                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               65.519111                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                 33262621                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                  47799938                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               58.966727                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                 32674404                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                  48388155                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               59.692361                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                 63236282                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                  17826277                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               21.990765                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                 26883065                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                  54179494                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               66.836644                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.threadCycles                      80607865                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.timesIdled                           10786                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
+system.cpu.workload.num_syscalls                  389                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 0fa57e7b8..9d0ac975a 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
index c1340f659..ec6c3f639 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 21:44:37
-M5 started Mar 17 2011 21:44:40
-M5 executing on zizzer
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:35
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index c969dd1c3..8dc1a35af 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 141441                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 212592                       # Number of bytes of host memory used
-host_seconds                                   595.16                       # Real time elapsed on the host
-host_tick_rate                               57448767                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 274016                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 208580                       # Number of bytes of host memory used
+host_seconds                                   307.21                       # Real time elapsed on the host
+host_tick_rate                              111296260                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_seconds                                  0.034191                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect            1952481                       # Nu
 system.cpu.BPredUnit.condPredicted           13040695                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                 17634633                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                  1674129                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               10240685                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           3636559                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples     62672395                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.466404                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     2.205429                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     30204906     48.19%     48.19% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     13903993     22.19%     70.38% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2      6182558      9.86%     80.24% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      3801476      6.07%     86.31% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      2048830      3.27%     89.58% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      1270161      2.03%     91.61% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6       776463      1.24%     92.85% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       847449      1.35%     94.20% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      3636559      5.80%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total     62672395                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                  91903055                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                6862061                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls          1029620                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts              79581076                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                  19996198                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   26497301                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts           1939282                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                   10240685                       # Number of branches committed
+system.cpu.commit.bw_lim_events               3636559                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts       91903055                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts        35667755                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples     62672395                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.466404                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.205429                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     30204906     48.19%     48.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     13903993     22.19%     70.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      6182558      9.86%     80.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3801476      6.07%     86.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2048830      3.27%     89.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1270161      2.03%     91.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       776463      1.24%     92.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       847449      1.35%     94.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3636559      5.80%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     62672395                       # Number of insts commited each cycle
+system.cpu.commit.count                      91903055                       # Number of instructions committed
+system.cpu.commit.fp_insts                    6862061                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls              1029620                       # Number of function calls committed.
+system.cpu.commit.int_insts                  79581076                       # Number of committed integer instructions.
+system.cpu.commit.loads                      19996198                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                       26497301                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedInsts_total              84179709                       # Number of Instructions Simulated
 system.cpu.cpi                               0.812335                       # CPI: Cycles Per Instruction
@@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses             2243                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.356334                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           1459.544584                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.356334                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           30021191                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 34866.834452                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 34674.765938                       # average overall mshr miss latency
@@ -121,15 +121,15 @@ system.cpu.dcache.tagsinuse               1459.544584                       # Cy
 system.cpu.dcache.total_refs                 30012261                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                      109                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles         838288                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          13474                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved       2813146                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts       143267385                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          35496040                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           26313036                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         5601227                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts          49112                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles          25031                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles                838288                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                 13474                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved              2813146                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts              143267385                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                 35496040                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                  26313036                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                5601227                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                 49112                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles                 25031                       # Number of cycles decode is unblocking
 system.cpu.dtb.data_accesses                 32239873                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                     31883201                       # DTB hits
@@ -209,8 +209,8 @@ system.cpu.icache.demand_mshr_misses            10134                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.755537                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1547.340406                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.755537                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           17397269                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 15677.629201                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 11875.370041                       # average overall mshr miss latency
@@ -233,21 +233,13 @@ system.cpu.icache.total_refs                 17386201                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                          108531                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 12448390                       # Number of branches executed
-system.cpu.iew.EXEC:nop                      11194543                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.455255                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     32240280                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                    7278167                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                  87558338                       # num instructions consuming a value
-system.cpu.iew.WB:count                      97422402                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.737743                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                  64595544                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.424676                       # insts written-back per cycle
-system.cpu.iew.WB:sent                       98290476                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts              2083154                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                 12448390                       # Number of branches executed
+system.cpu.iew.exec_nop                      11194543                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.455255                       # Inst execution rate
+system.cpu.iew.exec_refs                     32240280                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                    7278167                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                   54226                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts              28836221                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                434                       # Number of dispatched non-speculative instructions
@@ -275,103 +267,93 @@ system.cpu.iew.lsq.thread.0.squashedStores      2710213                       #
 system.cpu.iew.memOrderViolationEvents         361752                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       455682                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        1627472                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                  87558338                       # num instructions consuming a value
+system.cpu.iew.wb_count                      97422402                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.737743                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                  64595544                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.424676                       # insts written-back per cycle
+system.cpu.iew.wb_sent                       98290476                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                134796814                       # number of integer regfile reads
 system.cpu.int_regfile_writes                73485618                       # number of integer regfile writes
 system.cpu.ipc                               1.231019                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.231019                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            7      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu        61903709     60.72%     60.72% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult         478641      0.47%     61.19% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     61.19% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd       2776827      2.72%     63.91% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp        114478      0.11%     64.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt       2390013      2.34%     66.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult       305170      0.30%     66.66% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv        758780      0.74%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt          320      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     67.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       25831010     25.34%     92.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite       7397506      7.26%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        101956461                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               1618550                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.015875                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu            211558     13.07%     13.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     13.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     13.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd             411      0.03%     13.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     13.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     13.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult           1262      0.08%     13.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv          831302     51.36%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     64.54% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead           469173     28.99%     93.52% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          104844      6.48%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples     68273622                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.493351                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.698376                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      26699327     39.11%     39.11% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      15011311     21.99%     61.09% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      10325819     15.12%     76.22% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3       6572668      9.63%     85.84% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4       4677869      6.85%     92.70% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       2930251      4.29%     96.99% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       1292691      1.89%     98.88% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        652857      0.96%     99.84% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        110829      0.16%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total     68273622                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.490981                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              61903709     60.72%     60.72% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               478641      0.47%     61.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2776827      2.72%     63.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp              114478      0.11%     64.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2390013      2.34%     66.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult             305170      0.30%     66.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv              758780      0.74%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                320      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             25831010     25.34%     92.74% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7397506      7.26%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              101956461                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                 7926911                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads            15016184                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses      7008699                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes            8486129                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                     1618550                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.015875                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  211558     13.07%     13.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     13.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     13.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                   411      0.03%     13.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     13.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     13.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                 1262      0.08%     13.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                831302     51.36%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 469173     28.99%     93.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                104844      6.48%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses               95648093                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads          258930448                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses     90413703                       # Number of integer instruction queue wakeup accesses
@@ -383,6 +365,24 @@ system.cpu.iq.iqSquashedInstsExamined        30709271                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            141538                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             45                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined     24277340                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples      68273622                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.493351                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.698376                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            26699327     39.11%     39.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            15011311     21.99%     61.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            10325819     15.12%     76.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6572668      9.63%     85.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4677869      6.85%     92.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2930251      4.29%     96.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1292691      1.89%     98.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              652857      0.96%     99.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              110829      0.16%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        68273622                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.490981                       # Inst issue rate
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
@@ -443,10 +443,10 @@ system.cpu.l2cache.demand_mshr_misses            5098                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.070076                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.000540                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          2296.266103                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1            17.691689                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.070076                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000540                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses             12377                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34375.147117                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.357395                       # average overall mshr miss latency
@@ -477,27 +477,27 @@ system.cpu.misc_regfile_writes                      1                       # nu
 system.cpu.numCycles                         68382153                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles           332303                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps       68427361                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents           66062                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          36404617                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents         424450                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups      178909439                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       138778599                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    101591818                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           25415273                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         5601227                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles         515125                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          33164457                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups      9732280                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups    169177159                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles         5077                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts          469                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts            1208043                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts          457                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                  332303                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                  66062                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                 36404617                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents                424450                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenameLookups             178909439                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts              138778599                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands           101591818                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                  25415273                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                5601227                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles                515125                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                 33164457                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups           9732280                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups        169177159                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles           5077                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts                469                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                   1208043                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts            457                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                    186605606                       # The number of ROB reads
 system.cpu.rob.rob_writes                   260771760                       # The number of ROB writes
 system.cpu.timesIdled                            2331                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
+system.cpu.workload.num_syscalls                  389                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
index 06628f244..8a2d657fe 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:38
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:02:07
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
 Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
 Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index 3667c8fef..17088cdf6 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1609489                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 222008                       # Number of bytes of host memory used
-host_seconds                                    57.10                       # Real time elapsed on the host
-host_tick_rate                              804741446                       # Simulator tick rate (ticks/s)
+host_inst_rate                                5556970                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199664                       # Number of bytes of host memory used
+host_seconds                                    16.54                       # Real time elapsed on the host
+host_tick_rate                             2778455792                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_seconds                                  0.045952                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes           62575473                       # nu
 system.cpu.num_load_insts                    19996208                       # Number of load instructions
 system.cpu.num_mem_refs                      26497334                       # number of memory refs
 system.cpu.num_store_insts                    6501126                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
+system.cpu.workload.num_syscalls                  389                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index cab9a523d..f2a594baf 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
index 5503045c3..c82977f3d 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:48
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:05:08
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
 Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav
 Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index 2aaa18b18..ea7e649f7 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 559604                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 229724                       # Number of bytes of host memory used
-host_seconds                                   164.23                       # Real time elapsed on the host
-host_tick_rate                              723015392                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2623121                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 207408                       # Number of bytes of host memory used
+host_seconds                                    35.04                       # Real time elapsed on the host
+host_tick_rate                             3389091421                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_seconds                                  0.118740                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses             2223                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.352058                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           1442.028823                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.352058                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 54507.422402                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402                       # average overall mshr miss latency
@@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses             8510                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.692401                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1418.037996                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.692401                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           91903090                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 26935.605170                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170                       # average overall mshr miss latency
@@ -205,10 +205,10 @@ system.cpu.l2cache.demand_mshr_misses            4765                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.062752                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.000543                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          2056.253411                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1            17.795183                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.062752                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000543                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses             10733                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -250,6 +250,6 @@ system.cpu.num_int_register_writes           62575473                       # nu
 system.cpu.num_load_insts                    19996208                       # Number of load instructions
 system.cpu.num_mem_refs                      26497334                       # number of memory refs
 system.cpu.num_store_insts                    6501126                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
+system.cpu.workload.num_syscalls                  389                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
index 0db8749b7..6ac40b8d3 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -498,7 +498,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
index 0ed791575..573beb25f 100755
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 19:17:05
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:27:04
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing
+Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
index cc80406fa..cc9da8f96 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 145657                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 262540                       # Number of bytes of host memory used
-host_seconds                                  1295.30                       # Real time elapsed on the host
-host_tick_rate                               97115047                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 180598                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 218960                       # Number of bytes of host memory used
+host_seconds                                  1044.69                       # Real time elapsed on the host
+host_tick_rate                              120412102                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   188669132                       # Number of instructions simulated
 sim_seconds                                  0.125793                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect            9866046                       # Nu
 system.cpu.BPredUnit.condPredicted           86389460                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                110931092                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                  4559844                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               40284207                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           1785335                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    224388172                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.840880                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.269231                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    118836869     52.96%     52.96% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     58355167     26.01%     78.97% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     31951737     14.24%     93.21% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      7144506      3.18%     96.39% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      2914461      1.30%     97.69% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      1962763      0.87%     98.56% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6       824316      0.37%     98.93% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       613018      0.27%     99.20% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      1785335      0.80%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    224388172                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                 188683520                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                1752310                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls          1848934                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts             150271150                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                  29852009                       # Number of loads committed
-system.cpu.commit.COM:membars                   22408                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   42499167                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts           9726959                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                   40284207                       # Number of branches committed
+system.cpu.commit.bw_lim_events               1785335                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts      188683520                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls         1635919                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts       179794570                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples    224388172                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.840880                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.269231                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    118836869     52.96%     52.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     58355167     26.01%     78.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     31951737     14.24%     93.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      7144506      3.18%     96.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2914461      1.30%     97.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1962763      0.87%     98.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       824316      0.37%     98.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       613018      0.27%     99.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1785335      0.80%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    224388172                       # Number of insts commited each cycle
+system.cpu.commit.count                     188683520                       # Number of instructions committed
+system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
+system.cpu.commit.int_insts                 150271150                       # Number of committed integer instructions.
+system.cpu.commit.loads                      29852009                       # Number of loads committed
+system.cpu.commit.membars                       22408                       # Number of memory barriers committed
+system.cpu.commit.refs                       42499167                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                   188669132                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             188669132                       # Number of Instructions Simulated
 system.cpu.cpi                               1.333479                       # CPI: Cycles Per Instruction
@@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses             1827                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.338856                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           1387.955871                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.338856                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           50846441                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 31573.330399                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 33963.054187                       # average overall mshr miss latency
@@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse               1387.955871                       # Cy
 system.cpu.dcache.total_refs                 50888924                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                       16                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       36464777                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred         170249                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved      17878904                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts       446600367                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          82272510                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          104826667                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        27129630                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts         707147                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles         824217                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles              36464777                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                170249                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved             17878904                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts              446600367                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                 82272510                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                 104826667                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles               27129630                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                707147                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles                824217                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -221,8 +221,8 @@ system.cpu.icache.demand_mshr_misses             3509                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.620491                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1270.764699                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.620491                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           38679890                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 23669.425633                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 20344.827586                       # average overall mshr miss latency
@@ -245,21 +245,13 @@ system.cpu.icache.total_refs                 38675903                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                           68606                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 53273558                       # Number of branches executed
-system.cpu.iew.EXEC:nop                         53064                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.964190                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     53783248                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   13613267                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 284801843                       # num instructions consuming a value
-system.cpu.iew.WB:count                     238885590                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.499623                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                 142293577                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.949517                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      240138833                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts             11160275                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                 53273558                       # Number of branches executed
+system.cpu.iew.exec_nop                         53064                       # number of nop insts executed
+system.cpu.iew.exec_rate                     0.964190                       # Inst execution rate
+system.cpu.iew.exec_refs                     53783248                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                   13613267                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                   19997                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts              50338304                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts            2241625                       # Number of dispatched non-speculative instructions
@@ -287,103 +279,93 @@ system.cpu.iew.lsq.thread.0.squashedStores      5462392                       #
 system.cpu.iew.memOrderViolationEvents         222499                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect      2295597                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        8864678                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                 284801843                       # num instructions consuming a value
+system.cpu.iew.wb_count                     238885590                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.499623                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                 142293577                       # num instructions producing a value
+system.cpu.iew.wb_rate                       0.949517                       # insts written-back per cycle
+system.cpu.iew.wb_sent                      240138833                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                542109498                       # number of integer regfile reads
 system.cpu.int_regfile_writes               231159216                       # number of integer regfile writes
 system.cpu.ipc                               0.749918                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.749918                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       192549438     76.89%     76.89% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult         913605      0.36%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd           7231      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     77.26% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd        32771      0.01%     77.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     77.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp       160968      0.06%     77.34% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt       255770      0.10%     77.44% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv        76475      0.03%     77.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc       457524      0.18%     77.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult       202683      0.08%     77.73% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc        71630      0.03%     77.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt          325      0.00%     77.76% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       41871023     16.72%     94.48% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      13821469      5.52%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        250420912                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               1580075                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.006310                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu                55      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult             5520      0.35%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          1266721     80.17%     80.52% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          307779     19.48%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    251517801                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.995639                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.196239                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     114687732     45.60%     45.60% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      66176551     26.31%     71.91% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      44052792     17.51%     89.42% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3      15274317      6.07%     95.50% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4       7530457      2.99%     98.49% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       2838961      1.13%     99.62% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6        766561      0.30%     99.92% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        123613      0.05%     99.97% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8         66817      0.03%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    251517801                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.995367                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             192549438     76.89%     76.89% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               913605      0.36%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                 7231      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     77.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd           32771      0.01%     77.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     77.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          160968      0.06%     77.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt          255770      0.10%     77.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv           76475      0.03%     77.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         457524      0.18%     77.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         202683      0.08%     77.73% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc        71630      0.03%     77.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt            325      0.00%     77.76% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             41871023     16.72%     94.48% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            13821469      5.52%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              250420912                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                 1881090                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads             3742288                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses      1821838                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes            2251906                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                     1580075                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006310                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      55      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   5520      0.35%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1266721     80.17%     80.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                307779     19.48%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses              250119897                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads          750424252                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses    237063752                       # Number of integer instruction queue wakeup accesses
@@ -395,6 +377,24 @@ system.cpu.iq.iqSquashedInstsExamined       177594377                       # Nu
 system.cpu.iq.iqSquashedInstsIssued            226843                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved         629835                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined    280770553                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples     251517801                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.995639                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.196239                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           114687732     45.60%     45.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            66176551     26.31%     71.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            44052792     17.51%     89.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            15274317      6.07%     95.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             7530457      2.99%     98.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2838961      1.13%     99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6              766561      0.30%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              123613      0.05%     99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               66817      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       251517801                       # Number of insts issued each cycle
+system.cpu.iq.rate                           0.995367                       # Inst issue rate
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -461,10 +461,10 @@ system.cpu.l2cache.demand_mshr_misses            3652                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.055915                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.000092                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          1832.230344                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1             3.029186                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.055915                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000092                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses              5336                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34289.940022                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31059.967141                       # average overall mshr miss latency
@@ -495,27 +495,27 @@ system.cpu.misc_regfile_writes                 825084                       # nu
 system.cpu.numCycles                        251586407                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles           895052                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps      180981200                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents          614225                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          90974405                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        2116730                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups      956098353                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       414819410                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    416850208                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           96863032                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        27129630                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        5258013                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps         235869004                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups     13790121                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups    942308232                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles     30397669                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts      2658319                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           23659926                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts      2454002                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                  895052                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps             180981200                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                 614225                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                 90974405                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents               2116730                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenameLookups             956098353                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts              414819410                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands           416850208                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                  96863032                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles               27129630                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles               5258013                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                235869004                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups          13790121                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups        942308232                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles       30397669                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts            2658319                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                  23659926                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts        2454002                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                    591075726                       # The number of ROB reads
 system.cpu.rob.rob_writes                   764090765                       # The number of ROB writes
 system.cpu.timesIdled                            1409                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
index d713880d3..283406dc2 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -61,12 +61,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
index 8b4af0675..03f12e59d 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 19:22:24
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:30:09
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic
+Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sav
+Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index bbc7121bd..bdd5452bf 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1042149                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 250372                       # Number of bytes of host memory used
-host_seconds                                   181.04                       # Real time elapsed on the host
-host_tick_rate                              569523249                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3821612                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209488                       # Number of bytes of host memory used
+host_seconds                                    49.37                       # Real time elapsed on the host
+host_tick_rate                             2088466357                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   188670900                       # Number of instructions simulated
 sim_seconds                                  0.103107                       # Number of seconds simulated
@@ -71,6 +71,6 @@ system.cpu.num_int_register_writes          177007633                       # nu
 system.cpu.num_load_insts                    29849485                       # Number of load instructions
 system.cpu.num_mem_refs                      42494120                       # number of memory refs
 system.cpu.num_store_insts                   12644635                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
index 0ecbfede5..c22086808 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -164,12 +164,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
index 9ae12354c..a62fdd8f9 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 19:25:36
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:31:09
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing
+Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sav
+Couldn't unlink  build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 1ea8a3c3d..6b9d8abcc 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 569972                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 258100                       # Number of bytes of host memory used
-host_seconds                                   330.17                       # Real time elapsed on the host
-host_tick_rate                              702907358                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2299830                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 217236                       # Number of bytes of host memory used
+host_seconds                                    81.83                       # Real time elapsed on the host
+host_tick_rate                             2836221203                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   188185929                       # Number of instructions simulated
 sim_seconds                                  0.232077                       # Number of seconds simulated
@@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses             1789                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.332911                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           1363.604315                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.332911                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           41964334                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 54474.007826                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 51474.007826                       # average overall mshr miss latency
@@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses             3051                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.560538                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1147.981155                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.560538                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          189860061                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 37801.376598                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598                       # average overall mshr miss latency
@@ -219,10 +219,10 @@ system.cpu.l2cache.demand_mshr_misses            3453                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.051044                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.000093                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          1672.609981                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1             3.038048                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.051044                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000093                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses              4840                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -264,6 +264,6 @@ system.cpu.num_int_register_writes          177007633                       # nu
 system.cpu.num_load_insts                    29849485                       # Number of load instructions
 system.cpu.num_mem_refs                      42494120                       # number of memory refs
 system.cpu.num_store_insts                   12644635                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
index f4dfd8899..9f7fb86bc 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:13:39
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:20:03
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
 Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
 Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index 5f3549812..df028f09a 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1142521                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 224208                       # Number of bytes of host memory used
-host_seconds                                   169.31                       # Real time elapsed on the host
-host_tick_rate                              571263026                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4299467                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202100                       # Number of bytes of host memory used
+host_seconds                                    44.99                       # Real time elapsed on the host
+host_tick_rate                             2149737482                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193444769                       # Number of instructions simulated
 sim_seconds                                  0.096723                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes          163703467                       # nu
 system.cpu.num_load_insts                    57735092                       # Number of load instructions
 system.cpu.num_mem_refs                      76733959                       # number of memory refs
 system.cpu.num_store_insts                   18998867                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             401                       # Number of system calls
+system.cpu.workload.num_syscalls                  401                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index c8439f7fb..1787724e4 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
index a4abb12dd..748c08434 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:14:19
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:21:39
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
 Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
 Couldn't unlink  build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index f02c69451..9ba399fb8 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 498703                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 231920                       # Number of bytes of host memory used
-host_seconds                                   387.90                       # Real time elapsed on the host
-host_tick_rate                              697549821                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2425845                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209848                       # Number of bytes of host memory used
+host_seconds                                    79.74                       # Real time elapsed on the host
+host_tick_rate                             3393094719                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193444769                       # Number of instructions simulated
 sim_seconds                                  0.270577                       # Number of seconds simulated
@@ -60,8 +60,8 @@ system.cpu.dcache.demand_mshr_misses             1575                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.302050                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           1237.197455                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.302050                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           76711508                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses            12288                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.777135                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1591.571713                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.777135                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          193445549                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 26294.433594                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594                       # average overall mshr miss latency
@@ -182,10 +182,10 @@ system.cpu.l2cache.demand_mshr_misses            5173                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.081736                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          2678.326682                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1             0.000454                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.081736                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses             13864                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -227,6 +227,6 @@ system.cpu.num_int_register_writes          163703466                       # nu
 system.cpu.num_load_insts                    57735092                       # Number of load instructions
 system.cpu.num_mem_refs                      76733959                       # number of memory refs
 system.cpu.num_store_insts                   18998867                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             401                       # Number of system calls
+system.cpu.workload.num_syscalls                  401                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
index 61dc4a8fe..15faea73a 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
index d11a4f41f..09f414a42 100755
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
@@ -5,10 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 18 2011 20:12:06
-M5 started Mar 18 2011 20:12:16
-M5 executing on zizzer
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:39:55
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 4edd15028..84b97ca66 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 118324                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 224536                       # Number of bytes of host memory used
-host_seconds                                  1870.83                       # Real time elapsed on the host
-host_tick_rate                               57079180                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 200454                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 220376                       # Number of bytes of host memory used
+host_seconds                                  1104.31                       # Real time elapsed on the host
+host_tick_rate                               96698720                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   221363017                       # Number of instructions simulated
 sim_seconds                                  0.106785                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect            3071588                       # Nu
 system.cpu.BPredUnit.condPredicted           25075434                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                 25075434                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches               12326943                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           2318001                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    190318905                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.163116                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.516800                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     74095187     38.93%     38.93% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     71171116     37.40%     76.33% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     18278998      9.60%     85.93% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     12739096      6.69%     92.63% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      5868968      3.08%     95.71% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      2789277      1.47%     97.18% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6      1957482      1.03%     98.20% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      1100780      0.58%     98.78% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      2318001      1.22%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    190318905                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                 221363017                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                2162459                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts             220339606                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                  56649590                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   77165306                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts           3071621                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                   12326943                       # Number of branches committed
+system.cpu.commit.bw_lim_events               2318001                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts      221363017                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls            1246                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts       174370767                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples    190318905                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.163116                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.516800                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     74095187     38.93%     38.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     71171116     37.40%     76.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     18278998      9.60%     85.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12739096      6.69%     92.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      5868968      3.08%     95.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2789277      1.47%     97.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1957482      1.03%     98.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1100780      0.58%     98.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2318001      1.22%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    190318905                       # Number of insts commited each cycle
+system.cpu.commit.count                     221363017                       # Number of instructions committed
+system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.int_insts                 220339606                       # Number of committed integer instructions.
+system.cpu.commit.loads                      56649590                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                       77165306                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                   221363017                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             221363017                       # Number of Instructions Simulated
 system.cpu.cpi                               0.964799                       # CPI: Cycles Per Instruction
@@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses             1955                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.341442                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           1398.546932                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.341442                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           71006066                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 27063.622370                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 35228.132992                       # average overall mshr miss latency
@@ -119,12 +119,12 @@ system.cpu.dcache.tagsinuse               1398.546932                       # Cy
 system.cpu.dcache.total_refs                 70998272                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                       10                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       57112679                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts       420105654                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          67048451                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           60385094                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        23161998                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles        5772681                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles              57112679                       # Number of cycles decode is blocked
+system.cpu.decode.DecodedInsts              420105654                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                 67048451                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                  60385094                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles               23161998                       # Number of cycles decode is squashing
+system.cpu.decode.UnblockCycles               5772681                       # Number of cycles decode is unblocking
 system.cpu.fetch.Branches                    25075434                       # Number of branches that fetch encountered
 system.cpu.fetch.CacheLines                  27531173                       # Number of cache lines fetched
 system.cpu.fetch.Cycles                      69569563                       # Number of cycles fetch has run and was not squashing or blocked
@@ -188,8 +188,8 @@ system.cpu.icache.demand_mshr_misses             5384                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.784044                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1605.721886                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.784044                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses           27531173                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 25557.221784                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 22462.481426                       # average overall mshr miss latency
@@ -212,21 +212,13 @@ system.cpu.icache.total_refs                 27524838                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                           89860                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 15858881                       # Number of branches executed
-system.cpu.iew.EXEC:nop                             0                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.303230                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     90240962                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   23196856                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 371845968                       # num instructions consuming a value
-system.cpu.iew.WB:count                     275965139                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.599241                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                 222825226                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.292148                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      277010234                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts              3274274                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                 15858881                       # Number of branches executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_rate                     1.303230                       # Inst execution rate
+system.cpu.iew.exec_refs                     90240962                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                   23196856                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                  536838                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts             104995800                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts               1427                       # Number of dispatched non-speculative instructions
@@ -254,103 +246,93 @@ system.cpu.iew.lsq.thread.0.squashedStores     16601009                       #
 system.cpu.iew.memOrderViolationEvents          35659                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       741660                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        2532614                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                 371845968                       # num instructions consuming a value
+system.cpu.iew.wb_count                     275965139                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.599241                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                 222825226                       # num instructions producing a value
+system.cpu.iew.wb_rate                       1.292148                       # insts written-back per cycle
+system.cpu.iew.wb_sent                      277010234                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                516469209                       # number of integer regfile reads
 system.cpu.int_regfile_writes               283974364                       # number of integer regfile writes
 system.cpu.ipc                               1.036486                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.036486                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass      1200408      0.43%      0.43% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       187079024     66.38%     66.80% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              0      0.00%     66.80% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     66.80% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd       1589764      0.56%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       68461114     24.29%     91.66% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      23516361      8.34%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        281846671                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               2813875                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.009984                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu             68222      2.42%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      2.42% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          2379596     84.57%     86.99% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          366057     13.01%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    213480903                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.320243                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.372505                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      72600816     34.01%     34.01% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      65586069     30.72%     64.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      36613512     17.15%     81.88% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3      20576315      9.64%     91.52% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      12054901      5.65%     97.17% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       3944773      1.85%     99.01% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       1483005      0.69%     99.71% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        508962      0.24%     99.95% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        112550      0.05%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    213480903                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.319688                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass           1200408      0.43%      0.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             187079024     66.38%     66.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1589764      0.56%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             68461114     24.29%     91.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            23516361      8.34%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              281846671                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                 2636909                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads             5233833                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses      2531388                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes            5663526                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                     2813875                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009984                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   68222      2.42%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2379596     84.57%     86.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                366057     13.01%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses              280823229                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads          774810101                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses    273433751                       # Number of integer instruction queue wakeup accesses
@@ -362,6 +344,24 @@ system.cpu.iq.iqSquashedInstsExamined       174039946                       # Nu
 system.cpu.iq.iqSquashedInstsIssued             55814                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved            181                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined    358439815                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples     213480903                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.320243                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.372505                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            72600816     34.01%     34.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            65586069     30.72%     64.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            36613512     17.15%     81.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            20576315      9.64%     91.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12054901      5.65%     97.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3944773      1.85%     99.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1483005      0.69%     99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              508962      0.24%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              112550      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       213480903                       # Number of insts issued each cycle
+system.cpu.iq.rate                           1.319688                       # Inst issue rate
 system.cpu.l2cache.ReadExReq_accesses            1567                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34548.046124                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31351.697630                       # average ReadExReq mshr miss latency
@@ -413,10 +413,10 @@ system.cpu.l2cache.demand_mshr_misses            5223                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.074157                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.000031                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          2429.985932                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1             1.014854                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.074157                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000031                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses              7335                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34369.136512                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31135.171357                       # average overall mshr miss latency
@@ -447,27 +447,27 @@ system.cpu.misc_regfile_writes                    844                       # nu
 system.cpu.numCycles                        213570763                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         18060003                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps      234363409                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents        21564374                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          74887260                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents       16382604                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups     1054491347                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       409882715                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    430914543                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           57380379                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        23161998                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       39968831                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps         196551134                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups     11087102                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups   1043404245                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles        22432                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts         1444                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           83221554                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts         1312                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                18060003                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps             234363409                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents               21564374                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                 74887260                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents              16382604                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenameLookups            1054491347                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts              409882715                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands           430914543                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                  57380379                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles               23161998                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles              39968831                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                196551134                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups          11087102                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups       1043404245                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles          22432                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts               1444                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                  83221554                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts           1312                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                    583734688                       # The number of ROB reads
 system.cpu.rob.rob_writes                   814640460                       # The number of ROB writes
 system.cpu.timesIdled                            1934                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
index 9f05df433..6d11a44d3 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb  8 2011 00:58:34
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:38:23
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 0c54c7d41..80e0c67c1 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1396551                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 231332                       # Number of bytes of host memory used
-host_seconds                                   158.51                       # Real time elapsed on the host
-host_tick_rate                              828940820                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3098099                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209904                       # Number of bytes of host memory used
+host_seconds                                    71.45                       # Real time elapsed on the host
+host_tick_rate                             1838915708                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   221363018                       # Number of instructions simulated
 sim_seconds                                  0.131393                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes          232532006                       # nu
 system.cpu.num_load_insts                    56649590                       # Number of load instructions
 system.cpu.num_mem_refs                      77165306                       # number of memory refs
 system.cpu.num_store_insts                   20515716                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
index 2709fd0f4..040454ea4 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
index 72c0f8f4d..ac8ab44c7 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb  8 2011 00:58:34
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:30:33
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav
+Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
index bbd74268b..b2588e568 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 920852                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 239052                       # Number of bytes of host memory used
-host_seconds                                   240.39                       # Real time elapsed on the host
-host_tick_rate                             1043974445                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1944621                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 217656                       # Number of bytes of host memory used
+host_seconds                                   113.83                       # Real time elapsed on the host
+host_tick_rate                             2204625935                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   221363018                       # Number of instructions simulated
 sim_seconds                                  0.250961                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses             1905                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.332874                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0           1363.451495                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.332874                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses           77197738                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 55780.577428                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961                       # average overall mshr miss latency
@@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses             4694                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.710590                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0           1455.289108                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.710590                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses          173494412                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 39420.856412                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718                       # average overall mshr miss latency
@@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses            4735                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.062810                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.000001                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0          2058.146434                       # Average occupied blocks per context
 system.cpu.l2cache.occ_blocks::1             0.021756                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.062810                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000001                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses              6599                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 52003.273495                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -218,6 +218,6 @@ system.cpu.num_int_register_writes          232532006                       # nu
 system.cpu.num_load_insts                    56649590                       # Number of load instructions
 system.cpu.num_mem_refs                      77165306                       # number of memory refs
 system.cpu.num_store_insts                   20515716                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
index fe4ad698b..62a971a25 100755
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:10:38
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:10:45
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:22:08
+M5 started Apr 19 2011 12:22:10
+M5 executing on maize
 command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
 Global frequency set at 2000000000 ticks per second
 info: No kernel set for full system simulation. Assuming you know what you're doing...
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
index d05ca1e9f..3bd8ad178 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1272725                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 524564                       # Number of bytes of host memory used
-host_seconds                                  1751.49                       # Real time elapsed on the host
-host_tick_rate                                1275361                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4668188                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 504368                       # Number of bytes of host memory used
+host_seconds                                   477.52                       # Real time elapsed on the host
+host_tick_rate                                4677854                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
 sim_insts                                  2229160714                       # Number of instructions simulated
 sim_seconds                                  1.116889                       # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
index 92b040488..c06b2c602 100644
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
@@ -86,6 +86,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +122,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -156,6 +158,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
index fa50fea55..f797f48a3 100755
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 18 2011 15:40:30
-M5 revision Unknown
-M5 started Feb 18 2011 18:52:59
-M5 executing on m55-001.pool
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:24
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index bb298d30a..f36ebb971 100644
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
@@ -1,37 +1,25 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  97475                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 190320                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
-host_tick_rate                              337940129                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 116380                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203032                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                              403915000                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000022                       # Number of seconds simulated
 sim_ticks                                    22294500                       # Number of ticks simulated
-system.cpu.AGEN-Unit.agens                       2186                       # Number of Address Generations
-system.cpu.Branch-Predictor.BTBHitPct       23.015873                       # BTB Hit Percentage
-system.cpu.Branch-Predictor.BTBHits                87                       # Number of BTB hits
-system.cpu.Branch-Predictor.BTBLookups            378                       # Number of BTB lookups
-system.cpu.Branch-Predictor.RASInCorrect            0                       # Number of incorrect RAS predictions.
-system.cpu.Branch-Predictor.condIncorrect          542                       # Number of conditional branches incorrect
-system.cpu.Branch-Predictor.condPredicted          995                       # Number of conditional branches predicted
-system.cpu.Branch-Predictor.lookups              1423                       # Number of BP lookups
-system.cpu.Branch-Predictor.predictedNotTaken         1183                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken          240                       # Number of Branches Predicted As Taken (True).
-system.cpu.Branch-Predictor.usedRAS               125                       # Number of times the RAS was used to get a target.
-system.cpu.Execution-Unit.executions             4596                       # Number of Instructions Executed.
-system.cpu.Execution-Unit.mispredictPct     51.569933                       # Percentage of Incorrect Branches Predicts
-system.cpu.Execution-Unit.mispredicted            542                       # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predicted               509                       # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predictedNotTakenIncorrect          537                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.Execution-Unit.predictedTakenIncorrect            5                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.Mult-Div-Unit.divides                    0                       # Number of Divide Operations Executed
-system.cpu.Mult-Div-Unit.multiplies                 1                       # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses        10530                       # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads          5947                       # Number of Reads from Register File
-system.cpu.RegFile-Manager.regFileWrites         4583                       # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards           2845                       # Number of Registers Read Through Forwarding Logic
 system.cpu.activity                         16.075353                       # Percentage of cycles cpu is active
+system.cpu.agen_unit.agens                       2186                       # Number of Address Generations
+system.cpu.branch_predictor.BTBHitPct       23.015873                       # BTB Hit Percentage
+system.cpu.branch_predictor.BTBHits                87                       # Number of BTB hits
+system.cpu.branch_predictor.BTBLookups            378                       # Number of BTB lookups
+system.cpu.branch_predictor.RASInCorrect            0                       # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.condIncorrect          542                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.condPredicted          995                       # Number of conditional branches predicted
+system.cpu.branch_predictor.lookups              1423                       # Number of BP lookups
+system.cpu.branch_predictor.predictedNotTaken         1183                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.branch_predictor.predictedTaken          240                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.usedRAS               125                       # Number of times the RAS was used to get a target.
 system.cpu.comBranches                           1051                       # Number of Branches instructions committed
 system.cpu.comFloats                                2                       # Number of Floating Point instructions committed
 system.cpu.comInts                               3265                       # Number of Integer instructions committed
@@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses              168                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.024898                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            101.981030                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.024898                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               2050                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 56663.223140                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 53690.476190                       # average overall mshr miss latency
@@ -127,6 +115,12 @@ system.cpu.dtb.write_accesses                     868                       # DT
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
+system.cpu.execution_unit.executions             4596                       # Number of Instructions Executed.
+system.cpu.execution_unit.mispredictPct     51.569933                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.mispredicted            542                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted               509                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predictedNotTakenIncorrect          537                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.predictedTakenIncorrect            5                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.icache.ReadReq_accesses                955                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 55322.580645                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 53094.684385                       # average ReadReq mshr miss latency
@@ -160,8 +154,8 @@ system.cpu.icache.demand_mshr_misses              301                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.066877                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            136.964505                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.066877                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses                955                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55322.580645                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 53094.684385                       # average overall mshr miss latency
@@ -243,8 +237,8 @@ system.cpu.l2cache.demand_mshr_misses             468                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.005888                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           192.950109                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.005888                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               469                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 52243.589744                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 40087.606838                       # average overall mshr miss latency
@@ -266,31 +260,37 @@ system.cpu.l2cache.tagsinuse               192.950109                       # Cy
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
+system.cpu.mult_div_unit.multiplies                 1                       # Number of Multipy Operations Executed
 system.cpu.numCycles                            44590                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.regfile_manager.regFileAccesses        10530                       # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.regfile_manager.regFileReads          5947                       # Number of Reads from Register File
+system.cpu.regfile_manager.regFileWrites         4583                       # Number of Writes to Register File
+system.cpu.regfile_manager.regForwards           2845                       # Number of Registers Read Through Forwarding Logic
 system.cpu.runCycles                             7168                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles                   39847                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-0.runCycles                     4743                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization              10.636914                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles                   40758                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles                     3832                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization               8.593855                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles                   40488                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-2.runCycles                     4102                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization               9.199372                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles                   43180                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-3.runCycles                     1410                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization               3.162144                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles                   40181                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-4.runCycles                     4409                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization               9.887867                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage0.idleCycles                    39847                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                      4743                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               10.636914                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    40758                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                      3832                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization                8.593855                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    40488                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                      4102                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization                9.199372                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    43180                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                      1410                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization                3.162144                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    40181                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      4409                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization                9.887867                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.threadCycles                         11319                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.timesIdled                             425                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index 694ecbd33..08baf7c22 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
index 99080254c..fb1ddd9ef 100755
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 21:44:37
-M5 started Mar 17 2011 21:44:43
-M5 executing on zizzer
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:00:29
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 614787416..6483a471a 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  83889                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 205772                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
-host_tick_rate                              161742329                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 150919                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203704                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
+host_tick_rate                              290889761                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6386                       # Number of instructions simulated
 sim_seconds                                  0.000012                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect                443                       # Nu
 system.cpu.BPredUnit.condPredicted               1297                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                     2180                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                      306                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches                   1051                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events               127                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples        12090                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.529611                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.331978                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0         9222     76.28%     76.28% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1         1613     13.34%     89.62% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2          453      3.75%     93.37% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3          264      2.18%     95.55% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4          157      1.30%     96.85% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5          121      1.00%     97.85% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6           88      0.73%     98.58% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7           45      0.37%     98.95% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8          127      1.05%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total        12090                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                      6403                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                     10                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls              127                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts                  6321                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                      1185                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                       2050                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts               369                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                       1051                       # Number of branches committed
+system.cpu.commit.bw_lim_events                   127                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts           6403                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts            4249                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples        12090                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.529611                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.331978                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         9222     76.28%     76.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1613     13.34%     89.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          453      3.75%     93.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          264      2.18%     95.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          157      1.30%     96.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          121      1.00%     97.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           88      0.73%     98.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           45      0.37%     98.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          127      1.05%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12090                       # Number of insts commited each cycle
+system.cpu.commit.count                          6403                       # Number of instructions committed
+system.cpu.commit.fp_insts                         10                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls                  127                       # Number of function calls committed.
+system.cpu.commit.int_insts                      6321                       # Number of committed integer instructions.
+system.cpu.commit.loads                          1185                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                           2050                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                        6386                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  6386                       # Number of Instructions Simulated
 system.cpu.cpi                               3.870341                       # CPI: Cycles Per Instruction
@@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses              174                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.026841                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            109.940770                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.026841                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               2570                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 35355.731225                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 36083.333333                       # average overall mshr miss latency
@@ -119,15 +119,15 @@ system.cpu.dcache.tagsinuse                109.940770                       # Cy
 system.cpu.dcache.total_refs                     2064                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles           1035                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred             75                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved           181                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts           12021                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles              8780                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles               2228                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles             825                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts            209                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles             47                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles                  1035                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                    75                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved                  181                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts                  12021                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                     8780                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                      2228                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                    825                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                   209                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles                    47                       # Number of cycles decode is unblocking
 system.cpu.dtb.data_accesses                     2822                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                         2761                       # DTB hits
@@ -207,8 +207,8 @@ system.cpu.icache.demand_mshr_misses              307                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.076986                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            157.666490                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.076986                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses               1711                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 35919.512195                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622                       # average overall mshr miss latency
@@ -231,21 +231,13 @@ system.cpu.icache.total_refs                     1301                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                           11801                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                     1424                       # Number of branches executed
-system.cpu.iew.EXEC:nop                            82                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.357542                       # Inst execution rate
-system.cpu.iew.EXEC:refs                         2832                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                       1038                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                      5952                       # num instructions consuming a value
-system.cpu.iew.WB:count                          8559                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.744120                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                      4429                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.346294                       # insts written-back per cycle
-system.cpu.iew.WB:sent                           8658                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts                  429                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                     1424                       # Number of branches executed
+system.cpu.iew.exec_nop                            82                       # number of nop insts executed
+system.cpu.iew.exec_rate                     0.357542                       # Inst execution rate
+system.cpu.iew.exec_refs                         2832                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                       1038                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                      67                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts                  2144                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                 25                       # Number of dispatched non-speculative instructions
@@ -273,103 +265,93 @@ system.cpu.iew.lsq.thread.0.squashedStores          330                       #
 system.cpu.iew.memOrderViolationEvents             16                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          304                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            125                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                      5952                       # num instructions consuming a value
+system.cpu.iew.wb_count                          8559                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.744120                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                      4429                       # num instructions producing a value
+system.cpu.iew.wb_rate                       0.346294                       # insts written-back per cycle
+system.cpu.iew.wb_sent                           8658                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                    11291                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    6385                       # number of integer regfile writes
 system.cpu.ipc                               0.258375                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.258375                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu            6174     67.79%     67.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              1      0.01%     67.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             2      0.02%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     67.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead           1875     20.59%     88.43% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite          1054     11.57%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total             9108                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                    88                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.009662                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu                 1      1.14%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      1.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead               52     59.09%     60.23% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite              35     39.77%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples        12915                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.705226                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.305176                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0          8840     68.45%     68.45% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1          1652     12.79%     81.24% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2          1039      8.04%     89.28% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3           684      5.30%     94.58% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4           367      2.84%     97.42% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5           198      1.53%     98.95% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6            88      0.68%     99.64% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7            36      0.28%     99.91% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8            11      0.09%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total        12915                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.368506                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  6174     67.79%     67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.84% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1875     20.59%     88.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1054     11.57%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total                   9108                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                      11                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                  21                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                 10                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                          88                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009662                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       1      1.14%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     52     59.09%     60.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    35     39.77%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses                   9183                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads              31223                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses         8549                       # Number of integer instruction queue wakeup accesses
@@ -381,6 +363,24 @@ system.cpu.iq.iqSquashedInstsExamined            3797                       # Nu
 system.cpu.iq.iqSquashedInstsIssued                25                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved              8                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined         2286                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples         12915                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.705226                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.305176                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                8840     68.45%     68.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1652     12.79%     81.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1039      8.04%     89.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 684      5.30%     94.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 367      2.84%     97.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 198      1.53%     98.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  88      0.68%     99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  36      0.28%     99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  11      0.09%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           12915                       # Number of insts issued each cycle
+system.cpu.iq.rate                           0.368506                       # Inst issue rate
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
@@ -438,8 +438,8 @@ system.cpu.l2cache.demand_mshr_misses             480                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.006698                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           219.485914                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.006698                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               481                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34421.875000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31252.083333                       # average overall mshr miss latency
@@ -470,27 +470,27 @@ system.cpu.misc_regfile_writes                      1                       # nu
 system.cpu.numCycles                            24716                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles              337                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps           4583                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents               8                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles              8928                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents            260                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups          14615                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts           11616                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands         8669                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles               2118                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles             825                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles            301                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps              4086                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups           17                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups        14598                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles          406                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts           28                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts                754                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts           22                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                     337                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps                  4583                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                      8                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                     8928                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents                   260                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenameLookups                 14615                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts                  11616                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands                8669                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                      2118                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                    825                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles                   301                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                     4086                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups                17                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups            14598                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles            406                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts                 28                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                       754                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts             22                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                        22264                       # The number of ROB reads
 system.cpu.rob.rob_writes                       22135                       # The number of ROB writes
 system.cpu.timesIdled                             240                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
index b6cabe98f..e68d877ae 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:39
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:03:52
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index 29c354685..16e0bb854 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 474100                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215244                       # Number of bytes of host memory used
+host_inst_rate                                 863821                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195076                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              233713954                       # Simulator tick rate (ticks/s)
+host_tick_rate                              424966568                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes               4581                       # nu
 system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_mem_refs                          2060                       # number of memory refs
 system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
index c905c3ec3..97adc30bc 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -63,7 +63,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -201,6 +201,7 @@ deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 50b357793..61a1f65c1 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/08/2011 17:31:55
+Real time: Apr/19/2011 12:12:41
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.51
-Virtual_time_in_minutes: 0.0085
-Virtual_time_in_hours:   0.000141667
-Virtual_time_in_days:    5.90278e-06
+Virtual_time_in_seconds: 0.22
+Virtual_time_in_minutes: 0.00366667
+Virtual_time_in_hours:   6.11111e-05
+Virtual_time_in_days:    2.5463e-06
 
 Ruby_current_time: 275313
 Ruby_start_time: 0
 Ruby_cycles: 275313
 
-mbytes_resident: 37.0469
-mbytes_total: 210.465
-resident_ratio: 0.176098
+mbytes_resident: 39.0156
+mbytes_total: 208.391
+resident_ratio: 0.187242
 
 ruby_cycles_executed: [ 275314 ]
 
@@ -71,9 +71,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_NULL: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -85,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 imcomplete_dir_Times: 0
-miss_latency_IFETCH_NULL: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD_NULL: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_NULL: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_NULL: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10681
+page_reclaims: 10280
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 64
 
 Network Stats
 -------------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
index 8e7f8bf86..87aa40602 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 17:31:51
-M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip
-M5 started Feb  8 2011 17:31:55
-M5 executing on SC2B0617
+M5 compiled Apr 19 2011 12:12:36
+M5 started Apr 19 2011 12:12:40
+M5 executing on maize
 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
index d0f6b1167..752b7fee0 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  30108                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215520                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
-host_tick_rate                                1293296                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  53768                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213396                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
+host_tick_rate                                2308748                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000275                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes               4581                       # nu
 system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_mem_refs                          2060                       # number of memory refs
 system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index cb765942a..f21fa2c0d 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -63,7 +63,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -197,6 +197,7 @@ deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 9154f09df..4ab7d1237 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/08/2011 17:41:43
+Real time: Apr/19/2011 12:14:53
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.52
-Virtual_time_in_minutes: 0.00866667
-Virtual_time_in_hours:   0.000144444
-Virtual_time_in_days:    6.01852e-06
+Virtual_time_in_seconds: 0.24
+Virtual_time_in_minutes: 0.004
+Virtual_time_in_hours:   6.66667e-05
+Virtual_time_in_days:    2.77778e-06
 
 Ruby_current_time: 223854
 Ruby_start_time: 0
 Ruby_cycles: 223854
 
-mbytes_resident: 37.1562
-mbytes_total: 210.609
-resident_ratio: 0.176478
+mbytes_resident: 39.1172
+mbytes_total: 208.504
+resident_ratio: 0.187628
 
 ruby_cycles_executed: [ 223855 ]
 
@@ -71,9 +71,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 276 count: 8464 average: 25.4478 | standard deviation: 56.39 | 0 7102 0 0 0 0 0 0 0 188 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 197 238 187 165 13 4 20 3 7 5 4 3 3 1 0 1 1 1 0 0 1 0 1 0 0 0 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_NULL: [binsize: 2 max: 276 count: 8464 average: 25.4478 | standard deviation: 56.39 | 0 7102 0 0 0 0 0 0 0 188 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 197 238 187 165 13 4 20 3 7 5 4 3 3 1 0 1 1 1 0 0 1 0 1 0 0 0 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -85,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 imcomplete_dir_Times: 0
-miss_latency_IFETCH_NULL: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD_NULL: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_NULL: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_NULL: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10696
+page_reclaims: 10307
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 64
 
 Network Stats
 -------------
@@ -411,6 +411,7 @@ Writeback_Ack [1098 ] 1098
 Writeback_Nack [0 ] 0
 Unblock [0 ] 0
 Exclusive_Unblock [1362 ] 1362
+DmaAck [0 ] 0
 L2_Replacement [1098 ] 1098
 
  - Transitions -
@@ -1160,6 +1161,76 @@ ILSI  All_Acks [0 ] 0
 ILSI  Writeback_Ack [0 ] 0
 ILSI  L2_Replacement [0 ] 0
 
+ILOSD  L1_GETS [0 ] 0
+ILOSD  L1_GETX [0 ] 0
+ILOSD  L1_PUTO [0 ] 0
+ILOSD  L1_PUTX [0 ] 0
+ILOSD  L1_PUTS_only [0 ] 0
+ILOSD  L1_PUTS [0 ] 0
+ILOSD  Fwd_GETX [0 ] 0
+ILOSD  Fwd_GETS [0 ] 0
+ILOSD  Fwd_DMA [0 ] 0
+ILOSD  Own_GETX [0 ] 0
+ILOSD  Inv [0 ] 0
+ILOSD  DmaAck [0 ] 0
+ILOSD  L2_Replacement [0 ] 0
+
+ILOSXD  L1_GETS [0 ] 0
+ILOSXD  L1_GETX [0 ] 0
+ILOSXD  L1_PUTO [0 ] 0
+ILOSXD  L1_PUTX [0 ] 0
+ILOSXD  L1_PUTS_only [0 ] 0
+ILOSXD  L1_PUTS [0 ] 0
+ILOSXD  Fwd_GETX [0 ] 0
+ILOSXD  Fwd_GETS [0 ] 0
+ILOSXD  Fwd_DMA [0 ] 0
+ILOSXD  Own_GETX [0 ] 0
+ILOSXD  Inv [0 ] 0
+ILOSXD  DmaAck [0 ] 0
+ILOSXD  L2_Replacement [0 ] 0
+
+ILOD  L1_GETS [0 ] 0
+ILOD  L1_GETX [0 ] 0
+ILOD  L1_PUTO [0 ] 0
+ILOD  L1_PUTX [0 ] 0
+ILOD  L1_PUTS_only [0 ] 0
+ILOD  L1_PUTS [0 ] 0
+ILOD  Fwd_GETX [0 ] 0
+ILOD  Fwd_GETS [0 ] 0
+ILOD  Fwd_DMA [0 ] 0
+ILOD  Own_GETX [0 ] 0
+ILOD  Inv [0 ] 0
+ILOD  DmaAck [0 ] 0
+ILOD  L2_Replacement [0 ] 0
+
+ILXD  L1_GETS [0 ] 0
+ILXD  L1_GETX [0 ] 0
+ILXD  L1_PUTO [0 ] 0
+ILXD  L1_PUTX [0 ] 0
+ILXD  L1_PUTS_only [0 ] 0
+ILXD  L1_PUTS [0 ] 0
+ILXD  Fwd_GETX [0 ] 0
+ILXD  Fwd_GETS [0 ] 0
+ILXD  Fwd_DMA [0 ] 0
+ILXD  Own_GETX [0 ] 0
+ILXD  Inv [0 ] 0
+ILXD  DmaAck [0 ] 0
+ILXD  L2_Replacement [0 ] 0
+
+ILOXD  L1_GETS [0 ] 0
+ILOXD  L1_GETX [0 ] 0
+ILOXD  L1_PUTO [0 ] 0
+ILOXD  L1_PUTX [0 ] 0
+ILOXD  L1_PUTS_only [0 ] 0
+ILOXD  L1_PUTS [0 ] 0
+ILOXD  Fwd_GETX [0 ] 0
+ILOXD  Fwd_GETS [0 ] 0
+ILOXD  Fwd_DMA [0 ] 0
+ILOXD  Own_GETX [0 ] 0
+ILOXD  Inv [0 ] 0
+ILOXD  DmaAck [0 ] 0
+ILOXD  L2_Replacement [0 ] 0
+
 Memory controller: system.dir_cntrl0.memBuffer:
   memory_total_requests: 1308
   memory_reads: 1114
@@ -1196,6 +1267,7 @@ Memory_Data [1114 ] 1114
 Memory_Ack [194 ] 194
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
+DMA_ACK [0 ] 0
 Data [0 ] 0
 
  - Transitions -
@@ -1376,4 +1448,22 @@ OI_D  PUTO [0 ] 0
 OI_D  PUTO_SHARERS [0 ] 0
 OI_D  DMA_READ [0 ] 0
 OI_D  DMA_WRITE [0 ] 0
-OI_D  Data
\ No newline at end of file
+OI_D  Data [0 ] 0
+
+OD  GETX [0 ] 0
+OD  GETS [0 ] 0
+OD  PUTX [0 ] 0
+OD  PUTO [0 ] 0
+OD  PUTO_SHARERS [0 ] 0
+OD  DMA_READ [0 ] 0
+OD  DMA_WRITE [0 ] 0
+OD  DMA_ACK [0 ] 0
+
+MD  GETX [0 ] 0
+MD  GETS [0 ] 0
+MD  PUTX [0 ] 0
+MD  PUTO [0 ] 0
+MD  PUTO_SHARERS [0 ] 0
+MD  DMA_READ [0 ] 0
+MD  DMA_WRITE [0 ] 0
+MD  DMA_ACK
\ No newline at end of file
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index c4db03463..e906774aa 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 17:41:34
-M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
-M5 started Feb  8 2011 17:41:42
-M5 executing on SC2B0617
+M5 compiled Apr 19 2011 12:14:48
+M5 started Apr 19 2011 12:14:53
+M5 executing on maize
 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index e92c6159b..03c5a78bf 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  26297                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215668                       # Number of bytes of host memory used
-host_seconds                                     0.24                       # Real time elapsed on the host
-host_tick_rate                                 918519                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  44214                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213512                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
+host_tick_rate                                1544058                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000224                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes               4581                       # nu
 system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_mem_refs                          2060                       # number of memory refs
 system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index 2f2bf304c..f1fd9e728 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -63,7 +63,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index 0fc931dc4..6e05a4449 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Mar/26/2011 22:00:44
+Real time: Apr/19/2011 12:17:16
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.23
-Virtual_time_in_minutes: 0.00383333
-Virtual_time_in_hours:   6.38889e-05
-Virtual_time_in_days:    2.66204e-06
+Virtual_time_in_seconds: 0.18
+Virtual_time_in_minutes: 0.003
+Virtual_time_in_hours:   5e-05
+Virtual_time_in_days:    2.08333e-06
 
 Ruby_current_time: 217591
 Ruby_start_time: 0
 Ruby_cycles: 217591
 
-mbytes_resident: 38.1094
-mbytes_total: 199.473
-resident_ratio: 0.19107
+mbytes_resident: 38.9258
+mbytes_total: 208.391
+resident_ratio: 0.186811
 
 ruby_cycles_executed: [ 217592 ]
 
@@ -127,7 +127,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10053
+page_reclaims: 10260
 page_faults: 0
 swaps: 0
 block_inputs: 0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
index 97520046b..b93a9ba34 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 26 2011 14:06:20
-M5 started Mar 26 2011 22:00:43
-M5 executing on phenom
+M5 compiled Apr 19 2011 12:17:10
+M5 started Apr 19 2011 12:17:16
+M5 executing on maize
 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index fd6cdb90f..a40ed048f 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  21360                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204264                       # Number of bytes of host memory used
-host_seconds                                     0.30                       # Real time elapsed on the host
-host_tick_rate                                 725351                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  82829                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213396                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
+host_tick_rate                                2809629                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000218                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes               4581                       # nu
 system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_mem_refs                          2060                       # number of memory refs
 system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index b25662a67..2dfe81c60 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -63,7 +63,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -184,6 +184,7 @@ deadlock_threshold=500000
 icache=system.ruby.cpu_ruby_ports.icache
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
index afe766dd7..e78377434 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/08/2011 17:57:03
+Real time: Apr/19/2011 12:10:00
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.42
-Virtual_time_in_minutes: 0.007
-Virtual_time_in_hours:   0.000116667
-Virtual_time_in_days:    4.86111e-06
+Virtual_time_in_seconds: 0.18
+Virtual_time_in_minutes: 0.003
+Virtual_time_in_hours:   5e-05
+Virtual_time_in_days:    2.08333e-06
 
 Ruby_current_time: 208400
 Ruby_start_time: 0
 Ruby_cycles: 208400
 
-mbytes_resident: 36.6641
-mbytes_total: 209.902
-resident_ratio: 0.174709
+mbytes_resident: 38.6719
+mbytes_total: 208.031
+resident_ratio: 0.185913
 
 ruby_cycles_executed: [ 208401 ]
 
@@ -70,9 +70,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.6219 | standard deviation: 54.4451 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8564 | standard deviation: 43.57 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD: [binsize: 2 max: 327 count: 1185 average: 57.3924 | standard deviation: 73.6654 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9399 | standard deviation: 73.2706 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8564 | standard deviation: 43.57 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average:     2 | standard deviation: 0 | 0 0 7102 ]
 miss_latency_L2Cache: [binsize: 1 max: 13 count: 203 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 203 ]
 miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.975 | standard deviation: 26.6537 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
@@ -86,15 +86,15 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average:
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average:   158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
 imcomplete_dir_Times: 1158
-miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average:     2 | standard deviation: 0 | 0 0 5768 ]
-miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 65 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
-miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.738 | standard deviation: 5.93543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average:     2 | standard deviation: 0 | 0 0 660 ]
 miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 105 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 105 ]
 miss_latency_LD_Directory: [binsize: 2 max: 327 count: 420 average: 155.536 | standard deviation: 18.768 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average:     2 | standard deviation: 0 | 0 0 674 ]
 miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 33 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 33 ]
 miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.038 | standard deviation: 59.9794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average:     2 | standard deviation: 0 | 0 0 5768 ]
+miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 65 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.738 | standard deviation: 5.93543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -126,11 +126,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10608
+page_reclaims: 10195
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 64
 
 Network Stats
 -------------
@@ -190,7 +190,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.icache
 
   system.ruby.cpu_ruby_ports.icache_request_type_IFETCH:   100%
 
-  system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode:   646    100%
+  system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor:   646    100%
 
 Cache Stats: system.ruby.cpu_ruby_ports.dcache
   system.ruby.cpu_ruby_ports.dcache_total_misses: 716
@@ -202,7 +202,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache
   system.ruby.cpu_ruby_ports.dcache_request_type_LD:   73.324%
   system.ruby.cpu_ruby_ports.dcache_request_type_ST:   26.676%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   716    100%
+  system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor:   716    100%
 
 Cache Stats: system.l1_cntrl0.L2cacheMemory
   system.l1_cntrl0.L2cacheMemory_total_misses: 1362
@@ -215,7 +215,7 @@ Cache Stats: system.l1_cntrl0.L2cacheMemory
   system.l1_cntrl0.L2cacheMemory_request_type_ST:   14.0235%
   system.l1_cntrl0.L2cacheMemory_request_type_IFETCH:   47.4302%
 
-  system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   1362    100%
+  system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   1362    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -242,6 +242,8 @@ Writeback_Ack [1143 ] 1143
 Writeback_Nack [0 ] 0
 All_acks [0 ] 0
 All_acks_no_sharers [1159 ] 1159
+Flush_line [0 ] 0
+Block_Ack [0 ] 0
 
  - Transitions -
 I  Load [420 ] 420
@@ -256,6 +258,7 @@ I  Other_GETS [0 ] 0
 I  Other_GETS_No_Mig [0 ] 0
 I  NC_DMA_GETS [0 ] 0
 I  Invalidate [0 ] 0
+I  Flush_line [0 ] 0
 
 S  Load [0 ] 0
 S  Ifetch [0 ] 0
@@ -269,6 +272,7 @@ S  Other_GETS [0 ] 0
 S  Other_GETS_No_Mig [0 ] 0
 S  NC_DMA_GETS [0 ] 0
 S  Invalidate [0 ] 0
+S  Flush_line [0 ] 0
 
 O  Load [0 ] 0
 O  Ifetch [0 ] 0
@@ -283,6 +287,7 @@ O  Merged_GETS [0 ] 0
 O  Other_GETS_No_Mig [0 ] 0
 O  NC_DMA_GETS [0 ] 0
 O  Invalidate [0 ] 0
+O  Flush_line [0 ] 0
 
 M  Load [368 ] 368
 M  Ifetch [5833 ] 5833
@@ -297,6 +302,7 @@ M  Merged_GETS [0 ] 0
 M  Other_GETS_No_Mig [0 ] 0
 M  NC_DMA_GETS [0 ] 0
 M  Invalidate [0 ] 0
+M  Flush_line [0 ] 0
 
 MM  Load [397 ] 397
 MM  Ifetch [0 ] 0
@@ -311,6 +317,7 @@ MM  Merged_GETS [0 ] 0
 MM  Other_GETS_No_Mig [0 ] 0
 MM  NC_DMA_GETS [0 ] 0
 MM  Invalidate [0 ] 0
+MM  Flush_line [0 ] 0
 
 IM  Load [0 ] 0
 IM  Ifetch [0 ] 0
@@ -325,6 +332,7 @@ IM  Invalidate [0 ] 0
 IM  Ack [0 ] 0
 IM  Data [0 ] 0
 IM  Exclusive_Data [158 ] 158
+IM  Flush_line [0 ] 0
 
 SM  Load [0 ] 0
 SM  Ifetch [0 ] 0
@@ -339,6 +347,7 @@ SM  Invalidate [0 ] 0
 SM  Ack [0 ] 0
 SM  Data [0 ] 0
 SM  Exclusive_Data [0 ] 0
+SM  Flush_line [0 ] 0
 
 OM  Load [0 ] 0
 OM  Ifetch [0 ] 0
@@ -354,6 +363,7 @@ OM  Invalidate [0 ] 0
 OM  Ack [0 ] 0
 OM  All_acks [0 ] 0
 OM  All_acks_no_sharers [0 ] 0
+OM  Flush_line [0 ] 0
 
 ISM  Load [0 ] 0
 ISM  Ifetch [0 ] 0
@@ -362,6 +372,7 @@ ISM  L2_Replacement [0 ] 0
 ISM  L1_to_L2 [0 ] 0
 ISM  Ack [0 ] 0
 ISM  All_acks_no_sharers [0 ] 0
+ISM  Flush_line [0 ] 0
 
 M_W  Load [0 ] 0
 M_W  Ifetch [0 ] 0
@@ -370,6 +381,7 @@ M_W  L2_Replacement [0 ] 0
 M_W  L1_to_L2 [0 ] 0
 M_W  Ack [0 ] 0
 M_W  All_acks_no_sharers [1001 ] 1001
+M_W  Flush_line [0 ] 0
 
 MM_W  Load [0 ] 0
 MM_W  Ifetch [0 ] 0
@@ -378,6 +390,7 @@ MM_W  L2_Replacement [0 ] 0
 MM_W  L1_to_L2 [0 ] 0
 MM_W  Ack [0 ] 0
 MM_W  All_acks_no_sharers [158 ] 158
+MM_W  Flush_line [0 ] 0
 
 IS  Load [0 ] 0
 IS  Ifetch [0 ] 0
@@ -394,6 +407,7 @@ IS  Shared_Ack [0 ] 0
 IS  Data [0 ] 0
 IS  Shared_Data [0 ] 0
 IS  Exclusive_Data [1001 ] 1001
+IS  Flush_line [0 ] 0
 
 SS  Load [0 ] 0
 SS  Ifetch [0 ] 0
@@ -404,6 +418,7 @@ SS  Ack [0 ] 0
 SS  Shared_Ack [0 ] 0
 SS  All_acks [0 ] 0
 SS  All_acks_no_sharers [0 ] 0
+SS  Flush_line [0 ] 0
 
 OI  Load [0 ] 0
 OI  Ifetch [0 ] 0
@@ -417,6 +432,7 @@ OI  Other_GETS_No_Mig [0 ] 0
 OI  NC_DMA_GETS [0 ] 0
 OI  Invalidate [0 ] 0
 OI  Writeback_Ack [0 ] 0
+OI  Flush_line [0 ] 0
 
 MI  Load [8 ] 8
 MI  Ifetch [11 ] 11
@@ -430,6 +446,7 @@ MI  Other_GETS_No_Mig [0 ] 0
 MI  NC_DMA_GETS [0 ] 0
 MI  Invalidate [0 ] 0
 MI  Writeback_Ack [1143 ] 1143
+MI  Flush_line [0 ] 0
 
 II  Load [0 ] 0
 II  Ifetch [0 ] 0
@@ -443,6 +460,7 @@ II  NC_DMA_GETS [0 ] 0
 II  Invalidate [0 ] 0
 II  Writeback_Ack [0 ] 0
 II  Writeback_Nack [0 ] 0
+II  Flush_line [0 ] 0
 
 IT  Load [0 ] 0
 IT  Ifetch [0 ] 0
@@ -456,6 +474,7 @@ IT  Merged_GETS [0 ] 0
 IT  Other_GETS_No_Mig [0 ] 0
 IT  NC_DMA_GETS [0 ] 0
 IT  Invalidate [0 ] 0
+IT  Flush_line [0 ] 0
 
 ST  Load [0 ] 0
 ST  Ifetch [0 ] 0
@@ -469,6 +488,7 @@ ST  Merged_GETS [0 ] 0
 ST  Other_GETS_No_Mig [0 ] 0
 ST  NC_DMA_GETS [0 ] 0
 ST  Invalidate [0 ] 0
+ST  Flush_line [0 ] 0
 
 OT  Load [0 ] 0
 OT  Ifetch [0 ] 0
@@ -482,6 +502,7 @@ OT  Merged_GETS [0 ] 0
 OT  Other_GETS_No_Mig [0 ] 0
 OT  NC_DMA_GETS [0 ] 0
 OT  Invalidate [0 ] 0
+OT  Flush_line [0 ] 0
 
 MT  Load [0 ] 0
 MT  Ifetch [0 ] 0
@@ -495,6 +516,7 @@ MT  Merged_GETS [0 ] 0
 MT  Other_GETS_No_Mig [0 ] 0
 MT  NC_DMA_GETS [0 ] 0
 MT  Invalidate [0 ] 0
+MT  Flush_line [0 ] 0
 
 MMT  Load [0 ] 0
 MMT  Ifetch [0 ] 0
@@ -508,6 +530,94 @@ MMT  Merged_GETS [0 ] 0
 MMT  Other_GETS_No_Mig [0 ] 0
 MMT  NC_DMA_GETS [0 ] 0
 MMT  Invalidate [0 ] 0
+MMT  Flush_line [0 ] 0
+
+MI_F  Load [0 ] 0
+MI_F  Ifetch [0 ] 0
+MI_F  Store [0 ] 0
+MI_F  L1_to_L2 [0 ] 0
+MI_F  Writeback_Ack [0 ] 0
+MI_F  Flush_line [0 ] 0
+
+MM_F  Load [0 ] 0
+MM_F  Ifetch [0 ] 0
+MM_F  Store [0 ] 0
+MM_F  L1_to_L2 [0 ] 0
+MM_F  Other_GETX [0 ] 0
+MM_F  Other_GETS [0 ] 0
+MM_F  Merged_GETS [0 ] 0
+MM_F  Other_GETS_No_Mig [0 ] 0
+MM_F  NC_DMA_GETS [0 ] 0
+MM_F  Invalidate [0 ] 0
+MM_F  Ack [0 ] 0
+MM_F  All_acks [0 ] 0
+MM_F  All_acks_no_sharers [0 ] 0
+MM_F  Flush_line [0 ] 0
+MM_F  Block_Ack [0 ] 0
+
+IM_F  Load [0 ] 0
+IM_F  Ifetch [0 ] 0
+IM_F  Store [0 ] 0
+IM_F  L2_Replacement [0 ] 0
+IM_F  L1_to_L2 [0 ] 0
+IM_F  Other_GETX [0 ] 0
+IM_F  Other_GETS [0 ] 0
+IM_F  Other_GETS_No_Mig [0 ] 0
+IM_F  NC_DMA_GETS [0 ] 0
+IM_F  Invalidate [0 ] 0
+IM_F  Ack [0 ] 0
+IM_F  Data [0 ] 0
+IM_F  Exclusive_Data [0 ] 0
+IM_F  Flush_line [0 ] 0
+
+ISM_F  Load [0 ] 0
+ISM_F  Ifetch [0 ] 0
+ISM_F  Store [0 ] 0
+ISM_F  L2_Replacement [0 ] 0
+ISM_F  L1_to_L2 [0 ] 0
+ISM_F  Ack [0 ] 0
+ISM_F  All_acks_no_sharers [0 ] 0
+ISM_F  Flush_line [0 ] 0
+
+SM_F  Load [0 ] 0
+SM_F  Ifetch [0 ] 0
+SM_F  Store [0 ] 0
+SM_F  L2_Replacement [0 ] 0
+SM_F  L1_to_L2 [0 ] 0
+SM_F  Other_GETX [0 ] 0
+SM_F  Other_GETS [0 ] 0
+SM_F  Other_GETS_No_Mig [0 ] 0
+SM_F  NC_DMA_GETS [0 ] 0
+SM_F  Invalidate [0 ] 0
+SM_F  Ack [0 ] 0
+SM_F  Data [0 ] 0
+SM_F  Exclusive_Data [0 ] 0
+SM_F  Flush_line [0 ] 0
+
+OM_F  Load [0 ] 0
+OM_F  Ifetch [0 ] 0
+OM_F  Store [0 ] 0
+OM_F  L2_Replacement [0 ] 0
+OM_F  L1_to_L2 [0 ] 0
+OM_F  Other_GETX [0 ] 0
+OM_F  Other_GETS [0 ] 0
+OM_F  Merged_GETS [0 ] 0
+OM_F  Other_GETS_No_Mig [0 ] 0
+OM_F  NC_DMA_GETS [0 ] 0
+OM_F  Invalidate [0 ] 0
+OM_F  Ack [0 ] 0
+OM_F  All_acks [0 ] 0
+OM_F  All_acks_no_sharers [0 ] 0
+OM_F  Flush_line [0 ] 0
+
+MM_WF  Load [0 ] 0
+MM_WF  Ifetch [0 ] 0
+MM_WF  Store [0 ] 0
+MM_WF  L2_Replacement [0 ] 0
+MM_WF  L1_to_L2 [0 ] 0
+MM_WF  Ack [0 ] 0
+MM_WF  All_acks_no_sharers [0 ] 0
+MM_WF  Flush_line [0 ] 0
 
 Cache Stats: system.dir_cntrl0.probeFilter
   system.dir_cntrl0.probeFilter_total_misses: 0
@@ -563,6 +673,8 @@ All_acks_and_shared_data [0 ] 0
 All_acks_and_owner_data [0 ] 0
 All_acks_and_data_no_sharers [0 ] 0
 All_Unblocks [0 ] 0
+GETF [0 ] 0
+PUTF [0 ] 0
 
  - Transitions -
 NX  GETX [0 ] 0
@@ -571,6 +683,7 @@ NX  PUT [0 ] 0
 NX  Pf_Replacement [0 ] 0
 NX  DMA_READ [0 ] 0
 NX  DMA_WRITE [0 ] 0
+NX  GETF [0 ] 0
 
 NO  GETX [0 ] 0
 NO  GETS [0 ] 0
@@ -578,6 +691,7 @@ NO  PUT [1143 ] 1143
 NO  Pf_Replacement [0 ] 0
 NO  DMA_READ [0 ] 0
 NO  DMA_WRITE [0 ] 0
+NO  GETF [0 ] 0
 
 S  GETX [0 ] 0
 S  GETS [0 ] 0
@@ -585,6 +699,7 @@ S  PUT [0 ] 0
 S  Pf_Replacement [0 ] 0
 S  DMA_READ [0 ] 0
 S  DMA_WRITE [0 ] 0
+S  GETF [0 ] 0
 
 O  GETX [0 ] 0
 O  GETS [0 ] 0
@@ -592,12 +707,14 @@ O  PUT [0 ] 0
 O  Pf_Replacement [0 ] 0
 O  DMA_READ [0 ] 0
 O  DMA_WRITE [0 ] 0
+O  GETF [0 ] 0
 
 E  GETX [158 ] 158
 E  GETS [1001 ] 1001
 E  PUT [0 ] 0
 E  DMA_READ [0 ] 0
 E  DMA_WRITE [0 ] 0
+E  GETF [0 ] 0
 
 O_R  GETX [0 ] 0
 O_R  GETS [0 ] 0
@@ -607,6 +724,7 @@ O_R  DMA_READ [0 ] 0
 O_R  DMA_WRITE [0 ] 0
 O_R  Ack [0 ] 0
 O_R  All_acks_and_data_no_sharers [0 ] 0
+O_R  GETF [0 ] 0
 
 S_R  GETX [0 ] 0
 S_R  GETS [0 ] 0
@@ -617,6 +735,7 @@ S_R  DMA_WRITE [0 ] 0
 S_R  Ack [0 ] 0
 S_R  Data [0 ] 0
 S_R  All_acks_and_data_no_sharers [0 ] 0
+S_R  GETF [0 ] 0
 
 NO_R  GETX [0 ] 0
 NO_R  GETS [0 ] 0
@@ -628,6 +747,7 @@ NO_R  Ack [0 ] 0
 NO_R  Data [0 ] 0
 NO_R  Exclusive_Data [0 ] 0
 NO_R  All_acks_and_data_no_sharers [0 ] 0
+NO_R  GETF [0 ] 0
 
 NO_B  GETX [0 ] 0
 NO_B  GETS [0 ] 0
@@ -637,6 +757,7 @@ NO_B  UnblockM [1159 ] 1159
 NO_B  Pf_Replacement [0 ] 0
 NO_B  DMA_READ [0 ] 0
 NO_B  DMA_WRITE [0 ] 0
+NO_B  GETF [0 ] 0
 
 NO_B_X  GETX [0 ] 0
 NO_B_X  GETS [0 ] 0
@@ -646,6 +767,7 @@ NO_B_X  UnblockM [0 ] 0
 NO_B_X  Pf_Replacement [0 ] 0
 NO_B_X  DMA_READ [0 ] 0
 NO_B_X  DMA_WRITE [0 ] 0
+NO_B_X  GETF [0 ] 0
 
 NO_B_S  GETX [0 ] 0
 NO_B_S  GETS [0 ] 0
@@ -655,6 +777,7 @@ NO_B_S  UnblockM [0 ] 0
 NO_B_S  Pf_Replacement [0 ] 0
 NO_B_S  DMA_READ [0 ] 0
 NO_B_S  DMA_WRITE [0 ] 0
+NO_B_S  GETF [0 ] 0
 
 NO_B_S_W  GETX [0 ] 0
 NO_B_S_W  GETS [0 ] 0
@@ -664,6 +787,7 @@ NO_B_S_W  Pf_Replacement [0 ] 0
 NO_B_S_W  DMA_READ [0 ] 0
 NO_B_S_W  DMA_WRITE [0 ] 0
 NO_B_S_W  All_Unblocks [0 ] 0
+NO_B_S_W  GETF [0 ] 0
 
 O_B  GETX [0 ] 0
 O_B  GETS [0 ] 0
@@ -673,6 +797,7 @@ O_B  UnblockM [0 ] 0
 O_B  Pf_Replacement [0 ] 0
 O_B  DMA_READ [0 ] 0
 O_B  DMA_WRITE [0 ] 0
+O_B  GETF [0 ] 0
 
 NO_B_W  GETX [0 ] 0
 NO_B_W  GETS [0 ] 0
@@ -683,6 +808,7 @@ NO_B_W  Pf_Replacement [0 ] 0
 NO_B_W  DMA_READ [0 ] 0
 NO_B_W  DMA_WRITE [0 ] 0
 NO_B_W  Memory_Data [1159 ] 1159
+NO_B_W  GETF [0 ] 0
 
 O_B_W  GETX [0 ] 0
 O_B_W  GETS [0 ] 0
@@ -692,6 +818,7 @@ O_B_W  Pf_Replacement [0 ] 0
 O_B_W  DMA_READ [0 ] 0
 O_B_W  DMA_WRITE [0 ] 0
 O_B_W  Memory_Data [0 ] 0
+O_B_W  GETF [0 ] 0
 
 NO_W  GETX [0 ] 0
 NO_W  GETS [0 ] 0
@@ -700,6 +827,7 @@ NO_W  Pf_Replacement [0 ] 0
 NO_W  DMA_READ [0 ] 0
 NO_W  DMA_WRITE [0 ] 0
 NO_W  Memory_Data [0 ] 0
+NO_W  GETF [0 ] 0
 
 O_W  GETX [0 ] 0
 O_W  GETS [0 ] 0
@@ -708,6 +836,7 @@ O_W  Pf_Replacement [0 ] 0
 O_W  DMA_READ [0 ] 0
 O_W  DMA_WRITE [0 ] 0
 O_W  Memory_Data [0 ] 0
+O_W  GETF [0 ] 0
 
 NO_DW_B_W  GETX [0 ] 0
 NO_DW_B_W  GETS [0 ] 0
@@ -719,6 +848,7 @@ NO_DW_B_W  Ack [0 ] 0
 NO_DW_B_W  Data [0 ] 0
 NO_DW_B_W  Exclusive_Data [0 ] 0
 NO_DW_B_W  All_acks_and_data_no_sharers [0 ] 0
+NO_DW_B_W  GETF [0 ] 0
 
 NO_DR_B_W  GETX [0 ] 0
 NO_DR_B_W  GETS [0 ] 0
@@ -732,6 +862,7 @@ NO_DR_B_W  Shared_Ack [0 ] 0
 NO_DR_B_W  Shared_Data [0 ] 0
 NO_DR_B_W  Data [0 ] 0
 NO_DR_B_W  Exclusive_Data [0 ] 0
+NO_DR_B_W  GETF [0 ] 0
 
 NO_DR_B_D  GETX [0 ] 0
 NO_DR_B_D  GETS [0 ] 0
@@ -747,6 +878,7 @@ NO_DR_B_D  Exclusive_Data [0 ] 0
 NO_DR_B_D  All_acks_and_shared_data [0 ] 0
 NO_DR_B_D  All_acks_and_owner_data [0 ] 0
 NO_DR_B_D  All_acks_and_data_no_sharers [0 ] 0
+NO_DR_B_D  GETF [0 ] 0
 
 NO_DR_B  GETX [0 ] 0
 NO_DR_B  GETS [0 ] 0
@@ -762,6 +894,7 @@ NO_DR_B  Exclusive_Data [0 ] 0
 NO_DR_B  All_acks_and_shared_data [0 ] 0
 NO_DR_B  All_acks_and_owner_data [0 ] 0
 NO_DR_B  All_acks_and_data_no_sharers [0 ] 0
+NO_DR_B  GETF [0 ] 0
 
 NO_DW_W  GETX [0 ] 0
 NO_DW_W  GETS [0 ] 0
@@ -770,6 +903,7 @@ NO_DW_W  Pf_Replacement [0 ] 0
 NO_DW_W  DMA_READ [0 ] 0
 NO_DW_W  DMA_WRITE [0 ] 0
 NO_DW_W  Memory_Ack [0 ] 0
+NO_DW_W  GETF [0 ] 0
 
 O_DR_B_W  GETX [0 ] 0
 O_DR_B_W  GETS [0 ] 0
@@ -780,6 +914,7 @@ O_DR_B_W  DMA_WRITE [0 ] 0
 O_DR_B_W  Memory_Data [0 ] 0
 O_DR_B_W  Ack [0 ] 0
 O_DR_B_W  Shared_Ack [0 ] 0
+O_DR_B_W  GETF [0 ] 0
 
 O_DR_B  GETX [0 ] 0
 O_DR_B  GETS [0 ] 0
@@ -791,6 +926,7 @@ O_DR_B  Ack [0 ] 0
 O_DR_B  Shared_Ack [0 ] 0
 O_DR_B  All_acks_and_owner_data [0 ] 0
 O_DR_B  All_acks_and_data_no_sharers [0 ] 0
+O_DR_B  GETF [0 ] 0
 
 WB  GETX [27 ] 27
 WB  GETS [19 ] 19
@@ -803,6 +939,7 @@ WB  Writeback_Exclusive_Dirty [220 ] 220
 WB  Pf_Replacement [0 ] 0
 WB  DMA_READ [0 ] 0
 WB  DMA_WRITE [0 ] 0
+WB  GETF [0 ] 0
 
 WB_O_W  GETX [0 ] 0
 WB_O_W  GETS [0 ] 0
@@ -811,6 +948,7 @@ WB_O_W  Pf_Replacement [0 ] 0
 WB_O_W  DMA_READ [0 ] 0
 WB_O_W  DMA_WRITE [0 ] 0
 WB_O_W  Memory_Ack [0 ] 0
+WB_O_W  GETF [0 ] 0
 
 WB_E_W  GETX [4 ] 4
 WB_E_W  GETS [7 ] 7
@@ -818,4 +956,22 @@ WB_E_W  PUT [0 ] 0
 WB_E_W  Pf_Replacement [0 ] 0
 WB_E_W  DMA_READ [0 ] 0
 WB_E_W  DMA_WRITE [0 ] 0
-WB_E_W  Memory_Ack
\ No newline at end of file
+WB_E_W  Memory_Ack [220 ] 220
+WB_E_W  GETF [0 ] 0
+
+NO_F  GETX [0 ] 0
+NO_F  GETS [0 ] 0
+NO_F  PUT [0 ] 0
+NO_F  UnblockM [0 ] 0
+NO_F  Pf_Replacement [0 ] 0
+NO_F  GETF [0 ] 0
+NO_F  PUTF [0 ] 0
+
+NO_F_W  GETX [0 ] 0
+NO_F_W  GETS [0 ] 0
+NO_F_W  PUT [0 ] 0
+NO_F_W  Pf_Replacement [0 ] 0
+NO_F_W  DMA_READ [0 ] 0
+NO_F_W  DMA_WRITE [0 ] 0
+NO_F_W  Memory_Data [0 ] 0
+NO_F_W  GETF
\ No newline at end of file
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index 968d521e0..8cd875f7c 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 17:56:59
-M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
-M5 started Feb  8 2011 17:57:03
-M5 executing on SC2B0617
+M5 compiled Apr 19 2011 12:09:47
+M5 started Apr 19 2011 12:10:00
+M5 executing on maize
 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 5f06bc32c..bbdd232d4 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  50833                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214944                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
-host_tick_rate                                1651975                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  81916                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213028                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
+host_tick_rate                                2661098                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000208                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes               4581                       # nu
 system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_mem_refs                          2060                       # number of memory refs
 system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 5053e806a..dd1e9cef6 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -160,6 +160,7 @@ deadlock_threshold=500000
 icache=system.ruby.cpu_ruby_ports.dcache
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
index a6219b7a9..4874f85a0 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/07/2011 01:47:49
+Real time: Apr/19/2011 11:58:50
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.35
-Virtual_time_in_minutes: 0.00583333
-Virtual_time_in_hours:   9.72222e-05
-Virtual_time_in_days:    4.05093e-06
+Virtual_time_in_seconds: 0.17
+Virtual_time_in_minutes: 0.00283333
+Virtual_time_in_hours:   4.72222e-05
+Virtual_time_in_days:    1.96759e-06
 
 Ruby_current_time: 342698
 Ruby_start_time: 0
 Ruby_cycles: 342698
 
-mbytes_resident: 37.7383
-mbytes_total: 227.77
-resident_ratio: 0.165703
+mbytes_resident: 38.5859
+mbytes_total: 208.09
+resident_ratio: 0.185448
 
 ruby_cycles_executed: [ 342699 ]
 
@@ -70,9 +70,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_L1Cache: [binsize: 1 max: 3 count: 6734 average:     3 | standard deviation: 0 | 0 0 0 6734 ]
 miss_latency_Directory: [binsize: 2 max: 377 count: 1730 average: 181.521 | standard deviation: 26.4115 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -85,12 +85,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average:
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average:   159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 imcomplete_dir_Times: 1729
-miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5684 average:     3 | standard deviation: 0 | 0 0 0 5684 ]
-miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 730 average: 181.192 | standard deviation: 25.9199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 458 average:     3 | standard deviation: 0 | 0 0 0 458 ]
 miss_latency_LD_Directory: [binsize: 2 max: 375 count: 727 average: 178.4 | standard deviation: 21.0913 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 592 average:     3 | standard deviation: 0 | 0 0 0 592 ]
 miss_latency_ST_Directory: [binsize: 2 max: 377 count: 273 average: 190.714 | standard deviation: 36.5384 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5684 average:     3 | standard deviation: 0 | 0 0 0 5684 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 730 average: 181.192 | standard deviation: 25.9199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -122,7 +122,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10742
+page_reclaims: 10179
 page_faults: 0
 swaps: 0
 block_inputs: 0
@@ -181,7 +181,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache
   system.ruby.cpu_ruby_ports.dcache_request_type_ST:   15.7803%
   system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   42.1965%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   1730    100%
+  system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor:   1730    100%
 
  --- L1Cache ---
  - Event Counts -
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
index 6867d8c8b..06d5157d3 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:48
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:50
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index a6f61bb79..546fc87e2 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  16267                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 233240                       # Number of bytes of host memory used
-host_seconds                                     0.39                       # Real time elapsed on the host
-host_tick_rate                                 870027                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  85595                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213088                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                                4571649                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000343                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes               4581                       # nu
 system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_mem_refs                          2060                       # number of memory refs
 system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index 8ac220e1e..49928ea02 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
index 6e929844e..ece1fd443 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:37
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:04:47
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
index 710a7cdd2..fdf9b36d5 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 267933                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 222956                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1366456557                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  19269                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202736                       # Number of bytes of host memory used
+host_seconds                                     0.33                       # Real time elapsed on the host
+host_tick_rate                               99261557                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000033                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses              168                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.025313                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            103.680615                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.025313                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               2050                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses              279                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.062443                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            127.883393                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.062443                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses               6415                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55849.462366                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366                       # average overall mshr miss latency
@@ -202,8 +202,8 @@ system.cpu.l2cache.demand_mshr_misses             446                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.005626                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           184.342479                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.005626                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               447                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -245,6 +245,6 @@ system.cpu.num_int_register_writes               4581                       # nu
 system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_mem_refs                          2060                       # number of memory refs
 system.cpu.num_store_insts                        868                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index e2033d8c4..838834423 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
index 6c13eb8f5..fc9118372 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 21:44:37
-M5 started Mar 17 2011 21:45:02
-M5 executing on zizzer
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:04:56
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 3fca93af7..e80a12bfa 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  58135                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204672                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
-host_tick_rate                              176416397                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 106844                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202600                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                              323591910                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2387                       # Number of instructions simulated
 sim_seconds                                  0.000007                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect                223                       # Nu
 system.cpu.BPredUnit.condPredicted                485                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                      931                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                      174                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches                    396                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events                41                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples         6308                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.408370                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.199072                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0         5350     84.81%     84.81% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1          259      4.11%     88.92% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2          343      5.44%     94.36% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3          133      2.11%     96.46% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4           72      1.14%     97.61% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5           64      1.01%     98.62% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6           26      0.41%     99.03% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7           20      0.32%     99.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8           41      0.65%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total         6308                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                      2576                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                      6                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls               71                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts                  2367                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                       415                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                        709                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts               146                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                        396                       # Number of branches committed
+system.cpu.commit.bw_lim_events                    41                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts           2576                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls               4                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts            1995                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples         6308                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.408370                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.199072                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         5350     84.81%     84.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          259      4.11%     88.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          343      5.44%     94.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          133      2.11%     96.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4           72      1.14%     97.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           64      1.01%     98.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           26      0.41%     99.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           20      0.32%     99.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           41      0.65%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total         6308                       # Number of insts commited each cycle
+system.cpu.commit.count                          2576                       # Number of instructions committed
+system.cpu.commit.fp_insts                          6                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls                   71                       # Number of function calls committed.
+system.cpu.commit.int_insts                      2367                       # Number of committed integer instructions.
+system.cpu.commit.loads                           415                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                            709                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                        2387                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  2387                       # Number of Instructions Simulated
 system.cpu.cpi                               6.107667                       # CPI: Cycles Per Instruction
@@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses               85                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.011366                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0             46.556735                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.011366                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses                883                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 35891.666667                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 35829.411765                       # average overall mshr miss latency
@@ -119,15 +119,15 @@ system.cpu.dcache.tagsinuse                 46.556735                       # Cy
 system.cpu.dcache.total_refs                      703                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles            217                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred             79                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved           136                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts            5047                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles              5111                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles                977                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles             374                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts            284                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles              3                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles                   217                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                    79                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved                  136                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts                   5047                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                     5111                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                       977                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                    374                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                   284                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles                     3                       # Number of cycles decode is unblocking
 system.cpu.dtb.data_accesses                     1010                       # DTB accesses
 system.cpu.dtb.data_acv                             1                       # DTB access violations
 system.cpu.dtb.data_hits                          964                       # DTB hits
@@ -206,8 +206,8 @@ system.cpu.icache.demand_mshr_misses              181                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.044195                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0             90.511194                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.044195                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses                777                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 36200.431034                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 35306.629834                       # average overall mshr miss latency
@@ -230,21 +230,13 @@ system.cpu.icache.total_refs                      545                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                            7897                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                      600                       # Number of branches executed
-system.cpu.iew.EXEC:nop                           311                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.241855                       # Inst execution rate
-system.cpu.iew.EXEC:refs                         1011                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                        366                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                      1995                       # num instructions consuming a value
-system.cpu.iew.WB:count                          3404                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.790977                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                      1578                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.233487                       # insts written-back per cycle
-system.cpu.iew.WB:sent                           3463                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts                  171                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                      600                       # Number of branches executed
+system.cpu.iew.exec_nop                           311                       # number of nop insts executed
+system.cpu.iew.exec_rate                     0.241855                       # Inst execution rate
+system.cpu.iew.exec_refs                         1011                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                        366                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                      48                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts                   779                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                  6                       # Number of dispatched non-speculative instructions
@@ -272,103 +264,93 @@ system.cpu.iew.lsq.thread.0.squashedStores          134                       #
 system.cpu.iew.memOrderViolationEvents              4                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          118                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect             53                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                      1995                       # num instructions consuming a value
+system.cpu.iew.wb_count                          3404                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.790977                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                      1578                       # num instructions producing a value
+system.cpu.iew.wb_rate                       0.233487                       # insts written-back per cycle
+system.cpu.iew.wb_sent                           3463                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                     4291                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    2610                       # number of integer regfile writes
 system.cpu.ipc                               0.163729                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.163729                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu            2594     71.36%     71.36% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              1      0.03%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     71.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead            669     18.40%     89.79% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite           371     10.21%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total             3635                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                    32                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.008803                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu                 1      3.12%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      3.12% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead                9     28.12%     31.25% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite              22     68.75%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples         6682                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.543999                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.232060                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0          5130     76.77%     76.77% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1           639      9.56%     86.34% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2           335      5.01%     91.35% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3           242      3.62%     94.97% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4           178      2.66%     97.64% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5            94      1.41%     99.04% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6            39      0.58%     99.63% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7            16      0.24%     99.87% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8             9      0.13%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total         6682                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.249331                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  2594     71.36%     71.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.03%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                  669     18.40%     89.79% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                 371     10.21%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total                   3635                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                       7                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                  13                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses            6                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                  6                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                          32                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008803                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       1      3.12%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                      9     28.12%     31.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    22     68.75%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses                   3660                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads              14000                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses         3398                       # Number of integer instruction queue wakeup accesses
@@ -380,6 +362,24 @@ system.cpu.iq.iqSquashedInstsExamined            1704                       # Nu
 system.cpu.iq.iqSquashedInstsIssued                29                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined          959                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples          6682                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.543999                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.232060                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                5130     76.77%     76.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                 639      9.56%     86.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 335      5.01%     91.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 242      3.62%     94.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 178      2.66%     97.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                  94      1.41%     99.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  39      0.58%     99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  16      0.24%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                   9      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total            6682                       # Number of insts issued each cycle
+system.cpu.iq.rate                           0.249331                       # Inst issue rate
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
@@ -436,8 +436,8 @@ system.cpu.l2cache.demand_mshr_misses             266                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.003658                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           119.871330                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.003658                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               266                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34351.503759                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31176.691729                       # average overall mshr miss latency
@@ -468,27 +468,27 @@ system.cpu.misc_regfile_writes                      1                       # nu
 system.cpu.numCycles                            14579                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles               55                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps           1768                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents               6                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles              5189                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents              2                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups           5515                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts            4879                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands         3490                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles                901                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles             374                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles             17                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps              1722                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups           12                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups         5503                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles          146                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts            8                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts                 74                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts            6                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                      55                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps                  1768                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                      6                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                     5189                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents                     2                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenameLookups                  5515                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts                   4879                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands                3490                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                       901                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                    374                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles                    17                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                     1722                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups                12                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups             5503                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles            146                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts                  8                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                        74                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts              6                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                        10591                       # The number of ROB reads
 system.cpu.rob.rob_writes                        9519                       # The number of ROB writes
 system.cpu.timesIdled                             151                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
index 800e2e284..534040190 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:37
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:00:19
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index 835697644..50ec4667d 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 290762                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214352                       # Number of bytes of host memory used
+host_inst_rate                                 343171                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 194176                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              142079814                       # Simulator tick rate (ticks/s)
+host_tick_rate                              169102503                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes               1768                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_mem_refs                           717                       # number of memory refs
 system.cpu.num_store_insts                        298                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
index b7bfb0aae..2236053ad 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -63,7 +63,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -201,6 +201,7 @@ deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 594f80de9..5ce289e6f 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/08/2011 17:31:55
+Real time: Apr/19/2011 12:12:40
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.39
-Virtual_time_in_minutes: 0.0065
-Virtual_time_in_hours:   0.000108333
-Virtual_time_in_days:    4.51389e-06
+Virtual_time_in_seconds: 0.16
+Virtual_time_in_minutes: 0.00266667
+Virtual_time_in_hours:   4.44444e-05
+Virtual_time_in_days:    1.85185e-06
 
 Ruby_current_time: 103637
 Ruby_start_time: 0
 Ruby_cycles: 103637
 
-mbytes_resident: 35.7188
-mbytes_total: 209.473
-resident_ratio: 0.170592
+mbytes_resident: 37.7031
+mbytes_total: 207.426
+resident_ratio: 0.181786
 
 ruby_cycles_executed: [ 103638 ]
 
@@ -71,9 +71,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 223 count: 3294 average: 30.4624 | standard deviation: 61.2716 | 0 2722 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 156 96 122 80 3 4 5 3 3 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ]
 miss_latency_LD: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ]
 miss_latency_NULL: [binsize: 2 max: 223 count: 3294 average: 30.4624 | standard deviation: 61.2716 | 0 2722 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 156 96 122 80 3 4 5 3 3 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -85,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 imcomplete_dir_Times: 0
-miss_latency_IFETCH_NULL: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ]
 miss_latency_LD_NULL: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_NULL: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_NULL: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10341
+page_reclaims: 9943
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 64
 
 Network Stats
 -------------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
index 38e786bad..f2d20d5dd 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 17:31:51
-M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip
-M5 started Feb  8 2011 17:31:55
-M5 executing on SC2B0617
+M5 compiled Apr 19 2011 12:12:36
+M5 started Apr 19 2011 12:12:40
+M5 executing on maize
 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
index 591cdf9bb..b8af50b9b 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  31237                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214504                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
-host_tick_rate                                1253532                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  46920                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 212408                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                                1882342                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000104                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes               1768                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_mem_refs                           717                       # number of memory refs
 system.cpu.num_store_insts                        298                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index dae855509..412f71fac 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -63,7 +63,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -197,6 +197,7 @@ deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index b0eff5788..18c0ded27 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/08/2011 17:41:43
+Real time: Apr/19/2011 12:14:52
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.4
-Virtual_time_in_minutes: 0.00666667
-Virtual_time_in_hours:   0.000111111
-Virtual_time_in_days:    4.62963e-06
+Virtual_time_in_seconds: 0.16
+Virtual_time_in_minutes: 0.00266667
+Virtual_time_in_hours:   4.44444e-05
+Virtual_time_in_days:    1.85185e-06
 
 Ruby_current_time: 85988
 Ruby_start_time: 0
 Ruby_cycles: 85988
 
-mbytes_resident: 35.8359
-mbytes_total: 209.617
-resident_ratio: 0.171015
+mbytes_resident: 37.793
+mbytes_total: 207.531
+resident_ratio: 0.182126
 
 ruby_cycles_executed: [ 85989 ]
 
@@ -71,9 +71,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 269 count: 3294 average: 25.1044 | standard deviation: 56.2234 | 0 2784 0 0 0 0 0 0 0 69 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 86 86 80 64 7 5 1 2 0 2 4 2 1 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD: [binsize: 2 max: 267 count: 415 average: 61.0506 | standard deviation: 78.3756 | 0 233 0 0 0 0 0 0 0 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 18 42 18 23 1 0 0 1 0 0 1 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST: [binsize: 2 max: 269 count: 294 average: 29.3027 | standard deviation: 60.9274 | 0 236 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 12 7 4 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_NULL: [binsize: 2 max: 269 count: 3294 average: 25.1044 | standard deviation: 56.2234 | 0 2784 0 0 0 0 0 0 0 69 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 86 86 80 64 7 5 1 2 0 2 4 2 1 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -85,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 imcomplete_dir_Times: 0
-miss_latency_IFETCH_NULL: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD_NULL: [binsize: 2 max: 267 count: 415 average: 61.0506 | standard deviation: 78.3756 | 0 233 0 0 0 0 0 0 0 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 18 42 18 23 1 0 0 1 0 0 1 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_NULL: [binsize: 2 max: 269 count: 294 average: 29.3027 | standard deviation: 60.9274 | 0 236 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 12 7 4 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_NULL: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10362
+page_reclaims: 9966
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 64
 
 Network Stats
 -------------
@@ -411,6 +411,7 @@ Writeback_Ack [411 ] 411
 Writeback_Nack [0 ] 0
 Unblock [0 ] 0
 Exclusive_Unblock [510 ] 510
+DmaAck [0 ] 0
 L2_Replacement [411 ] 411
 
  - Transitions -
@@ -1160,6 +1161,76 @@ ILSI  All_Acks [0 ] 0
 ILSI  Writeback_Ack [0 ] 0
 ILSI  L2_Replacement [0 ] 0
 
+ILOSD  L1_GETS [0 ] 0
+ILOSD  L1_GETX [0 ] 0
+ILOSD  L1_PUTO [0 ] 0
+ILOSD  L1_PUTX [0 ] 0
+ILOSD  L1_PUTS_only [0 ] 0
+ILOSD  L1_PUTS [0 ] 0
+ILOSD  Fwd_GETX [0 ] 0
+ILOSD  Fwd_GETS [0 ] 0
+ILOSD  Fwd_DMA [0 ] 0
+ILOSD  Own_GETX [0 ] 0
+ILOSD  Inv [0 ] 0
+ILOSD  DmaAck [0 ] 0
+ILOSD  L2_Replacement [0 ] 0
+
+ILOSXD  L1_GETS [0 ] 0
+ILOSXD  L1_GETX [0 ] 0
+ILOSXD  L1_PUTO [0 ] 0
+ILOSXD  L1_PUTX [0 ] 0
+ILOSXD  L1_PUTS_only [0 ] 0
+ILOSXD  L1_PUTS [0 ] 0
+ILOSXD  Fwd_GETX [0 ] 0
+ILOSXD  Fwd_GETS [0 ] 0
+ILOSXD  Fwd_DMA [0 ] 0
+ILOSXD  Own_GETX [0 ] 0
+ILOSXD  Inv [0 ] 0
+ILOSXD  DmaAck [0 ] 0
+ILOSXD  L2_Replacement [0 ] 0
+
+ILOD  L1_GETS [0 ] 0
+ILOD  L1_GETX [0 ] 0
+ILOD  L1_PUTO [0 ] 0
+ILOD  L1_PUTX [0 ] 0
+ILOD  L1_PUTS_only [0 ] 0
+ILOD  L1_PUTS [0 ] 0
+ILOD  Fwd_GETX [0 ] 0
+ILOD  Fwd_GETS [0 ] 0
+ILOD  Fwd_DMA [0 ] 0
+ILOD  Own_GETX [0 ] 0
+ILOD  Inv [0 ] 0
+ILOD  DmaAck [0 ] 0
+ILOD  L2_Replacement [0 ] 0
+
+ILXD  L1_GETS [0 ] 0
+ILXD  L1_GETX [0 ] 0
+ILXD  L1_PUTO [0 ] 0
+ILXD  L1_PUTX [0 ] 0
+ILXD  L1_PUTS_only [0 ] 0
+ILXD  L1_PUTS [0 ] 0
+ILXD  Fwd_GETX [0 ] 0
+ILXD  Fwd_GETS [0 ] 0
+ILXD  Fwd_DMA [0 ] 0
+ILXD  Own_GETX [0 ] 0
+ILXD  Inv [0 ] 0
+ILXD  DmaAck [0 ] 0
+ILXD  L2_Replacement [0 ] 0
+
+ILOXD  L1_GETS [0 ] 0
+ILOXD  L1_GETX [0 ] 0
+ILOXD  L1_PUTO [0 ] 0
+ILOXD  L1_PUTX [0 ] 0
+ILOXD  L1_PUTS_only [0 ] 0
+ILOXD  L1_PUTS [0 ] 0
+ILOXD  Fwd_GETX [0 ] 0
+ILOXD  Fwd_GETS [0 ] 0
+ILOXD  Fwd_DMA [0 ] 0
+ILOXD  Own_GETX [0 ] 0
+ILOXD  Inv [0 ] 0
+ILOXD  DmaAck [0 ] 0
+ILOXD  L2_Replacement [0 ] 0
+
 Memory controller: system.dir_cntrl0.memBuffer:
   memory_total_requests: 504
   memory_reads: 427
@@ -1196,6 +1267,7 @@ Memory_Data [427 ] 427
 Memory_Ack [77 ] 77
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
+DMA_ACK [0 ] 0
 Data [0 ] 0
 
  - Transitions -
@@ -1376,4 +1448,22 @@ OI_D  PUTO [0 ] 0
 OI_D  PUTO_SHARERS [0 ] 0
 OI_D  DMA_READ [0 ] 0
 OI_D  DMA_WRITE [0 ] 0
-OI_D  Data
\ No newline at end of file
+OI_D  Data [0 ] 0
+
+OD  GETX [0 ] 0
+OD  GETS [0 ] 0
+OD  PUTX [0 ] 0
+OD  PUTO [0 ] 0
+OD  PUTO_SHARERS [0 ] 0
+OD  DMA_READ [0 ] 0
+OD  DMA_WRITE [0 ] 0
+OD  DMA_ACK [0 ] 0
+
+MD  GETX [0 ] 0
+MD  GETS [0 ] 0
+MD  PUTX [0 ] 0
+MD  PUTO [0 ] 0
+MD  PUTO_SHARERS [0 ] 0
+MD  DMA_READ [0 ] 0
+MD  DMA_WRITE [0 ] 0
+MD  DMA_ACK
\ No newline at end of file
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index 2588731f1..26db17bca 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 17:41:34
-M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
-M5 started Feb  8 2011 17:41:42
-M5 executing on SC2B0617
+M5 compiled Apr 19 2011 12:14:48
+M5 started Apr 19 2011 12:14:52
+M5 executing on maize
 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index dd02fbf60..274f15f77 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  26760                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214652                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
-host_tick_rate                                 891261                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  38282                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 212516                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                                1274831                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000086                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes               1768                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_mem_refs                           717                       # number of memory refs
 system.cpu.num_store_insts                        298                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index 0c0cc2e1c..d99bf3102 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -63,7 +63,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index 54abfd298..9fa414f7b 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Mar/26/2011 22:00:44
+Real time: Apr/19/2011 12:17:16
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.19
-Virtual_time_in_minutes: 0.00316667
-Virtual_time_in_hours:   5.27778e-05
-Virtual_time_in_days:    2.19907e-06
+Virtual_time_in_seconds: 0.14
+Virtual_time_in_minutes: 0.00233333
+Virtual_time_in_hours:   3.88889e-05
+Virtual_time_in_days:    1.62037e-06
 
 Ruby_current_time: 84059
 Ruby_start_time: 0
 Ruby_cycles: 84059
 
-mbytes_resident: 36.8242
-mbytes_total: 198.527
-resident_ratio: 0.185507
+mbytes_resident: 37.6562
+mbytes_total: 207.355
+resident_ratio: 0.181621
 
 ruby_cycles_executed: [ 84060 ]
 
@@ -127,7 +127,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9723
+page_reclaims: 9934
 page_faults: 0
 swaps: 0
 block_inputs: 0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index f5c0cf433..978cef283 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 26 2011 14:06:20
-M5 started Mar 26 2011 22:00:43
-M5 executing on phenom
+M5 compiled Apr 19 2011 12:17:10
+M5 started Apr 19 2011 12:17:16
+M5 executing on maize
 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index ab4470f42..ef789547c 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                   8652                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 203296                       # Number of bytes of host memory used
-host_seconds                                     0.30                       # Real time elapsed on the host
-host_tick_rate                                 282076                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  40575                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 212336                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                                1320785                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000084                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes               1768                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_mem_refs                           717                       # number of memory refs
 system.cpu.num_store_insts                        298                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index 08f882272..b810f5467 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -63,7 +63,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -184,6 +184,7 @@ deadlock_threshold=500000
 icache=system.ruby.cpu_ruby_ports.icache
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
index 3e0d391db..4245fbc90 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/08/2011 17:57:03
+Real time: Apr/19/2011 12:09:50
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.34
-Virtual_time_in_minutes: 0.00566667
-Virtual_time_in_hours:   9.44444e-05
-Virtual_time_in_days:    3.93519e-06
+Virtual_time_in_seconds: 0.13
+Virtual_time_in_minutes: 0.00216667
+Virtual_time_in_hours:   3.61111e-05
+Virtual_time_in_days:    1.50463e-06
 
 Ruby_current_time: 78448
 Ruby_start_time: 0
 Ruby_cycles: 78448
 
-mbytes_resident: 35.3906
-mbytes_total: 208.879
-resident_ratio: 0.169469
+mbytes_resident: 37.4102
+mbytes_total: 207.098
+resident_ratio: 0.180659
 
 ruby_cycles_executed: [ 78449 ]
 
@@ -70,9 +70,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8154 | standard deviation: 52.8821 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
 miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.3952 | standard deviation: 74.7751 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.9728 | standard deviation: 63.5282 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
 miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average:     2 | standard deviation: 0 | 0 0 2784 ]
 miss_latency_L2Cache: [binsize: 1 max: 13 count: 69 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 69 ]
 miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.757 | standard deviation: 21.4255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
@@ -86,15 +86,15 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average:
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average:   158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
 imcomplete_dir_Times: 440
-miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average:     2 | standard deviation: 0 | 0 0 2315 ]
-miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
-miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
 miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average:     2 | standard deviation: 0 | 0 0 233 ]
 miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 36 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 36 ]
 miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 156.747 | standard deviation: 24.5989 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average:     2 | standard deviation: 0 | 0 0 236 ]
 miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 11 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 11 ]
 miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 168.149 | standard deviation: 46.0633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average:     2 | standard deviation: 0 | 0 0 2315 ]
+miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
+miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -126,11 +126,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10290
+page_reclaims: 9871
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 64
 
 Network Stats
 -------------
@@ -190,7 +190,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.icache
 
   system.ruby.cpu_ruby_ports.icache_request_type_IFETCH:   100%
 
-  system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode:   270    100%
+  system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor:   270    100%
 
 Cache Stats: system.ruby.cpu_ruby_ports.dcache
   system.ruby.cpu_ruby_ports.dcache_total_misses: 240
@@ -202,7 +202,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache
   system.ruby.cpu_ruby_ports.dcache_request_type_LD:   75.8333%
   system.ruby.cpu_ruby_ports.dcache_request_type_ST:   24.1667%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   240    100%
+  system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor:   240    100%
 
 Cache Stats: system.l1_cntrl0.L2cacheMemory
   system.l1_cntrl0.L2cacheMemory_total_misses: 510
@@ -215,7 +215,7 @@ Cache Stats: system.l1_cntrl0.L2cacheMemory
   system.l1_cntrl0.L2cacheMemory_request_type_ST:   11.3725%
   system.l1_cntrl0.L2cacheMemory_request_type_IFETCH:   52.9412%
 
-  system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   510    100%
+  system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   510    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -242,6 +242,8 @@ Writeback_Ack [425 ] 425
 Writeback_Nack [0 ] 0
 All_acks [0 ] 0
 All_acks_no_sharers [441 ] 441
+Flush_line [0 ] 0
+Block_Ack [0 ] 0
 
  - Transitions -
 I  Load [146 ] 146
@@ -256,6 +258,7 @@ I  Other_GETS [0 ] 0
 I  Other_GETS_No_Mig [0 ] 0
 I  NC_DMA_GETS [0 ] 0
 I  Invalidate [0 ] 0
+I  Flush_line [0 ] 0
 
 S  Load [0 ] 0
 S  Ifetch [0 ] 0
@@ -269,6 +272,7 @@ S  Other_GETS [0 ] 0
 S  Other_GETS_No_Mig [0 ] 0
 S  NC_DMA_GETS [0 ] 0
 S  Invalidate [0 ] 0
+S  Flush_line [0 ] 0
 
 O  Load [0 ] 0
 O  Ifetch [0 ] 0
@@ -283,6 +287,7 @@ O  Merged_GETS [0 ] 0
 O  Other_GETS_No_Mig [0 ] 0
 O  NC_DMA_GETS [0 ] 0
 O  Invalidate [0 ] 0
+O  Flush_line [0 ] 0
 
 M  Load [131 ] 131
 M  Ifetch [2337 ] 2337
@@ -297,6 +302,7 @@ M  Merged_GETS [0 ] 0
 M  Other_GETS_No_Mig [0 ] 0
 M  NC_DMA_GETS [0 ] 0
 M  Invalidate [0 ] 0
+M  Flush_line [0 ] 0
 
 MM  Load [138 ] 138
 MM  Ifetch [0 ] 0
@@ -311,6 +317,7 @@ MM  Merged_GETS [0 ] 0
 MM  Other_GETS_No_Mig [0 ] 0
 MM  NC_DMA_GETS [0 ] 0
 MM  Invalidate [0 ] 0
+MM  Flush_line [0 ] 0
 
 IM  Load [0 ] 0
 IM  Ifetch [0 ] 0
@@ -325,6 +332,7 @@ IM  Invalidate [0 ] 0
 IM  Ack [0 ] 0
 IM  Data [0 ] 0
 IM  Exclusive_Data [47 ] 47
+IM  Flush_line [0 ] 0
 
 SM  Load [0 ] 0
 SM  Ifetch [0 ] 0
@@ -339,6 +347,7 @@ SM  Invalidate [0 ] 0
 SM  Ack [0 ] 0
 SM  Data [0 ] 0
 SM  Exclusive_Data [0 ] 0
+SM  Flush_line [0 ] 0
 
 OM  Load [0 ] 0
 OM  Ifetch [0 ] 0
@@ -354,6 +363,7 @@ OM  Invalidate [0 ] 0
 OM  Ack [0 ] 0
 OM  All_acks [0 ] 0
 OM  All_acks_no_sharers [0 ] 0
+OM  Flush_line [0 ] 0
 
 ISM  Load [0 ] 0
 ISM  Ifetch [0 ] 0
@@ -362,6 +372,7 @@ ISM  L2_Replacement [0 ] 0
 ISM  L1_to_L2 [0 ] 0
 ISM  Ack [0 ] 0
 ISM  All_acks_no_sharers [0 ] 0
+ISM  Flush_line [0 ] 0
 
 M_W  Load [0 ] 0
 M_W  Ifetch [0 ] 0
@@ -370,6 +381,7 @@ M_W  L2_Replacement [0 ] 0
 M_W  L1_to_L2 [0 ] 0
 M_W  Ack [0 ] 0
 M_W  All_acks_no_sharers [394 ] 394
+M_W  Flush_line [0 ] 0
 
 MM_W  Load [0 ] 0
 MM_W  Ifetch [0 ] 0
@@ -378,6 +390,7 @@ MM_W  L2_Replacement [0 ] 0
 MM_W  L1_to_L2 [0 ] 0
 MM_W  Ack [0 ] 0
 MM_W  All_acks_no_sharers [47 ] 47
+MM_W  Flush_line [0 ] 0
 
 IS  Load [0 ] 0
 IS  Ifetch [0 ] 0
@@ -394,6 +407,7 @@ IS  Shared_Ack [0 ] 0
 IS  Data [0 ] 0
 IS  Shared_Data [0 ] 0
 IS  Exclusive_Data [394 ] 394
+IS  Flush_line [0 ] 0
 
 SS  Load [0 ] 0
 SS  Ifetch [0 ] 0
@@ -404,6 +418,7 @@ SS  Ack [0 ] 0
 SS  Shared_Ack [0 ] 0
 SS  All_acks [0 ] 0
 SS  All_acks_no_sharers [0 ] 0
+SS  Flush_line [0 ] 0
 
 OI  Load [0 ] 0
 OI  Ifetch [0 ] 0
@@ -417,6 +432,7 @@ OI  Other_GETS_No_Mig [0 ] 0
 OI  NC_DMA_GETS [0 ] 0
 OI  Invalidate [0 ] 0
 OI  Writeback_Ack [0 ] 0
+OI  Flush_line [0 ] 0
 
 MI  Load [7 ] 7
 MI  Ifetch [6 ] 6
@@ -430,6 +446,7 @@ MI  Other_GETS_No_Mig [0 ] 0
 MI  NC_DMA_GETS [0 ] 0
 MI  Invalidate [0 ] 0
 MI  Writeback_Ack [425 ] 425
+MI  Flush_line [0 ] 0
 
 II  Load [0 ] 0
 II  Ifetch [0 ] 0
@@ -443,6 +460,7 @@ II  NC_DMA_GETS [0 ] 0
 II  Invalidate [0 ] 0
 II  Writeback_Ack [0 ] 0
 II  Writeback_Nack [0 ] 0
+II  Flush_line [0 ] 0
 
 IT  Load [0 ] 0
 IT  Ifetch [0 ] 0
@@ -456,6 +474,7 @@ IT  Merged_GETS [0 ] 0
 IT  Other_GETS_No_Mig [0 ] 0
 IT  NC_DMA_GETS [0 ] 0
 IT  Invalidate [0 ] 0
+IT  Flush_line [0 ] 0
 
 ST  Load [0 ] 0
 ST  Ifetch [0 ] 0
@@ -469,6 +488,7 @@ ST  Merged_GETS [0 ] 0
 ST  Other_GETS_No_Mig [0 ] 0
 ST  NC_DMA_GETS [0 ] 0
 ST  Invalidate [0 ] 0
+ST  Flush_line [0 ] 0
 
 OT  Load [0 ] 0
 OT  Ifetch [0 ] 0
@@ -482,6 +502,7 @@ OT  Merged_GETS [0 ] 0
 OT  Other_GETS_No_Mig [0 ] 0
 OT  NC_DMA_GETS [0 ] 0
 OT  Invalidate [0 ] 0
+OT  Flush_line [0 ] 0
 
 MT  Load [0 ] 0
 MT  Ifetch [0 ] 0
@@ -495,6 +516,7 @@ MT  Merged_GETS [0 ] 0
 MT  Other_GETS_No_Mig [0 ] 0
 MT  NC_DMA_GETS [0 ] 0
 MT  Invalidate [0 ] 0
+MT  Flush_line [0 ] 0
 
 MMT  Load [0 ] 0
 MMT  Ifetch [0 ] 0
@@ -508,6 +530,94 @@ MMT  Merged_GETS [0 ] 0
 MMT  Other_GETS_No_Mig [0 ] 0
 MMT  NC_DMA_GETS [0 ] 0
 MMT  Invalidate [0 ] 0
+MMT  Flush_line [0 ] 0
+
+MI_F  Load [0 ] 0
+MI_F  Ifetch [0 ] 0
+MI_F  Store [0 ] 0
+MI_F  L1_to_L2 [0 ] 0
+MI_F  Writeback_Ack [0 ] 0
+MI_F  Flush_line [0 ] 0
+
+MM_F  Load [0 ] 0
+MM_F  Ifetch [0 ] 0
+MM_F  Store [0 ] 0
+MM_F  L1_to_L2 [0 ] 0
+MM_F  Other_GETX [0 ] 0
+MM_F  Other_GETS [0 ] 0
+MM_F  Merged_GETS [0 ] 0
+MM_F  Other_GETS_No_Mig [0 ] 0
+MM_F  NC_DMA_GETS [0 ] 0
+MM_F  Invalidate [0 ] 0
+MM_F  Ack [0 ] 0
+MM_F  All_acks [0 ] 0
+MM_F  All_acks_no_sharers [0 ] 0
+MM_F  Flush_line [0 ] 0
+MM_F  Block_Ack [0 ] 0
+
+IM_F  Load [0 ] 0
+IM_F  Ifetch [0 ] 0
+IM_F  Store [0 ] 0
+IM_F  L2_Replacement [0 ] 0
+IM_F  L1_to_L2 [0 ] 0
+IM_F  Other_GETX [0 ] 0
+IM_F  Other_GETS [0 ] 0
+IM_F  Other_GETS_No_Mig [0 ] 0
+IM_F  NC_DMA_GETS [0 ] 0
+IM_F  Invalidate [0 ] 0
+IM_F  Ack [0 ] 0
+IM_F  Data [0 ] 0
+IM_F  Exclusive_Data [0 ] 0
+IM_F  Flush_line [0 ] 0
+
+ISM_F  Load [0 ] 0
+ISM_F  Ifetch [0 ] 0
+ISM_F  Store [0 ] 0
+ISM_F  L2_Replacement [0 ] 0
+ISM_F  L1_to_L2 [0 ] 0
+ISM_F  Ack [0 ] 0
+ISM_F  All_acks_no_sharers [0 ] 0
+ISM_F  Flush_line [0 ] 0
+
+SM_F  Load [0 ] 0
+SM_F  Ifetch [0 ] 0
+SM_F  Store [0 ] 0
+SM_F  L2_Replacement [0 ] 0
+SM_F  L1_to_L2 [0 ] 0
+SM_F  Other_GETX [0 ] 0
+SM_F  Other_GETS [0 ] 0
+SM_F  Other_GETS_No_Mig [0 ] 0
+SM_F  NC_DMA_GETS [0 ] 0
+SM_F  Invalidate [0 ] 0
+SM_F  Ack [0 ] 0
+SM_F  Data [0 ] 0
+SM_F  Exclusive_Data [0 ] 0
+SM_F  Flush_line [0 ] 0
+
+OM_F  Load [0 ] 0
+OM_F  Ifetch [0 ] 0
+OM_F  Store [0 ] 0
+OM_F  L2_Replacement [0 ] 0
+OM_F  L1_to_L2 [0 ] 0
+OM_F  Other_GETX [0 ] 0
+OM_F  Other_GETS [0 ] 0
+OM_F  Merged_GETS [0 ] 0
+OM_F  Other_GETS_No_Mig [0 ] 0
+OM_F  NC_DMA_GETS [0 ] 0
+OM_F  Invalidate [0 ] 0
+OM_F  Ack [0 ] 0
+OM_F  All_acks [0 ] 0
+OM_F  All_acks_no_sharers [0 ] 0
+OM_F  Flush_line [0 ] 0
+
+MM_WF  Load [0 ] 0
+MM_WF  Ifetch [0 ] 0
+MM_WF  Store [0 ] 0
+MM_WF  L2_Replacement [0 ] 0
+MM_WF  L1_to_L2 [0 ] 0
+MM_WF  Ack [0 ] 0
+MM_WF  All_acks_no_sharers [0 ] 0
+MM_WF  Flush_line [0 ] 0
 
 Cache Stats: system.dir_cntrl0.probeFilter
   system.dir_cntrl0.probeFilter_total_misses: 0
@@ -563,6 +673,8 @@ All_acks_and_shared_data [0 ] 0
 All_acks_and_owner_data [0 ] 0
 All_acks_and_data_no_sharers [0 ] 0
 All_Unblocks [0 ] 0
+GETF [0 ] 0
+PUTF [0 ] 0
 
  - Transitions -
 NX  GETX [0 ] 0
@@ -571,6 +683,7 @@ NX  PUT [0 ] 0
 NX  Pf_Replacement [0 ] 0
 NX  DMA_READ [0 ] 0
 NX  DMA_WRITE [0 ] 0
+NX  GETF [0 ] 0
 
 NO  GETX [0 ] 0
 NO  GETS [0 ] 0
@@ -578,6 +691,7 @@ NO  PUT [425 ] 425
 NO  Pf_Replacement [0 ] 0
 NO  DMA_READ [0 ] 0
 NO  DMA_WRITE [0 ] 0
+NO  GETF [0 ] 0
 
 S  GETX [0 ] 0
 S  GETS [0 ] 0
@@ -585,6 +699,7 @@ S  PUT [0 ] 0
 S  Pf_Replacement [0 ] 0
 S  DMA_READ [0 ] 0
 S  DMA_WRITE [0 ] 0
+S  GETF [0 ] 0
 
 O  GETX [0 ] 0
 O  GETS [0 ] 0
@@ -592,12 +707,14 @@ O  PUT [0 ] 0
 O  Pf_Replacement [0 ] 0
 O  DMA_READ [0 ] 0
 O  DMA_WRITE [0 ] 0
+O  GETF [0 ] 0
 
 E  GETX [47 ] 47
 E  GETS [394 ] 394
 E  PUT [0 ] 0
 E  DMA_READ [0 ] 0
 E  DMA_WRITE [0 ] 0
+E  GETF [0 ] 0
 
 O_R  GETX [0 ] 0
 O_R  GETS [0 ] 0
@@ -607,6 +724,7 @@ O_R  DMA_READ [0 ] 0
 O_R  DMA_WRITE [0 ] 0
 O_R  Ack [0 ] 0
 O_R  All_acks_and_data_no_sharers [0 ] 0
+O_R  GETF [0 ] 0
 
 S_R  GETX [0 ] 0
 S_R  GETS [0 ] 0
@@ -617,6 +735,7 @@ S_R  DMA_WRITE [0 ] 0
 S_R  Ack [0 ] 0
 S_R  Data [0 ] 0
 S_R  All_acks_and_data_no_sharers [0 ] 0
+S_R  GETF [0 ] 0
 
 NO_R  GETX [0 ] 0
 NO_R  GETS [0 ] 0
@@ -628,6 +747,7 @@ NO_R  Ack [0 ] 0
 NO_R  Data [0 ] 0
 NO_R  Exclusive_Data [0 ] 0
 NO_R  All_acks_and_data_no_sharers [0 ] 0
+NO_R  GETF [0 ] 0
 
 NO_B  GETX [0 ] 0
 NO_B  GETS [0 ] 0
@@ -637,6 +757,7 @@ NO_B  UnblockM [440 ] 440
 NO_B  Pf_Replacement [0 ] 0
 NO_B  DMA_READ [0 ] 0
 NO_B  DMA_WRITE [0 ] 0
+NO_B  GETF [0 ] 0
 
 NO_B_X  GETX [0 ] 0
 NO_B_X  GETS [0 ] 0
@@ -646,6 +767,7 @@ NO_B_X  UnblockM [0 ] 0
 NO_B_X  Pf_Replacement [0 ] 0
 NO_B_X  DMA_READ [0 ] 0
 NO_B_X  DMA_WRITE [0 ] 0
+NO_B_X  GETF [0 ] 0
 
 NO_B_S  GETX [0 ] 0
 NO_B_S  GETS [0 ] 0
@@ -655,6 +777,7 @@ NO_B_S  UnblockM [0 ] 0
 NO_B_S  Pf_Replacement [0 ] 0
 NO_B_S  DMA_READ [0 ] 0
 NO_B_S  DMA_WRITE [0 ] 0
+NO_B_S  GETF [0 ] 0
 
 NO_B_S_W  GETX [0 ] 0
 NO_B_S_W  GETS [0 ] 0
@@ -664,6 +787,7 @@ NO_B_S_W  Pf_Replacement [0 ] 0
 NO_B_S_W  DMA_READ [0 ] 0
 NO_B_S_W  DMA_WRITE [0 ] 0
 NO_B_S_W  All_Unblocks [0 ] 0
+NO_B_S_W  GETF [0 ] 0
 
 O_B  GETX [0 ] 0
 O_B  GETS [0 ] 0
@@ -673,6 +797,7 @@ O_B  UnblockM [0 ] 0
 O_B  Pf_Replacement [0 ] 0
 O_B  DMA_READ [0 ] 0
 O_B  DMA_WRITE [0 ] 0
+O_B  GETF [0 ] 0
 
 NO_B_W  GETX [0 ] 0
 NO_B_W  GETS [0 ] 0
@@ -683,6 +808,7 @@ NO_B_W  Pf_Replacement [0 ] 0
 NO_B_W  DMA_READ [0 ] 0
 NO_B_W  DMA_WRITE [0 ] 0
 NO_B_W  Memory_Data [441 ] 441
+NO_B_W  GETF [0 ] 0
 
 O_B_W  GETX [0 ] 0
 O_B_W  GETS [0 ] 0
@@ -692,6 +818,7 @@ O_B_W  Pf_Replacement [0 ] 0
 O_B_W  DMA_READ [0 ] 0
 O_B_W  DMA_WRITE [0 ] 0
 O_B_W  Memory_Data [0 ] 0
+O_B_W  GETF [0 ] 0
 
 NO_W  GETX [0 ] 0
 NO_W  GETS [0 ] 0
@@ -700,6 +827,7 @@ NO_W  Pf_Replacement [0 ] 0
 NO_W  DMA_READ [0 ] 0
 NO_W  DMA_WRITE [0 ] 0
 NO_W  Memory_Data [0 ] 0
+NO_W  GETF [0 ] 0
 
 O_W  GETX [0 ] 0
 O_W  GETS [0 ] 0
@@ -708,6 +836,7 @@ O_W  Pf_Replacement [0 ] 0
 O_W  DMA_READ [0 ] 0
 O_W  DMA_WRITE [0 ] 0
 O_W  Memory_Data [0 ] 0
+O_W  GETF [0 ] 0
 
 NO_DW_B_W  GETX [0 ] 0
 NO_DW_B_W  GETS [0 ] 0
@@ -719,6 +848,7 @@ NO_DW_B_W  Ack [0 ] 0
 NO_DW_B_W  Data [0 ] 0
 NO_DW_B_W  Exclusive_Data [0 ] 0
 NO_DW_B_W  All_acks_and_data_no_sharers [0 ] 0
+NO_DW_B_W  GETF [0 ] 0
 
 NO_DR_B_W  GETX [0 ] 0
 NO_DR_B_W  GETS [0 ] 0
@@ -732,6 +862,7 @@ NO_DR_B_W  Shared_Ack [0 ] 0
 NO_DR_B_W  Shared_Data [0 ] 0
 NO_DR_B_W  Data [0 ] 0
 NO_DR_B_W  Exclusive_Data [0 ] 0
+NO_DR_B_W  GETF [0 ] 0
 
 NO_DR_B_D  GETX [0 ] 0
 NO_DR_B_D  GETS [0 ] 0
@@ -747,6 +878,7 @@ NO_DR_B_D  Exclusive_Data [0 ] 0
 NO_DR_B_D  All_acks_and_shared_data [0 ] 0
 NO_DR_B_D  All_acks_and_owner_data [0 ] 0
 NO_DR_B_D  All_acks_and_data_no_sharers [0 ] 0
+NO_DR_B_D  GETF [0 ] 0
 
 NO_DR_B  GETX [0 ] 0
 NO_DR_B  GETS [0 ] 0
@@ -762,6 +894,7 @@ NO_DR_B  Exclusive_Data [0 ] 0
 NO_DR_B  All_acks_and_shared_data [0 ] 0
 NO_DR_B  All_acks_and_owner_data [0 ] 0
 NO_DR_B  All_acks_and_data_no_sharers [0 ] 0
+NO_DR_B  GETF [0 ] 0
 
 NO_DW_W  GETX [0 ] 0
 NO_DW_W  GETS [0 ] 0
@@ -770,6 +903,7 @@ NO_DW_W  Pf_Replacement [0 ] 0
 NO_DW_W  DMA_READ [0 ] 0
 NO_DW_W  DMA_WRITE [0 ] 0
 NO_DW_W  Memory_Ack [0 ] 0
+NO_DW_W  GETF [0 ] 0
 
 O_DR_B_W  GETX [0 ] 0
 O_DR_B_W  GETS [0 ] 0
@@ -780,6 +914,7 @@ O_DR_B_W  DMA_WRITE [0 ] 0
 O_DR_B_W  Memory_Data [0 ] 0
 O_DR_B_W  Ack [0 ] 0
 O_DR_B_W  Shared_Ack [0 ] 0
+O_DR_B_W  GETF [0 ] 0
 
 O_DR_B  GETX [0 ] 0
 O_DR_B  GETS [0 ] 0
@@ -791,6 +926,7 @@ O_DR_B  Ack [0 ] 0
 O_DR_B  Shared_Ack [0 ] 0
 O_DR_B  All_acks_and_owner_data [0 ] 0
 O_DR_B  All_acks_and_data_no_sharers [0 ] 0
+O_DR_B  GETF [0 ] 0
 
 WB  GETX [4 ] 4
 WB  GETS [14 ] 14
@@ -803,6 +939,7 @@ WB  Writeback_Exclusive_Dirty [81 ] 81
 WB  Pf_Replacement [0 ] 0
 WB  DMA_READ [0 ] 0
 WB  DMA_WRITE [0 ] 0
+WB  GETF [0 ] 0
 
 WB_O_W  GETX [0 ] 0
 WB_O_W  GETS [0 ] 0
@@ -811,6 +948,7 @@ WB_O_W  Pf_Replacement [0 ] 0
 WB_O_W  DMA_READ [0 ] 0
 WB_O_W  DMA_WRITE [0 ] 0
 WB_O_W  Memory_Ack [0 ] 0
+WB_O_W  GETF [0 ] 0
 
 WB_E_W  GETX [2 ] 2
 WB_E_W  GETS [2 ] 2
@@ -818,4 +956,22 @@ WB_E_W  PUT [0 ] 0
 WB_E_W  Pf_Replacement [0 ] 0
 WB_E_W  DMA_READ [0 ] 0
 WB_E_W  DMA_WRITE [0 ] 0
-WB_E_W  Memory_Ack
\ No newline at end of file
+WB_E_W  Memory_Ack [81 ] 81
+WB_E_W  GETF [0 ] 0
+
+NO_F  GETX [0 ] 0
+NO_F  GETS [0 ] 0
+NO_F  PUT [0 ] 0
+NO_F  UnblockM [0 ] 0
+NO_F  Pf_Replacement [0 ] 0
+NO_F  GETF [0 ] 0
+NO_F  PUTF [0 ] 0
+
+NO_F_W  GETX [0 ] 0
+NO_F_W  GETS [0 ] 0
+NO_F_W  PUT [0 ] 0
+NO_F_W  Pf_Replacement [0 ] 0
+NO_F_W  DMA_READ [0 ] 0
+NO_F_W  DMA_WRITE [0 ] 0
+NO_F_W  Memory_Data [0 ] 0
+NO_F_W  GETF
\ No newline at end of file
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
index 06957aba3..256657039 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 17:56:59
-M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
-M5 started Feb  8 2011 17:57:03
-M5 executing on SC2B0617
+M5 compiled Apr 19 2011 12:09:47
+M5 started Apr 19 2011 12:09:50
+M5 executing on maize
 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index 73743c0c5..6446a9edb 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  49095                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 213896                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
-host_tick_rate                                1489708                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  62557                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 212072                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
+host_tick_rate                                1897992                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000078                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes               1768                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_mem_refs                           717                       # number of memory refs
 system.cpu.num_store_insts                        298                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 71495ec84..a38ab1515 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -160,6 +160,7 @@ deadlock_threshold=500000
 icache=system.ruby.cpu_ruby_ports.dcache
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
index c43ead0e8..986bc42a5 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/07/2011 01:47:37
+Real time: Apr/19/2011 12:00:50
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.26
-Virtual_time_in_minutes: 0.00433333
-Virtual_time_in_hours:   7.22222e-05
-Virtual_time_in_days:    3.00926e-06
+Virtual_time_in_seconds: 0.13
+Virtual_time_in_minutes: 0.00216667
+Virtual_time_in_hours:   3.61111e-05
+Virtual_time_in_days:    1.50463e-06
 
 Ruby_current_time: 123378
 Ruby_start_time: 0
 Ruby_cycles: 123378
 
-mbytes_resident: 36.4062
-mbytes_total: 226.781
-resident_ratio: 0.160552
+mbytes_resident: 37.2734
+mbytes_total: 207.098
+resident_ratio: 0.179999
 
 ruby_cycles_executed: [ 123379 ]
 
@@ -70,9 +70,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 375 count: 3294 average: 36.4554 | standard deviation: 69.7725 | 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_LD: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_L1Cache: [binsize: 1 max: 3 count: 2668 average:     3 | standard deviation: 0 | 0 0 0 2668 ]
 miss_latency_Directory: [binsize: 2 max: 375 count: 626 average: 179.042 | standard deviation: 22.5462 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -85,12 +85,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average:
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average:   159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 imcomplete_dir_Times: 625
-miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average:     3 | standard deviation: 0 | 0 0 0 2288 ]
-miss_latency_IFETCH_Directory: [binsize: 2 max: 375 count: 297 average: 178.556 | standard deviation: 21.9279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 170 average:     3 | standard deviation: 0 | 0 0 0 170 ]
 miss_latency_LD_Directory: [binsize: 2 max: 281 count: 245 average: 179.678 | standard deviation: 23.5327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 210 average:     3 | standard deviation: 0 | 0 0 0 210 ]
 miss_latency_ST_Directory: [binsize: 2 max: 265 count: 84 average: 178.905 | standard deviation: 21.977 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average:     3 | standard deviation: 0 | 0 0 0 2288 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 375 count: 297 average: 178.556 | standard deviation: 21.9279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -122,7 +122,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10395
+page_reclaims: 9841
 page_faults: 0
 swaps: 0
 block_inputs: 0
@@ -181,7 +181,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache
   system.ruby.cpu_ruby_ports.dcache_request_type_ST:   13.4185%
   system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   47.4441%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   626    100%
+  system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor:   626    100%
 
  --- L1Cache ---
  - Event Counts -
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
index 5f04faac1..69d07c3aa 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:36
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:00:50
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index 8d615ceb9..a05c1b96e 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  17883                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 232228                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
-host_tick_rate                                 854675                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  79660                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 212072                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
+host_tick_rate                                3797301                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000123                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes               1768                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_mem_refs                           717                       # number of memory refs
 system.cpu.num_store_insts                        298                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 6019fe73e..965487eb2 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
index 37ac69d98..363499d94 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:36
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:24
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index aa9ef9160..a8a5eaa16 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 236465                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 222144                       # Number of bytes of host memory used
+host_inst_rate                                 195987                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201848                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                             1500776387                       # Simulator tick rate (ticks/s)
+host_tick_rate                             1258278911                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000017                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses               82                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.011577                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0             47.418751                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.011577                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses                709                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses              163                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.039064                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0             80.003762                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.039064                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses               2586                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -201,8 +201,8 @@ system.cpu.l2cache.demand_mshr_misses             245                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.003268                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           107.101205                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.003268                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               245                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -244,6 +244,6 @@ system.cpu.num_int_register_writes               1768                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_mem_refs                           717                       # number of memory refs
 system.cpu.num_store_insts                        298                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
index c995df06b..92bf445c8 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -498,7 +498,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/arm/scratch/alisai01/dist/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
index 8947d803a..ca0b775a3 100755
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 19:31:16
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:32:41
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
index bb000db1d..d620e2c6d 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  51112                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 254432                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
-host_tick_rate                               95982480                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 117635                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 212912                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
+host_tick_rate                              220680920                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5739                       # Number of instructions simulated
 sim_seconds                                  0.000011                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect                406                       # Nu
 system.cpu.BPredUnit.condPredicted               1671                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                     2180                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                      242                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches                    945                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events                62                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples        11008                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.521348                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.245214                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0         8442     76.69%     76.69% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1         1229     11.16%     87.85% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2          550      5.00%     92.85% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3          321      2.92%     95.77% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4          184      1.67%     97.44% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5          137      1.24%     98.68% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6           51      0.46%     99.15% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7           32      0.29%     99.44% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8           62      0.56%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total        11008                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                      5739                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                     16                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls               82                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts                  4985                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                      1201                       # Number of loads committed
-system.cpu.commit.COM:membars                      12                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                       2139                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts               317                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                        945                       # Number of branches committed
+system.cpu.commit.bw_lim_events                    62                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts           5739                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls              24                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts            4490                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples        11008                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.521348                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.245214                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         8442     76.69%     76.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1229     11.16%     87.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          550      5.00%     92.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          321      2.92%     95.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          184      1.67%     97.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          137      1.24%     98.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           51      0.46%     99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           32      0.29%     99.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           62      0.56%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        11008                       # Number of insts commited each cycle
+system.cpu.commit.count                          5739                       # Number of instructions committed
+system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls                   82                       # Number of function calls committed.
+system.cpu.commit.int_insts                      4985                       # Number of committed integer instructions.
+system.cpu.commit.loads                          1201                       # Number of loads committed
+system.cpu.commit.membars                          12                       # Number of memory barriers committed
+system.cpu.commit.refs                           2139                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                        5739                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  5739                       # Number of Instructions Simulated
 system.cpu.cpi                               3.765116                       # CPI: Cycles Per Instruction
@@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses              147                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.021822                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0             89.381733                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.021822                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               2731                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 34928.411633                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 31969.387755                       # average overall mshr miss latency
@@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse                 89.381733                       # Cy
 system.cpu.dcache.total_refs                     2304                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles           1281                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred            158                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved           346                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts           12207                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles              7419                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles               2259                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles             770                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts            557                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles             48                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles                  1281                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                   158                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved                  346                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts                  12207                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                     7419                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                      2259                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                    770                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                   557                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles                    48                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -220,8 +220,8 @@ system.cpu.icache.demand_mshr_misses              287                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.071283                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            145.986730                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.071283                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses               1601                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 34737.313433                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 33334.494774                       # average overall mshr miss latency
@@ -244,21 +244,13 @@ system.cpu.icache.total_refs                     1266                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                            9831                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                     1296                       # Number of branches executed
-system.cpu.iew.EXEC:nop                             3                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.372316                       # Inst execution rate
-system.cpu.iew.EXEC:refs                         3091                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                       1139                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                      7215                       # num instructions consuming a value
-system.cpu.iew.WB:count                          7676                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.492862                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                      3556                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.355239                       # insts written-back per cycle
-system.cpu.iew.WB:sent                           7793                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts                  365                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                     1296                       # Number of branches executed
+system.cpu.iew.exec_nop                             3                       # number of nop insts executed
+system.cpu.iew.exec_rate                     0.372316                       # Inst execution rate
+system.cpu.iew.exec_refs                         3091                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                       1139                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                     209                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts                  2372                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                 13                       # Number of dispatched non-speculative instructions
@@ -286,103 +278,93 @@ system.cpu.iew.lsq.thread.0.squashedStores          560                       #
 system.cpu.iew.memOrderViolationEvents             12                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          246                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            119                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                      7215                       # num instructions consuming a value
+system.cpu.iew.wb_count                          7676                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.492862                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                      3556                       # num instructions producing a value
+system.cpu.iew.wb_rate                       0.355239                       # insts written-back per cycle
+system.cpu.iew.wb_sent                           7793                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                    18334                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    5503                       # number of integer regfile writes
 system.cpu.ipc                               0.265596                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.265596                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu            5116     61.06%     61.06% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              6      0.07%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     61.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            3      0.04%     61.16% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     61.16% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     61.16% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     61.16% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead           2082     24.85%     86.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite          1172     13.99%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total             8379                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                   180                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.021482                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu                 2      1.11%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      1.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead              119     66.11%     67.22% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite              59     32.78%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples        11777                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.711472                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.348484                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0          8190     69.54%     69.54% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1          1436     12.19%     81.74% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2           830      7.05%     88.78% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3           533      4.53%     93.31% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4           422      3.58%     96.89% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5           239      2.03%     98.92% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6            96      0.82%     99.74% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7            23      0.20%     99.93% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8             8      0.07%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total        11777                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.387773                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5116     61.06%     61.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    6      0.07%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.04%     61.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.16% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2082     24.85%     86.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1172     13.99%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total                   8379                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                         180                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.021482                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       2      1.11%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    119     66.11%     67.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    59     32.78%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses                   8539                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads              28698                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses         7660                       # Number of integer instruction queue wakeup accesses
@@ -394,6 +376,24 @@ system.cpu.iq.iqSquashedInstsExamined            4207                       # Nu
 system.cpu.iq.iqSquashedInstsIssued                19                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved              1                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined         6956                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples         11777                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.711472                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.348484                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                8190     69.54%     69.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1436     12.19%     81.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 830      7.05%     88.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 533      4.53%     93.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 422      3.58%     96.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 239      2.03%     98.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  96      0.82%     99.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  23      0.20%     99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                   8      0.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           11777                       # Number of insts issued each cycle
+system.cpu.iq.rate                           0.387773                       # Inst issue rate
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
@@ -457,8 +457,8 @@ system.cpu.l2cache.demand_mshr_misses             391                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.005656                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           185.350735                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.005656                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               434                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34368.090452                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.918159                       # average overall mshr miss latency
@@ -489,27 +489,27 @@ system.cpu.misc_regfile_writes                     24                       # nu
 system.cpu.numCycles                            21608                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles              329                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps           4124                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents              48                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles              7684                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents            118                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups          30009                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts           11406                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands         8239                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles               2041                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles             770                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles            193                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps              4112                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups          390                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups        29619                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles          760                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts           16                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts                508                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts           14                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                     329                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps                  4124                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                     48                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                     7684                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents                   118                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenameLookups                 30009                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts                  11406                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands                8239                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                      2041                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                    770                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles                   193                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                     4112                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups               390                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups            29619                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles            760                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts                 16                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                       508                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts             14                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                        21018                       # The number of ROB reads
 system.cpu.rob.rob_writes                       21240                       # The number of ROB writes
 system.cpu.timesIdled                             200                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
+system.cpu.workload.num_syscalls                   13                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
index e51c73913..327106c53 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -66,7 +66,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
index 716a43c24..974d1c8f4 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 19:31:27
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:32:52
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
index 41570e285..675d2d339 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 507203                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 243076                       # Number of bytes of host memory used
+host_inst_rate                                 742627                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204296                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              248530683                       # Simulator tick rate (ticks/s)
+host_tick_rate                              364670846                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5739                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -71,6 +71,6 @@ system.cpu.num_int_register_writes               3802                       # nu
 system.cpu.num_load_insts                        1201                       # Number of load instructions
 system.cpu.num_mem_refs                          2139                       # number of memory refs
 system.cpu.num_store_insts                        938                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
+system.cpu.workload.num_syscalls                   13                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
index ef085e35a..4214b8570 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -169,7 +169,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
index c22e81711..e4f30d324 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 30 2011 17:47:57
-M5 started Mar 30 2011 19:31:37
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing
+M5 compiled Apr 19 2011 12:47:10
+M5 started Apr 19 2011 13:33:02
+M5 executing on maize
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
index 06b8ada90..625b66866 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 270959                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 250792                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1240926423                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 564396                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 212044                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+host_tick_rate                             2575580302                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5682                       # Number of instructions simulated
 sim_seconds                                  0.000026                       # Number of seconds simulated
@@ -54,8 +54,8 @@ system.cpu.dcache.demand_mshr_misses              141                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.020249                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0             82.937979                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.020249                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               2060                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 51234.042553                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 48234.042553                       # average overall mshr miss latency
@@ -130,8 +130,8 @@ system.cpu.icache.demand_mshr_misses              241                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.055921                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            114.525744                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.055921                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses               4614                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 53211.618257                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 50211.618257                       # average overall mshr miss latency
@@ -216,8 +216,8 @@ system.cpu.l2cache.demand_mshr_misses             350                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.004698                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           153.954484                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.004698                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               382                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -259,6 +259,6 @@ system.cpu.num_int_register_writes               3802                       # nu
 system.cpu.num_load_insts                        1201                       # Number of load instructions
 system.cpu.num_mem_refs                          2139                       # number of memory refs
 system.cpu.num_store_insts                        938                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
+system.cpu.workload.num_syscalls                   13                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
index 5ba5eb09f..75367618d 100644
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -23,60 +23,6 @@ type=InOrderCPU
 children=dcache dtb icache itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
-CP0_Config=0
-CP0_Config1=0
-CP0_Config1_C2=false
-CP0_Config1_CA=false
-CP0_Config1_DA=0
-CP0_Config1_DL=0
-CP0_Config1_DS=0
-CP0_Config1_EP=false
-CP0_Config1_FP=false
-CP0_Config1_IA=0
-CP0_Config1_IL=0
-CP0_Config1_IS=0
-CP0_Config1_M=0
-CP0_Config1_MD=false
-CP0_Config1_MMU=0
-CP0_Config1_PC=false
-CP0_Config1_WR=false
-CP0_Config2=0
-CP0_Config2_M=false
-CP0_Config2_SA=0
-CP0_Config2_SL=0
-CP0_Config2_SS=0
-CP0_Config2_SU=0
-CP0_Config2_TA=0
-CP0_Config2_TL=0
-CP0_Config2_TS=0
-CP0_Config2_TU=0
-CP0_Config3=0
-CP0_Config3_DSPP=false
-CP0_Config3_LPA=false
-CP0_Config3_M=false
-CP0_Config3_MT=false
-CP0_Config3_SM=false
-CP0_Config3_SP=false
-CP0_Config3_TL=false
-CP0_Config3_VEIC=false
-CP0_Config3_VInt=false
-CP0_Config_AR=0
-CP0_Config_AT=0
-CP0_Config_BE=0
-CP0_Config_MT=0
-CP0_Config_VI=0
-CP0_EBase_CPUNum=0
-CP0_IntCtl_IPPCI=0
-CP0_IntCtl_IPTI=0
-CP0_PRId=0
-CP0_PRId_CompanyID=0
-CP0_PRId_CompanyOptions=0
-CP0_PRId_ProcessorID=1
-CP0_PRId_Revision=0
-CP0_PerfCtr_M=false
-CP0_PerfCtr_W=false
-CP0_SrsCtl_HSS=0
-CP0_WatchHi_M=false
 RASSize=16
 activity=0
 cachePorts=2
@@ -140,6 +86,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -175,6 +122,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -210,6 +158,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
index 41a76071a..99ccb1cf2 100755
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 18 2011 18:35:15
-M5 revision Unknown
-M5 started Feb 18 2011 18:52:36
-M5 executing on m55-001.pool
+M5 compiled Apr 19 2011 12:18:54
+M5 started Apr 19 2011 12:19:08
+M5 executing on maize
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
index ac0fe4aec..d39207b30 100644
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -1,37 +1,25 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  94112                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 191540                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                              346291258                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 121226                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203988                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
+host_tick_rate                              446414211                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5827                       # Number of instructions simulated
 sim_seconds                                  0.000022                       # Number of seconds simulated
 sim_ticks                                    21538000                       # Number of ticks simulated
-system.cpu.AGEN-Unit.agens                       2404                       # Number of Address Generations
-system.cpu.Branch-Predictor.BTBHitPct       14.054054                       # BTB Hit Percentage
-system.cpu.Branch-Predictor.BTBHits                26                       # Number of BTB hits
-system.cpu.Branch-Predictor.BTBLookups            185                       # Number of BTB lookups
-system.cpu.Branch-Predictor.RASInCorrect           30                       # Number of incorrect RAS predictions.
-system.cpu.Branch-Predictor.condIncorrect          844                       # Number of conditional branches incorrect
-system.cpu.Branch-Predictor.condPredicted          778                       # Number of conditional branches predicted
-system.cpu.Branch-Predictor.lookups              1066                       # Number of BP lookups
-system.cpu.Branch-Predictor.predictedNotTaken          949                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken          117                       # Number of Branches Predicted As Taken (True).
-system.cpu.Branch-Predictor.usedRAS                86                       # Number of times the RAS was used to get a target.
-system.cpu.Execution-Unit.executions             3261                       # Number of Instructions Executed.
-system.cpu.Execution-Unit.mispredictPct     92.139738                       # Percentage of Incorrect Branches Predicts
-system.cpu.Execution-Unit.mispredicted            844                       # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predicted                72                       # Number of Branches Incorrectly Predicted
-system.cpu.Execution-Unit.predictedNotTakenIncorrect          812                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.Execution-Unit.predictedTakenIncorrect           32                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.Mult-Div-Unit.divides                    1                       # Number of Divide Operations Executed
-system.cpu.Mult-Div-Unit.multiplies                 3                       # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses        10004                       # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads          6594                       # Number of Reads from Register File
-system.cpu.RegFile-Manager.regFileWrites         3410                       # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards           1378                       # Number of Registers Read Through Forwarding Logic
 system.cpu.activity                         13.954082                       # Percentage of cycles cpu is active
+system.cpu.agen_unit.agens                       2404                       # Number of Address Generations
+system.cpu.branch_predictor.BTBHitPct       14.054054                       # BTB Hit Percentage
+system.cpu.branch_predictor.BTBHits                26                       # Number of BTB hits
+system.cpu.branch_predictor.BTBLookups            185                       # Number of BTB lookups
+system.cpu.branch_predictor.RASInCorrect           30                       # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.condIncorrect          844                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.condPredicted          778                       # Number of conditional branches predicted
+system.cpu.branch_predictor.lookups              1066                       # Number of BP lookups
+system.cpu.branch_predictor.predictedNotTaken          949                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.branch_predictor.predictedTaken          117                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.usedRAS                86                       # Number of times the RAS was used to get a target.
 system.cpu.comBranches                            916                       # Number of Branches instructions committed
 system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
 system.cpu.comInts                               2155                       # Number of Integer instructions committed
@@ -88,8 +76,8 @@ system.cpu.dcache.demand_mshr_misses              138                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.021745                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0             89.067186                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.021745                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               2089                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 56295.580110                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 53663.043478                       # average overall mshr miss latency
@@ -120,6 +108,12 @@ system.cpu.dtb.read_misses                          0                       # DT
 system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.execution_unit.executions             3261                       # Number of Instructions Executed.
+system.cpu.execution_unit.mispredictPct     92.139738                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.mispredicted            844                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted                72                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predictedNotTakenIncorrect          812                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.predictedTakenIncorrect           32                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.icache.ReadReq_accesses                853                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 55527.559055                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 53156.739812                       # average ReadReq mshr miss latency
@@ -153,8 +147,8 @@ system.cpu.icache.demand_mshr_misses              319                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.070945                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            145.295903                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.070945                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses                853                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55527.559055                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 53156.739812                       # average overall mshr miss latency
@@ -229,8 +223,8 @@ system.cpu.l2cache.demand_mshr_misses             455                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.006169                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           202.151439                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.006169                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               457                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 52370.329670                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 40162.637363                       # average overall mshr miss latency
@@ -252,31 +246,37 @@ system.cpu.l2cache.tagsinuse               202.151439                       # Cy
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.mult_div_unit.divides                    1                       # Number of Divide Operations Executed
+system.cpu.mult_div_unit.multiplies                 3                       # Number of Multipy Operations Executed
 system.cpu.numCycles                            43077                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.regfile_manager.regFileAccesses        10004                       # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.regfile_manager.regFileReads          6594                       # Number of Reads from Register File
+system.cpu.regfile_manager.regFileWrites         3410                       # Number of Writes to Register File
+system.cpu.regfile_manager.regForwards           1378                       # Number of Registers Read Through Forwarding Logic
 system.cpu.runCycles                             6011                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles                   39203                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-0.runCycles                     3874                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization               8.993198                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles                   40159                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles                     2918                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization               6.773916                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles                   40245                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-2.runCycles                     2832                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization               6.574274                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles                   41757                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-3.runCycles                     1320                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization               3.064280                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles                   39874                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-4.runCycles                     3203                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization               7.435522                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage0.idleCycles                    39203                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                      3874                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization                8.993198                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    40159                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                      2918                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization                6.773916                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    40245                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                      2832                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization                6.574274                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    41757                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                      1320                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization                3.064280                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    39874                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      3203                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization                7.435522                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.threadCycles                         10193                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.timesIdled                             427                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
+system.cpu.workload.num_syscalls                    8                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
index f2ed87236..5fbba49b2 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -23,62 +23,10 @@ type=DerivO3CPU
 children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
-CP0_Config=0
-CP0_Config1=0
-CP0_Config1_C2=false
-CP0_Config1_CA=false
-CP0_Config1_DA=0
-CP0_Config1_DL=0
-CP0_Config1_DS=0
-CP0_Config1_EP=false
-CP0_Config1_FP=false
-CP0_Config1_IA=0
-CP0_Config1_IL=0
-CP0_Config1_IS=0
-CP0_Config1_M=0
-CP0_Config1_MD=false
-CP0_Config1_MMU=0
-CP0_Config1_PC=false
-CP0_Config1_WR=false
-CP0_Config2=0
-CP0_Config2_M=false
-CP0_Config2_SA=0
-CP0_Config2_SL=0
-CP0_Config2_SS=0
-CP0_Config2_SU=0
-CP0_Config2_TA=0
-CP0_Config2_TL=0
-CP0_Config2_TS=0
-CP0_Config2_TU=0
-CP0_Config3=0
-CP0_Config3_DSPP=false
-CP0_Config3_LPA=false
-CP0_Config3_M=false
-CP0_Config3_MT=false
-CP0_Config3_SM=false
-CP0_Config3_SP=false
-CP0_Config3_TL=false
-CP0_Config3_VEIC=false
-CP0_Config3_VInt=false
-CP0_Config_AR=0
-CP0_Config_AT=0
-CP0_Config_BE=0
-CP0_Config_MT=0
-CP0_Config_VI=0
-CP0_EBase_CPUNum=0
-CP0_IntCtl_IPPCI=0
-CP0_IntCtl_IPTI=0
-CP0_PRId=0
-CP0_PRId_CompanyID=0
-CP0_PRId_CompanyOptions=0
-CP0_PRId_ProcessorID=1
-CP0_PRId_Revision=0
-CP0_PerfCtr_M=false
-CP0_PerfCtr_W=false
-CP0_SrsCtl_HSS=0
-CP0_WatchHi_M=false
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
index 27c18cbea..5852e6d08 100755
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 23:01:20
-M5 started Mar 17 2011 23:01:33
-M5 executing on zizzer
+M5 compiled Apr 19 2011 12:18:54
+M5 started Apr 19 2011 12:19:08
+M5 executing on maize
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
index 81b1a48e3..cdb83d87c 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  71769                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206840                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
-host_tick_rate                              176990793                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 109180                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204504                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
+host_tick_rate                              269299917                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5169                       # Number of instructions simulated
 sim_seconds                                  0.000013                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect                380                       # Nu
 system.cpu.BPredUnit.condPredicted               1180                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                     1716                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                      206                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches                    916                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events                77                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples        12220                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.476759                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.219720                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0         9742     79.72%     79.72% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1          995      8.14%     87.86% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2          703      5.75%     93.62% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3          335      2.74%     96.36% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4          169      1.38%     97.74% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5           98      0.80%     98.54% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6           69      0.56%     99.11% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7           32      0.26%     99.37% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8           77      0.63%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total        12220                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                      5826                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                      2                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls               87                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts                  5124                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                      1164                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                       2089                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts               339                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                        916                       # Number of branches committed
+system.cpu.commit.bw_lim_events                    77                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts           5826                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls              10                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts            3363                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples        12220                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.476759                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.219720                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         9742     79.72%     79.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          995      8.14%     87.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          703      5.75%     93.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          335      2.74%     96.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          169      1.38%     97.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           98      0.80%     98.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           69      0.56%     99.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           32      0.26%     99.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           77      0.63%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12220                       # Number of insts commited each cycle
+system.cpu.commit.count                          5826                       # Number of instructions committed
+system.cpu.commit.fp_insts                          2                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls                   87                       # Number of function calls committed.
+system.cpu.commit.int_insts                      5124                       # Number of committed integer instructions.
+system.cpu.commit.loads                          1164                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                           2089                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                        5169                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  5169                       # Number of Instructions Simulated
 system.cpu.cpi                               4.950281                       # CPI: Cycles Per Instruction
@@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses              141                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.022393                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0             91.720291                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.022393                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               2723                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 34710.970464                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 36035.460993                       # average overall mshr miss latency
@@ -119,15 +119,15 @@ system.cpu.dcache.tagsinuse                 91.720291                       # Cy
 system.cpu.dcache.total_refs                     2249                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles            742                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred             42                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved            89                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts           10279                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles              8753                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles               2688                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles             636                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts            153                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles             37                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles                   742                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                    42                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved                   89                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts                  10279                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                     8753                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                      2688                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                    636                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                   153                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles                    37                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
@@ -200,8 +200,8 @@ system.cpu.icache.demand_mshr_misses              329                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.077515                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            158.750706                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.077515                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses               1531                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 36303.482587                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 35016.717325                       # average overall mshr miss latency
@@ -224,21 +224,13 @@ system.cpu.icache.total_refs                     1129                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                           12732                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                     1171                       # Number of branches executed
-system.cpu.iew.EXEC:nop                          1220                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.276575                       # Inst execution rate
-system.cpu.iew.EXEC:refs                         2915                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                       1038                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                      3566                       # num instructions consuming a value
-system.cpu.iew.WB:count                          6732                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.716489                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                      2555                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.263092                       # insts written-back per cycle
-system.cpu.iew.WB:sent                           6801                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts                  377                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                     1171                       # Number of branches executed
+system.cpu.iew.exec_nop                          1220                       # number of nop insts executed
+system.cpu.iew.exec_rate                     0.276575                       # Inst execution rate
+system.cpu.iew.exec_refs                         2915                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                       1038                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                     165                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts                  2109                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                 10                       # Number of dispatched non-speculative instructions
@@ -266,103 +258,93 @@ system.cpu.iew.lsq.thread.0.squashedStores          202                       #
 system.cpu.iew.memOrderViolationEvents              5                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          259                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            118                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                      3566                       # num instructions consuming a value
+system.cpu.iew.wb_count                          6732                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.716489                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                      2555                       # num instructions producing a value
+system.cpu.iew.wb_rate                       0.263092                       # insts written-back per cycle
+system.cpu.iew.wb_sent                           6801                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                     9689                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    4703                       # number of integer regfile writes
 system.cpu.ipc                               0.202009                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.202009                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu            4286     58.77%     58.77% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              4      0.05%     58.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               2      0.03%     58.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             2      0.03%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     58.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead           1952     26.77%     85.64% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite          1047     14.36%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total             7293                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                   143                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.019608                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu                 7      4.90%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      4.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead               84     58.74%     63.64% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite              52     36.36%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples        12856                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.567284                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.210668                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0          9551     74.29%     74.29% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1          1436     11.17%     85.46% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2           786      6.11%     91.58% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3           503      3.91%     95.49% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4           300      2.33%     97.82% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5           160      1.24%     99.07% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6            76      0.59%     99.66% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7            32      0.25%     99.91% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8            12      0.09%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total        12856                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.285016                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  4286     58.77%     58.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    4      0.05%     58.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     2      0.03%     58.85% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.03%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     58.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1952     26.77%     85.64% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1047     14.36%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total                   7293                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                       2                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                   4                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses            2                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                  2                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                         143                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.019608                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       7      4.90%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     84     58.74%     63.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    52     36.36%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses                   7434                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads              27612                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses         6730                       # Number of integer instruction queue wakeup accesses
@@ -373,6 +355,24 @@ system.cpu.iq.iqNonSpecInstsAdded                  10                       # Nu
 system.cpu.iq.iqSquashedInstsExamined            2360                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedInstsIssued                31                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedOperandsExamined         1480                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples         12856                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.567284                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.210668                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                9551     74.29%     74.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1436     11.17%     85.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 786      6.11%     91.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 503      3.91%     95.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 300      2.33%     97.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 160      1.24%     99.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  76      0.59%     99.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  32      0.25%     99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  12      0.09%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           12856                       # Number of insts issued each cycle
+system.cpu.iq.rate                           0.285016                       # Inst issue rate
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
@@ -423,8 +423,8 @@ system.cpu.l2cache.demand_mshr_misses             467                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.006657                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           218.141494                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.006657                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               470                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34357.601713                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31169.164882                       # average overall mshr miss latency
@@ -454,26 +454,26 @@ system.cpu.misc_regfile_reads                     134                       # nu
 system.cpu.numCycles                            25588                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles              238                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps           3410                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles              8904                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents             71                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups          11929                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts            9880                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands         6029                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles               2577                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles             636                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles             81                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps              2619                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups            5                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups        11924                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles          420                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts           15                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts                193                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts           10                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                     238                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps                  3410                       # Number of HB maps that are committed
+system.cpu.rename.IdleCycles                     8904                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents                    71                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenameLookups                 11929                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts                   9880                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands                6029                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                      2577                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                    636                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles                    81                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                     2619                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups                 5                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups            11924                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles            420                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts                 15                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                       193                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts             10                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                        21319                       # The number of ROB reads
 system.cpu.rob.rob_writes                       19020                       # The number of ROB writes
 system.cpu.timesIdled                             260                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
+system.cpu.workload.num_syscalls                    8                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index 8a615b31d..9c80192e1 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -21,60 +21,6 @@ work_item_id=-1
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb itb tracer workload
-CP0_Config=0
-CP0_Config1=0
-CP0_Config1_C2=false
-CP0_Config1_CA=false
-CP0_Config1_DA=0
-CP0_Config1_DL=0
-CP0_Config1_DS=0
-CP0_Config1_EP=false
-CP0_Config1_FP=false
-CP0_Config1_IA=0
-CP0_Config1_IL=0
-CP0_Config1_IS=0
-CP0_Config1_M=0
-CP0_Config1_MD=false
-CP0_Config1_MMU=0
-CP0_Config1_PC=false
-CP0_Config1_WR=false
-CP0_Config2=0
-CP0_Config2_M=false
-CP0_Config2_SA=0
-CP0_Config2_SL=0
-CP0_Config2_SS=0
-CP0_Config2_SU=0
-CP0_Config2_TA=0
-CP0_Config2_TL=0
-CP0_Config2_TS=0
-CP0_Config2_TU=0
-CP0_Config3=0
-CP0_Config3_DSPP=false
-CP0_Config3_LPA=false
-CP0_Config3_M=false
-CP0_Config3_MT=false
-CP0_Config3_SM=false
-CP0_Config3_SP=false
-CP0_Config3_TL=false
-CP0_Config3_VEIC=false
-CP0_Config3_VInt=false
-CP0_Config_AR=0
-CP0_Config_AT=0
-CP0_Config_BE=0
-CP0_Config_MT=0
-CP0_Config_VI=0
-CP0_EBase_CPUNum=0
-CP0_IntCtl_IPPCI=0
-CP0_IntCtl_IPTI=0
-CP0_PRId=0
-CP0_PRId_CompanyID=0
-CP0_PRId_CompanyOptions=0
-CP0_PRId_ProcessorID=1
-CP0_PRId_Revision=0
-CP0_PerfCtr_M=false
-CP0_PerfCtr_W=false
-CP0_SrsCtl_HSS=0
-CP0_WatchHi_M=false
 checker=Null
 clock=500
 cpu_id=0
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
index 931c89646..8a1b8f67f 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:55:51
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:01
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:18:54
+M5 started Apr 19 2011 12:18:58
+M5 executing on maize
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
index d5304c4b4..4243ca997 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 106820                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 216064                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
-host_tick_rate                               53148750                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 798153                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195780                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+host_tick_rate                              390049435                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5827                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -47,6 +47,6 @@ system.cpu.num_int_register_writes               3409                       # nu
 system.cpu.num_load_insts                        1164                       # Number of load instructions
 system.cpu.num_mem_refs                          2090                       # number of memory refs
 system.cpu.num_store_insts                        926                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
+system.cpu.workload.num_syscalls                    8                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index 15d83d7b2..39758d41d 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -21,60 +21,6 @@ work_item_id=-1
 [system.cpu]
 type=TimingSimpleCPU
 children=dtb itb tracer workload
-CP0_Config=0
-CP0_Config1=0
-CP0_Config1_C2=false
-CP0_Config1_CA=false
-CP0_Config1_DA=0
-CP0_Config1_DL=0
-CP0_Config1_DS=0
-CP0_Config1_EP=false
-CP0_Config1_FP=false
-CP0_Config1_IA=0
-CP0_Config1_IL=0
-CP0_Config1_IS=0
-CP0_Config1_M=0
-CP0_Config1_MD=false
-CP0_Config1_MMU=0
-CP0_Config1_PC=false
-CP0_Config1_WR=false
-CP0_Config2=0
-CP0_Config2_M=false
-CP0_Config2_SA=0
-CP0_Config2_SL=0
-CP0_Config2_SS=0
-CP0_Config2_SU=0
-CP0_Config2_TA=0
-CP0_Config2_TL=0
-CP0_Config2_TS=0
-CP0_Config2_TU=0
-CP0_Config3=0
-CP0_Config3_DSPP=false
-CP0_Config3_LPA=false
-CP0_Config3_M=false
-CP0_Config3_MT=false
-CP0_Config3_SM=false
-CP0_Config3_SP=false
-CP0_Config3_TL=false
-CP0_Config3_VEIC=false
-CP0_Config3_VInt=false
-CP0_Config_AR=0
-CP0_Config_AT=0
-CP0_Config_BE=0
-CP0_Config_MT=0
-CP0_Config_VI=0
-CP0_EBase_CPUNum=0
-CP0_IntCtl_IPPCI=0
-CP0_IntCtl_IPTI=0
-CP0_PRId=0
-CP0_PRId_CompanyID=0
-CP0_PRId_CompanyOptions=0
-CP0_PRId_ProcessorID=1
-CP0_PRId_Revision=0
-CP0_PerfCtr_M=false
-CP0_PerfCtr_W=false
-CP0_SrsCtl_HSS=0
-CP0_WatchHi_M=false
 checker=Null
 clock=1
 cpu_id=0
@@ -214,6 +160,7 @@ deadlock_threshold=500000
 icache=system.ruby.cpu_ruby_ports.dcache
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
index 4a1640a47..e7dec82e9 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:55:51
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:00
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:18:54
+M5 started Apr 19 2011 12:18:57
+M5 executing on maize
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index 0a46cd560..12dfdb011 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  24226                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 234168                       # Number of bytes of host memory used
-host_seconds                                     0.24                       # Real time elapsed on the host
-host_tick_rate                                1216878                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  81519                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213976                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                                4090793                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        5827                       # Number of instructions simulated
 sim_seconds                                  0.000293                       # Number of seconds simulated
@@ -47,6 +47,6 @@ system.cpu.num_int_register_writes               3409                       # nu
 system.cpu.num_load_insts                        1164                       # Number of load instructions
 system.cpu.num_mem_refs                          2090                       # number of memory refs
 system.cpu.num_store_insts                        926                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
+system.cpu.workload.num_syscalls                    8                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index 01d13de53..00709865b 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -21,60 +21,6 @@ work_item_id=-1
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache itb l2cache toL2Bus tracer workload
-CP0_Config=0
-CP0_Config1=0
-CP0_Config1_C2=false
-CP0_Config1_CA=false
-CP0_Config1_DA=0
-CP0_Config1_DL=0
-CP0_Config1_DS=0
-CP0_Config1_EP=false
-CP0_Config1_FP=false
-CP0_Config1_IA=0
-CP0_Config1_IL=0
-CP0_Config1_IS=0
-CP0_Config1_M=0
-CP0_Config1_MD=false
-CP0_Config1_MMU=0
-CP0_Config1_PC=false
-CP0_Config1_WR=false
-CP0_Config2=0
-CP0_Config2_M=false
-CP0_Config2_SA=0
-CP0_Config2_SL=0
-CP0_Config2_SS=0
-CP0_Config2_SU=0
-CP0_Config2_TA=0
-CP0_Config2_TL=0
-CP0_Config2_TS=0
-CP0_Config2_TU=0
-CP0_Config3=0
-CP0_Config3_DSPP=false
-CP0_Config3_LPA=false
-CP0_Config3_M=false
-CP0_Config3_MT=false
-CP0_Config3_SM=false
-CP0_Config3_SP=false
-CP0_Config3_TL=false
-CP0_Config3_VEIC=false
-CP0_Config3_VInt=false
-CP0_Config_AR=0
-CP0_Config_AT=0
-CP0_Config_BE=0
-CP0_Config_MT=0
-CP0_Config_VI=0
-CP0_EBase_CPUNum=0
-CP0_IntCtl_IPPCI=0
-CP0_IntCtl_IPTI=0
-CP0_PRId=0
-CP0_PRId_CompanyID=0
-CP0_PRId_CompanyOptions=0
-CP0_PRId_ProcessorID=1
-CP0_PRId_Revision=0
-CP0_PerfCtr_M=false
-CP0_PerfCtr_W=false
-CP0_SrsCtl_HSS=0
-CP0_WatchHi_M=false
 checker=Null
 clock=500
 cpu_id=0
@@ -105,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -140,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -175,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
index 4a897b2a2..3a1be45f5 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:55:51
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:56:00
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:18:54
+M5 started Apr 19 2011 12:18:57
+M5 executing on maize
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
index 27b53a7ab..ec5ae032f 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 344481                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 223780                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1868884758                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 524923                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203516                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+host_tick_rate                             2843944401                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5827                       # Number of instructions simulated
 sim_seconds                                  0.000032                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses              138                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.021352                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0             87.458397                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.021352                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               2089                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses              303                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.064694                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            132.493866                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.064694                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses               5829                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55722.772277                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277                       # average overall mshr miss latency
@@ -188,8 +188,8 @@ system.cpu.l2cache.demand_mshr_misses             439                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.005739                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           188.045319                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.005739                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               441                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -231,6 +231,6 @@ system.cpu.num_int_register_writes               3409                       # nu
 system.cpu.num_load_insts                        1164                       # Number of load instructions
 system.cpu.num_mem_refs                          2090                       # number of memory refs
 system.cpu.num_store_insts                        926                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
+system.cpu.workload.num_syscalls                    8                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
index 8890f2cb3..228222f47 100644
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
index 9c2f3b607..e5517f525 100755
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
@@ -1,5 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: allowing mmap of file @ fd 17488232. This will break if not /dev/zero.
+warn: allowing mmap of file @ fd 32051064. This will break if not /dev/zero.
 For more information see: http://www.m5sim.org/warn/3a2134f6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout
index db07f12a1..5a9dfcd0e 100755
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 18 2011 02:41:27
-M5 started Mar 18 2011 02:41:29
-M5 executing on zizzer
+M5 compiled Apr 19 2011 12:19:26
+M5 started Apr 19 2011 12:19:32
+M5 executing on maize
 command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
index 6e32b0c6c..7ecc0010b 100644
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  15140                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204452                       # Number of bytes of host memory used
-host_seconds                                     0.38                       # Real time elapsed on the host
-host_tick_rate                               30510356                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 146379                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202304                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
+host_tick_rate                              293581871                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5800                       # Number of instructions simulated
 sim_seconds                                  0.000012                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect                388                       # Nu
 system.cpu.BPredUnit.condPredicted               1734                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                     2075                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                      187                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches                   1038                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events                42                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples        10395                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.557961                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.275569                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0         7869     75.70%     75.70% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1         1103     10.61%     86.31% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2          649      6.24%     92.55% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3          257      2.47%     95.03% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4          223      2.15%     97.17% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5          132      1.27%     98.44% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6          100      0.96%     99.40% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7           20      0.19%     99.60% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8           42      0.40%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total        10395                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                      5800                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                     22                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls              103                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts                  5706                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                       962                       # Number of loads committed
-system.cpu.commit.COM:membars                       7                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                       2008                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts               240                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                       1038                       # Number of branches committed
+system.cpu.commit.bw_lim_events                    42                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts           5800                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls              16                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts            3301                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples        10395                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.557961                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.275569                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         7869     75.70%     75.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1103     10.61%     86.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          649      6.24%     92.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          257      2.47%     95.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          223      2.15%     97.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          132      1.27%     98.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          100      0.96%     99.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           20      0.19%     99.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           42      0.40%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        10395                       # Number of insts commited each cycle
+system.cpu.commit.count                          5800                       # Number of instructions committed
+system.cpu.commit.fp_insts                         22                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls                  103                       # Number of function calls committed.
+system.cpu.commit.int_insts                      5706                       # Number of committed integer instructions.
+system.cpu.commit.loads                           962                       # Number of loads committed
+system.cpu.commit.membars                           7                       # Number of memory barriers committed
+system.cpu.commit.refs                           2008                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                        5800                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  5800                       # Number of Instructions Simulated
 system.cpu.cpi                               4.032931                       # CPI: Cycles Per Instruction
@@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses              104                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.016225                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0             66.459259                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.016225                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               2477                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 33810.606061                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 35307.692308                       # average overall mshr miss latency
@@ -119,15 +119,15 @@ system.cpu.dcache.tagsinuse                 66.459259                       # Cy
 system.cpu.dcache.total_refs                     2081                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles            887                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred            151                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved           265                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts           10261                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles              7524                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles               1914                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles             549                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts            421                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles             70                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles                   887                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                   151                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved                  265                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts                  10261                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                     7524                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                      1914                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                    549                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                   421                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles                    70                       # Number of cycles decode is unblocking
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
@@ -200,8 +200,8 @@ system.cpu.icache.demand_mshr_misses              333                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.078664                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            161.104076                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.078664                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses               1460                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 36594.488189                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 34774.774775                       # average overall mshr miss latency
@@ -224,21 +224,13 @@ system.cpu.icache.total_refs                     1079                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                           12447                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                     1262                       # Number of branches executed
-system.cpu.iew.EXEC:nop                             0                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.332008                       # Inst execution rate
-system.cpu.iew.EXEC:refs                         2790                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                       1305                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                      5916                       # num instructions consuming a value
-system.cpu.iew.WB:count                          7563                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.645030                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                      3816                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.323329                       # insts written-back per cycle
-system.cpu.iew.WB:sent                           7623                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts                  279                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                     1262                       # Number of branches executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_rate                     0.332008                       # Inst execution rate
+system.cpu.iew.exec_refs                         2790                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                       1305                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                     130                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts                  1666                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                 14                       # Number of dispatched non-speculative instructions
@@ -266,103 +258,93 @@ system.cpu.iew.lsq.thread.0.squashedStores          390                       #
 system.cpu.iew.memOrderViolationEvents             13                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          202                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect             77                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                      5916                       # num instructions consuming a value
+system.cpu.iew.wb_count                          7563                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.645030                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                      3816                       # num instructions producing a value
+system.cpu.iew.wb_rate                       0.323329                       # insts written-back per cycle
+system.cpu.iew.wb_sent                           7623                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                    12407                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    6585                       # number of integer regfile writes
 system.cpu.ipc                               0.247959                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.247959                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu            5116     63.51%     63.51% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              0      0.00%     63.51% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     63.51% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             2      0.02%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     63.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead           1580     19.62%     83.15% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite          1357     16.85%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total             8055                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                   152                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.018870                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu                11      7.24%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      7.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead               72     47.37%     54.61% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite              69     45.39%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples        10944                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.736020                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.423307                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0          7700     70.36%     70.36% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1          1176     10.75%     81.10% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2           793      7.25%     88.35% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3           485      4.43%     92.78% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4           365      3.34%     96.12% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5           233      2.13%     98.25% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6           138      1.26%     99.51% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7            47      0.43%     99.94% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8             7      0.06%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total        10944                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.344363                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5116     63.51%     63.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     63.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     63.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     63.54% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1580     19.62%     83.15% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1357     16.85%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total                   8055                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                      31                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                  59                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           27                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                 36                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                         152                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.018870                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      11      7.24%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     72     47.37%     54.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    69     45.39%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses                   8176                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads              27162                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses         7536                       # Number of integer instruction queue wakeup accesses
@@ -374,6 +356,24 @@ system.cpu.iq.iqSquashedInstsExamined            2924                       # Nu
 system.cpu.iq.iqSquashedInstsIssued                15                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved              6                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined         2633                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples         10944                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.736020                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.423307                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                7700     70.36%     70.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1176     10.75%     81.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 793      7.25%     88.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 485      4.43%     92.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 365      3.34%     96.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 233      2.13%     98.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 138      1.26%     99.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  47      0.43%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                   7      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           10944                       # Number of insts issued each cycle
+system.cpu.iq.rate                           0.344363                       # Inst issue rate
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
@@ -424,8 +424,8 @@ system.cpu.l2cache.demand_mshr_misses             429                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.005859                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           191.979751                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.005859                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               437                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34391.608392                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31216.783217                       # average overall mshr miss latency
@@ -454,27 +454,27 @@ system.cpu.memDep0.insertedStores                1436                       # Nu
 system.cpu.numCycles                            23391                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles              314                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps           5007                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents               7                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles              7703                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents            194                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups          16001                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts            9789                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands         8584                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles               1797                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles             549                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles            244                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps              3577                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups           55                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups        15946                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles          337                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts           22                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts                471                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts           22                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                     314                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps                  5007                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                      7                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                     7703                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents                   194                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenameLookups                 16001                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts                   9789                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands                8584                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                      1797                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                    549                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles                   244                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                     3577                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups                55                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups            15946                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles            337                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts                 22                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                       471                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts             22                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                        19454                       # The number of ROB reads
 system.cpu.rob.rob_writes                       18753                       # The number of ROB writes
 system.cpu.timesIdled                             229                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls               9                       # Number of system calls
+system.cpu.workload.num_syscalls                    9                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
index 4e7b25b97..c3d9ac55b 100755
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
@@ -1,5 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: allowing mmap of file @ fd 39589752. This will break if not /dev/zero.
+warn: allowing mmap of file @ fd 30329336. This will break if not /dev/zero.
 For more information see: http://www.m5sim.org/warn/3a2134f6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
index dea57bc4d..86b3ce749 100755
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:06:34
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:06:40
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:26
+M5 started Apr 19 2011 12:19:32
+M5 executing on maize
 command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
index 1731c3473..c1d1657bb 100644
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 628022                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214048                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              304927994                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 259061                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 193868                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                              128464915                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5801                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -47,6 +47,6 @@ system.cpu.num_int_register_writes               5005                       # nu
 system.cpu.num_load_insts                         962                       # Number of load instructions
 system.cpu.num_mem_refs                          2008                       # number of memory refs
 system.cpu.num_store_insts                       1046                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls               9                       # Number of system calls
+system.cpu.workload.num_syscalls                    9                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
index 38db96c18..a3abc632d 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:14:08
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:20:06
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index 2caa46c35..cfb190c91 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  96674                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215848                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                               48656953                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   4684                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195500                       # Number of bytes of host memory used
+host_seconds                                     1.14                       # Real time elapsed on the host
+host_tick_rate                                2368799                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes               4859                       # nu
 system.cpu.num_load_insts                         724                       # Number of load instructions
 system.cpu.num_mem_refs                          1402                       # number of memory refs
 system.cpu.num_store_insts                        678                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
+system.cpu.workload.num_syscalls                   11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index 6590fce9b..aacea45cb 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -160,6 +160,7 @@ deadlock_threshold=500000
 icache=system.ruby.cpu_ruby_ports.dcache
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
index b11f8c789..e4482bc0d 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/07/2011 02:13:39
+Real time: Apr/19/2011 12:21:28
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.34
-Virtual_time_in_minutes: 0.00566667
-Virtual_time_in_hours:   9.44444e-05
-Virtual_time_in_days:    3.93519e-06
+Virtual_time_in_seconds: 0.16
+Virtual_time_in_minutes: 0.00266667
+Virtual_time_in_hours:   4.44444e-05
+Virtual_time_in_days:    1.85185e-06
 
 Ruby_current_time: 253364
 Ruby_start_time: 0
 Ruby_cycles: 253364
 
-mbytes_resident: 37.8555
-mbytes_total: 228.355
-resident_ratio: 0.165791
+mbytes_resident: 38.7109
+mbytes_total: 208.668
+resident_ratio: 0.185533
 
 ruby_cycles_executed: [ 253365 ]
 
@@ -70,9 +70,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6773 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 371 count: 6772 average: 36.4135 | standard deviation: 69.5949 | 0 5483 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_IFETCH: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_IFETCH: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_L1Cache: [binsize: 1 max: 3 count: 5483 average:     3 | standard deviation: 0 | 0 0 0 5483 ]
 miss_latency_Directory: [binsize: 2 max: 371 count: 1289 average: 178.544 | standard deviation: 22.1923 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -85,12 +85,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average:
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average:   159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 imcomplete_dir_Times: 1288
-miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 4668 average:     3 | standard deviation: 0 | 0 0 0 4668 ]
-miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 715 average: 178.824 | standard deviation: 21.9931 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 321 average:     3 | standard deviation: 0 | 0 0 0 321 ]
 miss_latency_LD_Directory: [binsize: 2 max: 285 count: 395 average: 176.514 | standard deviation: 18.6332 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 494 average:     3 | standard deviation: 0 | 0 0 0 494 ]
 miss_latency_ST_Directory: [binsize: 2 max: 371 count: 179 average: 181.905 | standard deviation: 28.882 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 4668 average:     3 | standard deviation: 0 | 0 0 0 4668 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 715 average: 178.824 | standard deviation: 21.9931 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -122,10 +122,10 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11225
-page_faults: 3
+page_reclaims: 10204
+page_faults: 0
 swaps: 0
-block_inputs: 1280
+block_inputs: 0
 block_outputs: 64
 
 Network Stats
@@ -181,7 +181,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache
   system.ruby.cpu_ruby_ports.dcache_request_type_ST:   13.8867%
   system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   55.4694%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   1289    100%
+  system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor:   1289    100%
 
  --- L1Cache ---
  - Event Counts -
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index c97aaa4c9..facf1db54 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:13:38
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:21:28
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 5961a0ac8..11151259c 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  26190                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 233840                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
-host_tick_rate                                1241276                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  87677                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 213680                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                                4150530                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
 sim_seconds                                  0.000253                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes               4858                       # nu
 system.cpu.num_load_insts                         724                       # Number of load instructions
 system.cpu.num_mem_refs                          1402                       # number of memory refs
 system.cpu.num_store_insts                        678                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
+system.cpu.workload.num_syscalls                   11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index d416eae87..87bc655de 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
index 1b1015662..3cc40bf72 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:14:00
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:21:23
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
index d21947f29..98edbe0f3 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  87383                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 223480                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                              459485360                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 539149                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203248                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+host_tick_rate                             2800713812                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
 sim_seconds                                  0.000028                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses              135                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.020036                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0             82.065697                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.020036                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               1389                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 55688.888889                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 52688.888889                       # average overall mshr miss latency
@@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses              257                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.057117                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            116.975932                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.057117                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses               5384                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55673.151751                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751                       # average overall mshr miss latency
@@ -170,8 +170,8 @@ system.cpu.l2cache.demand_mshr_misses             389                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.004337                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           142.102892                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.004337                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               392                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -213,6 +213,6 @@ system.cpu.num_int_register_writes               4858                       # nu
 system.cpu.num_load_insts                         724                       # Number of load instructions
 system.cpu.num_mem_refs                          1402                       # number of memory refs
 system.cpu.num_store_insts                        678                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
+system.cpu.workload.num_syscalls                   11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
index 7618192c8..cd8df9d09 100644
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
index 18b684d12..79df40ec6 100755
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 18 2011 20:12:06
-M5 started Mar 18 2011 20:30:23
-M5 executing on zizzer
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:38:12
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
index 738321b57..177a37ea2 100644
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  85944                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211192                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
-host_tick_rate                               99394076                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 147922                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 208856                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                              171003814                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        9809                       # Number of instructions simulated
 sim_seconds                                  0.000011                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect                485                       # Nu
 system.cpu.BPredUnit.condPredicted               2758                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                     2758                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches                   1214                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events               141                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples        11809                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.830638                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.597584                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0         8189     69.35%     69.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1         1225     10.37%     79.72% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2          582      4.93%     84.65% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3          958      8.11%     92.76% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4          396      3.35%     96.11% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5          132      1.12%     97.23% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6          128      1.08%     98.31% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7           58      0.49%     98.81% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8          141      1.19%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total        11809                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                      9809                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                      0                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts                  9714                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                      1056                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                       1990                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts               485                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                       1214                       # Number of branches committed
+system.cpu.commit.bw_lim_events                   141                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts           9809                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls              13                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts            9222                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples        11809                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.830638                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.597584                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         8189     69.35%     69.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1225     10.37%     79.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          582      4.93%     84.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          958      8.11%     92.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          396      3.35%     96.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          132      1.12%     97.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          128      1.08%     98.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           58      0.49%     98.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          141      1.19%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        11809                       # Number of insts commited each cycle
+system.cpu.commit.count                          9809                       # Number of instructions committed
+system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.int_insts                      9714                       # Number of committed integer instructions.
+system.cpu.commit.loads                          1056                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                           1990                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                        9809                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  9809                       # Number of Instructions Simulated
 system.cpu.cpi                               2.318585                       # CPI: Cycles Per Instruction
@@ -96,8 +96,8 @@ system.cpu.dcache.demand_mshr_misses              144                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.020965                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0             85.873455                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.020965                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               2465                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 34196.009390                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 35600.694444                       # average overall mshr miss latency
@@ -119,12 +119,12 @@ system.cpu.dcache.tagsinuse                 85.873455                       # Cy
 system.cpu.dcache.total_refs                     2039                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles           1369                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts           22088                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles              7085                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles               3278                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles            1477                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles             77                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles                  1369                       # Number of cycles decode is blocked
+system.cpu.decode.DecodedInsts                  22088                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                     7085                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                      3278                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                   1477                       # Number of cycles decode is squashing
+system.cpu.decode.UnblockCycles                    77                       # Number of cycles decode is unblocking
 system.cpu.fetch.Branches                        2758                       # Number of branches that fetch encountered
 system.cpu.fetch.CacheLines                      1703                       # Number of cache lines fetched
 system.cpu.fetch.Cycles                          3590                       # Number of cycles fetch has run and was not squashing or blocked
@@ -187,8 +187,8 @@ system.cpu.icache.demand_mshr_misses              295                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.070743                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            144.881554                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.070743                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses               1703                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 36577.562327                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        35100                       # average overall mshr miss latency
@@ -211,21 +211,13 @@ system.cpu.icache.total_refs                     1342                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                            9457                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                     1545                       # Number of branches executed
-system.cpu.iew.EXEC:nop                             0                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.675461                       # Inst execution rate
-system.cpu.iew.EXEC:refs                         2952                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                       1295                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                     14668                       # num instructions consuming a value
-system.cpu.iew.WB:count                         15056                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.677734                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                      9941                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.662006                       # insts written-back per cycle
-system.cpu.iew.WB:sent                          15179                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts                  566                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                     1545                       # Number of branches executed
+system.cpu.iew.exec_nop                             0                       # number of nop insts executed
+system.cpu.iew.exec_rate                     0.675461                       # Inst execution rate
+system.cpu.iew.exec_refs                         2952                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                       1295                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                     187                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts                  2082                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                 33                       # Number of dispatched non-speculative instructions
@@ -253,103 +245,93 @@ system.cpu.iew.lsq.thread.0.squashedStores          683                       #
 system.cpu.iew.memOrderViolationEvents             14                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          497                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect             69                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                     14668                       # num instructions consuming a value
+system.cpu.iew.wb_count                         15056                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.677734                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                      9941                       # num instructions producing a value
+system.cpu.iew.wb_rate                       0.662006                       # insts written-back per cycle
+system.cpu.iew.wb_sent                          15179                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                    22959                       # number of integer regfile reads
 system.cpu.int_regfile_writes                   13993                       # number of integer regfile writes
 system.cpu.ipc                               0.431298                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.431298                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            4      0.02%      0.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu           12893     80.31%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     80.33% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead           1771     11.03%     91.36% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite          1387      8.64%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total            16055                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                   147                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.009156                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu               101     68.71%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     68.71% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead               27     18.37%     87.07% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite              19     12.93%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples        13286                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.208415                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.917020                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0          8201     61.73%     61.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1          1290      9.71%     71.44% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2           986      7.42%     78.86% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3           726      5.46%     84.32% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4           782      5.89%     90.21% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5           580      4.37%     94.57% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6           507      3.82%     98.39% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7           167      1.26%     99.65% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8            47      0.35%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total        13286                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.705931                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 4      0.02%      0.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 12893     80.31%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1771     11.03%     91.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1387      8.64%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total                  16055                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                       5                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                   9                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                         147                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009156                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     101     68.71%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     68.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     27     18.37%     87.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    19     12.93%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses                  16193                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads              45588                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses        15052                       # Number of integer instruction queue wakeup accesses
@@ -361,6 +343,24 @@ system.cpu.iq.iqSquashedInstsExamined            8610                       # Nu
 system.cpu.iq.iqSquashedInstsIssued                54                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             20                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined        10851                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples         13286                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.208415                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.917020                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                8201     61.73%     61.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1290      9.71%     71.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 986      7.42%     78.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 726      5.46%     84.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 782      5.89%     90.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 580      4.37%     94.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 507      3.82%     98.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 167      1.26%     99.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  47      0.35%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13286                       # Number of insts issued each cycle
+system.cpu.iq.rate                           0.705931                       # Inst issue rate
 system.cpu.l2cache.ReadExReq_accesses              77                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34603.896104                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31396.103896                       # average ReadExReq mshr miss latency
@@ -402,8 +402,8 @@ system.cpu.l2cache.demand_mshr_misses             437                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.005438                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           178.188786                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.005438                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               439                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34307.780320                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.974828                       # average overall mshr miss latency
@@ -433,28 +433,28 @@ system.cpu.misc_regfile_reads                    6812                       # nu
 system.cpu.numCycles                            22743                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles              565                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps           9368                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents              52                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles              7327                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents            248                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents              3                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups          44292                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts           21008                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands        19746                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles               3097                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles            1477                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles            380                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps             10378                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups           16                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups        44276                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles          440                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts           32                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts               1483                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts           31                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                     565                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps                  9368                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                     52                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                     7327                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents                   248                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups                 44292                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts                  21008                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands               19746                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                      3097                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                   1477                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles                   380                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                    10378                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups            44276                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles            440                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts                 32                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                      1483                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts             31                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                        30699                       # The number of ROB reads
 system.cpu.rob.rob_writes                       39564                       # The number of ROB writes
 system.cpu.timesIdled                             184                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
+system.cpu.workload.num_syscalls                   11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
index 8fb08388b..abc865e69 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb  8 2011 00:58:34
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:22:35
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
index cddb4c7b6..26beb56a5 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 992012                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 219616                       # Number of bytes of host memory used
+host_inst_rate                                 918185                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200072                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              556721453                       # Simulator tick rate (ticks/s)
+host_tick_rate                              520394424                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        9810                       # Number of instructions simulated
 sim_seconds                                  0.000006                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes               9368                       # nu
 system.cpu.num_load_insts                        1056                       # Number of load instructions
 system.cpu.num_mem_refs                          1990                       # number of memory refs
 system.cpu.num_store_insts                        934                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
+system.cpu.workload.num_syscalls                   11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index a51884b7a..f9c7081f4 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -160,6 +160,7 @@ deadlock_threshold=500000
 icache=system.ruby.cpu_ruby_ports.dcache
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index 569662936..5b362fa1f 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/08/2011 00:58:34
+Real time: Apr/19/2011 12:26:55
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.26
-Virtual_time_in_minutes: 0.00433333
-Virtual_time_in_hours:   7.22222e-05
-Virtual_time_in_days:    3.00926e-06
+Virtual_time_in_seconds: 0.17
+Virtual_time_in_minutes: 0.00283333
+Virtual_time_in_hours:   4.72222e-05
+Virtual_time_in_days:    1.96759e-06
 
 Ruby_current_time: 276484
 Ruby_start_time: 0
 Ruby_cycles: 276484
 
-mbytes_resident: 38.6797
-mbytes_total: 231.98
-resident_ratio: 0.166754
+mbytes_resident: 39.5938
+mbytes_total: 212.965
+resident_ratio: 0.185935
 
 ruby_cycles_executed: [ 276485 ]
 
@@ -70,9 +70,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8901 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 371 count: 8900 average: 30.0656 | standard deviation: 63.8436 | 0 7523 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ]
-miss_latency_IFETCH: [binsize: 2 max: 369 count: 6910 average: 18.6938 | standard deviation: 50.1996 | 0 6287 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_LD: [binsize: 2 max: 293 count: 1048 average: 86.792 | standard deviation: 89.333 | 0 549 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST: [binsize: 2 max: 371 count: 934 average: 50.6017 | standard deviation: 78.9939 | 0 680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_IFETCH: [binsize: 2 max: 369 count: 6910 average: 18.6938 | standard deviation: 50.1996 | 0 6287 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_RMW_Read: [binsize: 1 max: 169 count: 8 average: 23.75 | standard deviation: 58.6905 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_L1Cache: [binsize: 1 max: 3 count: 7523 average:     3 | standard deviation: 0 | 0 0 0 7523 ]
 miss_latency_Directory: [binsize: 2 max: 371 count: 1377 average: 177.934 | standard deviation: 21.7881 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ]
@@ -86,12 +86,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average:
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average:   159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 imcomplete_dir_Times: 1376
-miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6287 average:     3 | standard deviation: 0 | 0 0 0 6287 ]
-miss_latency_IFETCH_Directory: [binsize: 2 max: 369 count: 623 average: 177.067 | standard deviation: 19.4782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 549 average:     3 | standard deviation: 0 | 0 0 0 549 ]
 miss_latency_LD_Directory: [binsize: 2 max: 293 count: 499 average: 178.98 | standard deviation: 22.8519 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 680 average:     3 | standard deviation: 0 | 0 0 0 680 ]
 miss_latency_ST_Directory: [binsize: 2 max: 371 count: 254 average: 178.039 | standard deviation: 24.8377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6287 average:     3 | standard deviation: 0 | 0 0 0 6287 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 369 count: 623 average: 177.067 | standard deviation: 19.4782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average:     3 | standard deviation: 0 | 0 0 0 7 ]
 miss_latency_RMW_Read_Directory: [binsize: 1 max: 169 count: 1 average:   169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 
@@ -125,7 +125,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11003
+page_reclaims: 10428
 page_faults: 0
 swaps: 0
 block_inputs: 0
@@ -184,7 +184,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache
   system.ruby.cpu_ruby_ports.dcache_request_type_ST:   18.5185%
   system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   45.2433%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   1377    100%
+  system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor:   1377    100%
 
  --- L1Cache ---
  - Event Counts -
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
index ab908eedc..91b45434a 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb  8 2011 00:58:34
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:26:55
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 491eaf1d1..fddfe7f1a 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  81703                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 237552                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
-host_tick_rate                                2292859                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 147176                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 218080                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                                4140017                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        9810                       # Number of instructions simulated
 sim_seconds                                  0.000276                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes               9368                       # nu
 system.cpu.num_load_insts                        1056                       # Number of load instructions
 system.cpu.num_mem_refs                          1990                       # number of memory refs
 system.cpu.num_store_insts                        934                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
+system.cpu.workload.num_syscalls                   11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
index ab79b8cce..673c6e4e6 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
index 43766d7be..894d72125 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb  8 2011 00:58:34
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:22:33
+M5 started Apr 19 2011 12:39:44
+M5 executing on maize
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
index fc7acffe1..b1998f7b5 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 525864                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 227336                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1518719132                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 743049                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 207784                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+host_tick_rate                             2149305775                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        9810                       # Number of instructions simulated
 sim_seconds                                  0.000029                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses              134                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.019695                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0             80.668870                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.019695                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               1990                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses              228                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.051447                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            105.363985                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.051447                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses               6911                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55815.789474                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474                       # average overall mshr miss latency
@@ -170,8 +170,8 @@ system.cpu.l2cache.demand_mshr_misses             361                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.004084                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           133.809342                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.004084                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               362                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -213,6 +213,6 @@ system.cpu.num_int_register_writes               9368                       # nu
 system.cpu.num_load_insts                        1056                       # Number of load instructions
 system.cpu.num_mem_refs                          1990                       # number of memory refs
 system.cpu.num_store_insts                        934                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
+system.cpu.workload.num_syscalls                   11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index cf8986b59..2e792694f 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index c3da6f6a9..138b08408 100755
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 21:44:37
-M5 started Mar 17 2011 21:44:41
-M5 executing on zizzer
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:00:40
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index aedd2d287..93b62df2d 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  72321                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206332                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
-host_tick_rate                               79473363                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 136040                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204288                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
+host_tick_rate                              149415554                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       12773                       # Number of instructions simulated
 sim_seconds                                  0.000014                       # Number of seconds simulated
@@ -16,58 +16,58 @@ system.cpu.BPredUnit.condIncorrect               1551                       # Nu
 system.cpu.BPredUnit.condPredicted               3023                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                     5318                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                      660                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches::0                1051                       # Number of branches committed
-system.cpu.commit.COM:branches::1                1051                       # Number of branches committed
-system.cpu.commit.COM:branches::total            2102                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events               151                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited::0                 0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:bw_limited::1                 0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:bw_limited::total             0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples        22336                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.573379                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.337408                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0        16656     74.57%     74.57% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1         2886     12.92%     87.49% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2         1149      5.14%     92.64% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3          571      2.56%     95.19% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4          362      1.62%     96.81% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5          238      1.07%     97.88% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6          197      0.88%     98.76% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7          126      0.56%     99.32% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8          151      0.68%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total        22336                       # Number of insts commited each cycle
-system.cpu.commit.COM:count::0                   6404                       # Number of instructions committed
-system.cpu.commit.COM:count::1                   6403                       # Number of instructions committed
-system.cpu.commit.COM:count::total              12807                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts::0                  10                       # Number of committed floating point instructions.
-system.cpu.commit.COM:fp_insts::1                  10                       # Number of committed floating point instructions.
-system.cpu.commit.COM:fp_insts::total              20                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls::0           127                       # Number of function calls committed.
-system.cpu.commit.COM:function_calls::1           127                       # Number of function calls committed.
-system.cpu.commit.COM:function_calls::total          254                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts::0               6321                       # Number of committed integer instructions.
-system.cpu.commit.COM:int_insts::1               6321                       # Number of committed integer instructions.
-system.cpu.commit.COM:int_insts::total          12642                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads::0                   1185                       # Number of loads committed
-system.cpu.commit.COM:loads::1                   1185                       # Number of loads committed
-system.cpu.commit.COM:loads::total               2370                       # Number of loads committed
-system.cpu.commit.COM:membars::0                    0                       # Number of memory barriers committed
-system.cpu.commit.COM:membars::1                    0                       # Number of memory barriers committed
-system.cpu.commit.COM:membars::total                0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs::0                    2050                       # Number of memory references committed
-system.cpu.commit.COM:refs::1                    2050                       # Number of memory references committed
-system.cpu.commit.COM:refs::total                4100                       # Number of memory references committed
-system.cpu.commit.COM:swp_count::0                  0                       # Number of s/w prefetches committed
-system.cpu.commit.COM:swp_count::1                  0                       # Number of s/w prefetches committed
-system.cpu.commit.COM:swp_count::total              0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts              1135                       # The number of times a branch was mispredicted
+system.cpu.commit.branches::0                    1051                       # Number of branches committed
+system.cpu.commit.branches::1                    1051                       # Number of branches committed
+system.cpu.commit.branches::total                2102                       # Number of branches committed
+system.cpu.commit.bw_lim_events                   151                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited::0                     0                       # number of insts not committed due to BW limits
+system.cpu.commit.bw_limited::1                     0                       # number of insts not committed due to BW limits
+system.cpu.commit.bw_limited::total                 0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts          12807                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls              34                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts           10106                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples        22336                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.573379                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.337408                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        16656     74.57%     74.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         2886     12.92%     87.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1149      5.14%     92.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          571      2.56%     95.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          362      1.62%     96.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          238      1.07%     97.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          197      0.88%     98.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7          126      0.56%     99.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          151      0.68%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        22336                       # Number of insts commited each cycle
+system.cpu.commit.count::0                       6404                       # Number of instructions committed
+system.cpu.commit.count::1                       6403                       # Number of instructions committed
+system.cpu.commit.count::total                  12807                       # Number of instructions committed
+system.cpu.commit.fp_insts::0                      10                       # Number of committed floating point instructions.
+system.cpu.commit.fp_insts::1                      10                       # Number of committed floating point instructions.
+system.cpu.commit.fp_insts::total                  20                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls::0               127                       # Number of function calls committed.
+system.cpu.commit.function_calls::1               127                       # Number of function calls committed.
+system.cpu.commit.function_calls::total           254                       # Number of function calls committed.
+system.cpu.commit.int_insts::0                   6321                       # Number of committed integer instructions.
+system.cpu.commit.int_insts::1                   6321                       # Number of committed integer instructions.
+system.cpu.commit.int_insts::total              12642                       # Number of committed integer instructions.
+system.cpu.commit.loads::0                       1185                       # Number of loads committed
+system.cpu.commit.loads::1                       1185                       # Number of loads committed
+system.cpu.commit.loads::total                   2370                       # Number of loads committed
+system.cpu.commit.membars::0                        0                       # Number of memory barriers committed
+system.cpu.commit.membars::1                        0                       # Number of memory barriers committed
+system.cpu.commit.membars::total                    0                       # Number of memory barriers committed
+system.cpu.commit.refs::0                        2050                       # Number of memory references committed
+system.cpu.commit.refs::1                        2050                       # Number of memory references committed
+system.cpu.commit.refs::total                    4100                       # Number of memory references committed
+system.cpu.commit.swp_count::0                      0                       # Number of s/w prefetches committed
+system.cpu.commit.swp_count::1                      0                       # Number of s/w prefetches committed
+system.cpu.commit.swp_count::total                  0                       # Number of s/w prefetches committed
 system.cpu.committedInsts::0                     6387                       # Number of Instructions Simulated
 system.cpu.committedInsts::1                     6386                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                 12773                       # Number of Instructions Simulated
@@ -146,8 +146,8 @@ system.cpu.dcache.mshr_cap_events::0                0                       # nu
 system.cpu.dcache.mshr_cap_events::1                0                       # number of times MSHR cap was activated
 system.cpu.dcache.mshr_cap_events::total            0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.053796                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            220.347711                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.053796                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               5457                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency::0 33667.818361                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::1            0                       # average overall miss latency
@@ -195,15 +195,15 @@ system.cpu.dcache.warmup_cycle                      0                       # Cy
 system.cpu.dcache.writebacks::0                     0                       # number of writebacks
 system.cpu.dcache.writebacks::1                     0                       # number of writebacks
 system.cpu.dcache.writebacks::total                 0                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles           4700                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred            432                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved           582                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts           26467                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles             33032                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles               4744                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles            1971                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts            600                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles            114                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles                  4700                       # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred                   432                       # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved                  582                       # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts                  26467                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                    33032                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                      4744                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                   1971                       # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts                   600                       # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles                   114                       # Number of cycles decode is unblocking
 system.cpu.dtb.data_accesses                     6011                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                         5860                       # DTB hits
@@ -305,8 +305,8 @@ system.cpu.icache.mshr_cap_events::0                0                       # nu
 system.cpu.icache.mshr_cap_events::1                0                       # number of times MSHR cap was activated
 system.cpu.icache.mshr_cap_events::total            0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.155654                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            318.780075                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.155654                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses               3965                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency::0 36242.350061                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::1            0                       # average overall miss latency
@@ -355,47 +355,23 @@ system.cpu.icache.writebacks::0                     0                       # nu
 system.cpu.icache.writebacks::1                     0                       # number of writebacks
 system.cpu.icache.writebacks::total                 0                       # number of writebacks
 system.cpu.idleCycles                            5746                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches::0                  1549                       # Number of branches executed
-system.cpu.iew.EXEC:branches::1                  1545                       # Number of branches executed
-system.cpu.iew.EXEC:branches::total              3094                       # Number of branches executed
-system.cpu.iew.EXEC:nop::0                         67                       # number of nop insts executed
-system.cpu.iew.EXEC:nop::1                         70                       # number of nop insts executed
-system.cpu.iew.EXEC:nop::total                    137                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.665505                       # Inst execution rate
-system.cpu.iew.EXEC:refs::0                      3042                       # number of memory reference insts executed
-system.cpu.iew.EXEC:refs::1                      2988                       # number of memory reference insts executed
-system.cpu.iew.EXEC:refs::total                  6030                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores::0                    1059                       # Number of stores executed
-system.cpu.iew.EXEC:stores::1                    1037                       # Number of stores executed
-system.cpu.iew.EXEC:stores::total                2096                       # Number of stores executed
-system.cpu.iew.EXEC:swp::0                          0                       # number of swp insts executed
-system.cpu.iew.EXEC:swp::1                          0                       # number of swp insts executed
-system.cpu.iew.EXEC:swp::total                      0                       # number of swp insts executed
-system.cpu.iew.WB:consumers::0                   5857                       # num instructions consuming a value
-system.cpu.iew.WB:consumers::1                   5876                       # num instructions consuming a value
-system.cpu.iew.WB:consumers::total              11733                       # num instructions consuming a value
-system.cpu.iew.WB:count::0                       9007                       # cumulative count of insts written-back
-system.cpu.iew.WB:count::1                       9010                       # cumulative count of insts written-back
-system.cpu.iew.WB:count::total                  18017                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout::0                  0.769336                       # average fanout of values written-back
-system.cpu.iew.WB:fanout::1                  0.769401                       # average fanout of values written-back
-system.cpu.iew.WB:fanout::total              1.538737                       # average fanout of values written-back
-system.cpu.iew.WB:penalized::0                      0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized::1                      0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized::total                  0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate::0                 0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:penalized_rate::1                 0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:penalized_rate::total             0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers::0                   4506                       # num instructions producing a value
-system.cpu.iew.WB:producers::1                   4521                       # num instructions producing a value
-system.cpu.iew.WB:producers::total               9027                       # num instructions producing a value
-system.cpu.iew.WB:rate::0                    0.320340                       # insts written-back per cycle
-system.cpu.iew.WB:rate::1                    0.320447                       # insts written-back per cycle
-system.cpu.iew.WB:rate::total                0.640787                       # insts written-back per cycle
-system.cpu.iew.WB:sent::0                        9150                       # cumulative count of insts sent to commit
-system.cpu.iew.WB:sent::1                        9113                       # cumulative count of insts sent to commit
-system.cpu.iew.WB:sent::total                   18263                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts                 1313                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches::0                  1549                       # Number of branches executed
+system.cpu.iew.exec_branches::1                  1545                       # Number of branches executed
+system.cpu.iew.exec_branches::total              3094                       # Number of branches executed
+system.cpu.iew.exec_nop::0                         67                       # number of nop insts executed
+system.cpu.iew.exec_nop::1                         70                       # number of nop insts executed
+system.cpu.iew.exec_nop::total                    137                       # number of nop insts executed
+system.cpu.iew.exec_rate                     0.665505                       # Inst execution rate
+system.cpu.iew.exec_refs::0                      3042                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::1                      2988                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::total                  6030                       # number of memory reference insts executed
+system.cpu.iew.exec_stores::0                    1059                       # Number of stores executed
+system.cpu.iew.exec_stores::1                    1037                       # Number of stores executed
+system.cpu.iew.exec_stores::total                2096                       # Number of stores executed
+system.cpu.iew.exec_swp::0                          0                       # number of swp insts executed
+system.cpu.iew.exec_swp::1                          0                       # number of swp insts executed
+system.cpu.iew.exec_swp::total                      0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                     965                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts                  4691                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                 46                       # Number of dispatched non-speculative instructions
@@ -435,178 +411,184 @@ system.cpu.iew.lsq.thread.1.squashedStores          334                       #
 system.cpu.iew.memOrderViolationEvents             28                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect         1056                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            257                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers::0                   5857                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::1                   5876                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::total              11733                       # num instructions consuming a value
+system.cpu.iew.wb_count::0                       9007                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::1                       9010                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::total                  18017                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout::0                  0.769336                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::1                  0.769401                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::total              1.538737                       # average fanout of values written-back
+system.cpu.iew.wb_penalized::0                      0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized::1                      0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized::total                  0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate::0                 0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_penalized_rate::1                 0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_penalized_rate::total             0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers::0                   4506                       # num instructions producing a value
+system.cpu.iew.wb_producers::1                   4521                       # num instructions producing a value
+system.cpu.iew.wb_producers::total               9027                       # num instructions producing a value
+system.cpu.iew.wb_rate::0                    0.320340                       # insts written-back per cycle
+system.cpu.iew.wb_rate::1                    0.320447                       # insts written-back per cycle
+system.cpu.iew.wb_rate::total                0.640787                       # insts written-back per cycle
+system.cpu.iew.wb_sent::0                        9150                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1                        9113                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total                   18263                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                    23704                       # number of integer regfile reads
 system.cpu.int_regfile_writes                   13551                       # number of integer regfile writes
 system.cpu.ipc::0                            0.227158                       # IPC: Instructions Per Cycle
 system.cpu.ipc::1                            0.227122                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.454280                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu            6672     67.35%     67.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              1      0.01%     67.38% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     67.38% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             2      0.02%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     67.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead           2121     21.41%     88.81% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite          1109     11.19%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total             9907                       # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::No_OpClass            2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::IntAlu            6738     68.03%     68.05% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::IntMult              1      0.01%     68.06% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::IntDiv               0      0.00%     68.06% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::FloatAdd             2      0.02%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::FloatCmp             0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::FloatCvt             0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::FloatMult            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::FloatDiv             0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::FloatSqrt            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdAdd              0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdAddAcc            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdAlu              0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdCmp              0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdCvt              0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdMisc             0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdMult             0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdMultAcc            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdShift            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdShiftAcc            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdSqrt             0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdFloatAdd            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdFloatAlu            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdFloatCmp            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdFloatCvt            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdFloatDiv            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdFloatMisc            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdFloatMult            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdFloatMultAcc            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::SimdFloatSqrt            0      0.00%     68.08% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::MemRead           2064     20.84%     88.92% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::MemWrite          1097     11.08%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::total             9904                       # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::No_OpClass             4      0.02%      0.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::IntAlu             13410     67.69%     67.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::IntMult                2      0.01%     67.72% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::IntDiv                 0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::FloatAdd               4      0.02%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::FloatCmp               0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::FloatCvt               0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::FloatMult              0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::FloatDiv               0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::FloatSqrt              0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdAdd                0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdAddAcc             0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdAlu                0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdCmp                0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdCvt                0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdMisc               0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdMult               0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdMultAcc            0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdShift              0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdShiftAcc            0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdSqrt               0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdFloatAdd            0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdFloatAlu            0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdFloatCmp            0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdFloatCvt            0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdFloatDiv            0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdFloatMisc            0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdFloatMult            0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdFloatMultAcc            0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::SimdFloatSqrt            0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::MemRead             4185     21.12%     88.86% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::MemWrite            2206     11.14%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::IprAccess              0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::total              19811                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt::0                 76                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt::1                 88                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt::total            164                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate::0          0.003836                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate::1          0.004442                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate::total      0.008278                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu                10      6.10%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      6.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead               90     54.88%     60.98% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite              64     39.02%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples        22371                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.885566                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.449509                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0         13920     62.22%     62.22% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1          3143     14.05%     76.27% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2          2295     10.26%     86.53% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3          1308      5.85%     92.38% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4           818      3.66%     96.04% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5           557      2.49%     98.52% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6           231      1.03%     99.56% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7            81      0.36%     99.92% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8            18      0.08%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total        22371                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.704592                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  6672     67.35%     67.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2121     21.41%     88.81% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1109     11.19%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total                   9907                       # Type of FU issued
+system.cpu.iq.FU_type_1::No_OpClass                 2      0.02%      0.02% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu                  6738     68.03%     68.05% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult                    1      0.01%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     68.06% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead                 2064     20.84%     88.92% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite                1097     11.08%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::total                   9904                       # Type of FU issued
+system.cpu.iq.FU_type::No_OpClass                   4      0.02%      0.02% # Type of FU issued
+system.cpu.iq.FU_type::IntAlu                   13410     67.69%     67.71% # Type of FU issued
+system.cpu.iq.FU_type::IntMult                      2      0.01%     67.72% # Type of FU issued
+system.cpu.iq.FU_type::IntDiv                       0      0.00%     67.72% # Type of FU issued
+system.cpu.iq.FU_type::FloatAdd                     4      0.02%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::FloatCmp                     0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::FloatCvt                     0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::FloatMult                    0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::FloatDiv                     0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::FloatSqrt                    0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdAdd                      0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdAddAcc                   0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdAlu                      0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdCmp                      0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdCvt                      0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdMisc                     0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdMult                     0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdMultAcc                  0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdShift                    0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdShiftAcc                 0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdSqrt                     0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAdd                 0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAlu                 0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCmp                 0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCvt                 0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatDiv                 0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMisc                0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMult                0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMultAcc             0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatSqrt                0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type::MemRead                   4185     21.12%     88.86% # Type of FU issued
+system.cpu.iq.FU_type::MemWrite                  2206     11.14%    100.00% # Type of FU issued
+system.cpu.iq.FU_type::IprAccess                    0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type::InstPrefetch                 0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type::total                    19811                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                  42                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses           20                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                 20                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt::0                       76                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1                       88                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total                  164                       # FU busy when requested
+system.cpu.iq.fu_busy_rate::0                0.003836                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1                0.004442                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total            0.008278                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      10      6.10%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     90     54.88%     60.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    64     39.02%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses                  19949                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads              62191                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses        17997                       # Number of integer instruction queue wakeup accesses
@@ -618,6 +600,24 @@ system.cpu.iq.iqSquashedInstsExamined            8766                       # Nu
 system.cpu.iq.iqSquashedInstsIssued                76                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             12                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined         4974                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples         22371                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.885566                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.449509                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               13920     62.22%     62.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                3143     14.05%     76.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                2295     10.26%     86.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1308      5.85%     92.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 818      3.66%     96.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 557      2.49%     98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 231      1.03%     99.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  81      0.36%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  18      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           22371                       # Number of insts issued each cycle
+system.cpu.iq.rate                           0.704592                       # Inst issue rate
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
@@ -701,8 +701,8 @@ system.cpu.l2cache.mshr_cap_events::0               0                       # nu
 system.cpu.l2cache.mshr_cap_events::1               0                       # number of times MSHR cap was activated
 system.cpu.l2cache.mshr_cap_events::total            0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.013478                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           441.662390                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.013478                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               966                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency::0 34517.116183                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::1            0                       # average overall miss latency
@@ -763,29 +763,29 @@ system.cpu.misc_regfile_writes                      2                       # nu
 system.cpu.numCycles                            28117                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles             2820                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps           9166                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents               4                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles             33480                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents           1251                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents              2                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups          31536                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts           25241                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands        18899                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles               4323                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles            1971                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles           1300                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps              9733                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups           34                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups        31502                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles          667                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts           50                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts               3351                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts           38                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                    2820                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps                  9166                       # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents                      4                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles                    33480                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents                  1251                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.ROBFullEvents                     2                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RenameLookups                 31536                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts                  25241                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands               18899                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                      4323                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                   1971                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles                  1300                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                     9733                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups                34                       # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups            31502                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles            667                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts                 50                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                      3351                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts             38                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                       106938                       # The number of ROB reads
 system.cpu.rob.rob_writes                       47804                       # The number of ROB writes
 system.cpu.timesIdled                             269                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload0.PROG:num_syscalls             17                       # Number of system calls
-system.cpu.workload1.PROG:num_syscalls             17                       # Number of system calls
+system.cpu.workload0.num_syscalls                  17                       # Number of system calls
+system.cpu.workload1.num_syscalls                  17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 4308ebe8c..8343b4558 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
index 1c0d12619..1dc2f9c34 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 23:04:27
-M5 started Mar 17 2011 23:04:36
-M5 executing on zizzer
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:19:52
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index d6c8de2b4..89a5a939e 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  81712                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206196                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
-host_tick_rate                              105251575                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 110747                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203956                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
+host_tick_rate                              142631877                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       14449                       # Number of instructions simulated
 sim_seconds                                  0.000019                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect                714                       # Nu
 system.cpu.BPredUnit.condPredicted               5154                       # Number of conditional branches predicted
 system.cpu.BPredUnit.lookups                     5154                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches                   3359                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events                86                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples        27481                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.552200                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.190718                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0        19704     71.70%     71.70% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1         4516     16.43%     88.13% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2         1458      5.31%     93.44% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3          763      2.78%     96.22% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4          370      1.35%     97.56% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5          256      0.93%     98.49% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6          290      1.06%     99.55% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7           38      0.14%     99.69% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8           86      0.31%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total        27481                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                     15175                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                      0                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts                 12186                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                      2226                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                       3674                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
 system.cpu.commit.branchMispredicts               714                       # The number of times a branch was mispredicted
+system.cpu.commit.branches                       3359                       # Number of branches committed
+system.cpu.commit.bw_lim_events                    86                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
 system.cpu.commit.commitCommittedInsts          15175                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls             475                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.commitSquashedInsts            5051                       # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples        27481                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.552200                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.190718                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        19704     71.70%     71.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         4516     16.43%     88.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1458      5.31%     93.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          763      2.78%     96.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          370      1.35%     97.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          256      0.93%     98.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          290      1.06%     99.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           38      0.14%     99.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           86      0.31%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        27481                       # Number of insts commited each cycle
+system.cpu.commit.count                         15175                       # Number of instructions committed
+system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
+system.cpu.commit.function_calls                    0                       # Number of function calls committed.
+system.cpu.commit.int_insts                     12186                       # Number of committed integer instructions.
+system.cpu.commit.loads                          2226                       # Number of loads committed
+system.cpu.commit.membars                           0                       # Number of memory barriers committed
+system.cpu.commit.refs                           3674                       # Number of memory references committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.committedInsts                       14449                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                 14449                       # Number of Instructions Simulated
 system.cpu.cpi                               2.579210                       # CPI: Cycles Per Instruction
@@ -98,8 +98,8 @@ system.cpu.dcache.demand_mshr_misses              146                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.024936                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            102.139862                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.024936                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               4206                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 35361.842105                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 35719.178082                       # average overall mshr miss latency
@@ -121,12 +121,12 @@ system.cpu.dcache.tagsinuse                102.139862                       # Cy
 system.cpu.dcache.total_refs                     3680                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles           7079                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts           23444                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles             13037                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles               7241                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles            1159                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles            107                       # Number of cycles decode is unblocking
+system.cpu.decode.BlockedCycles                  7079                       # Number of cycles decode is blocked
+system.cpu.decode.DecodedInsts                  23444                       # Number of instructions handled by decode
+system.cpu.decode.IdleCycles                    13037                       # Number of cycles decode is idle
+system.cpu.decode.RunCycles                      7241                       # Number of cycles decode is running
+system.cpu.decode.SquashCycles                   1159                       # Number of cycles decode is squashing
+system.cpu.decode.UnblockCycles                   107                       # Number of cycles decode is unblocking
 system.cpu.fetch.Branches                        5154                       # Number of branches that fetch encountered
 system.cpu.fetch.CacheLines                      4051                       # Number of cache lines fetched
 system.cpu.fetch.Cycles                          7481                       # Number of cycles fetch has run and was not squashing or blocked
@@ -188,8 +188,8 @@ system.cpu.icache.demand_mshr_misses              354                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.099792                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            204.373592                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.099792                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses               4051                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 35069.791667                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 34975.988701                       # average overall mshr miss latency
@@ -212,21 +212,13 @@ system.cpu.icache.total_refs                     3571                       # To
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idleCycles                            8644                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                     3851                       # Number of branches executed
-system.cpu.iew.EXEC:nop                          1086                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.469692                       # Inst execution rate
-system.cpu.iew.EXEC:refs                         4584                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                       1742                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                      9307                       # num instructions consuming a value
-system.cpu.iew.WB:count                         17063                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.856022                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                      7967                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.457858                       # insts written-back per cycle
-system.cpu.iew.WB:sent                          17239                       # cumulative count of insts sent to commit
 system.cpu.iew.branchMispredicts                  800                       # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches                     3851                       # Number of branches executed
+system.cpu.iew.exec_nop                          1086                       # number of nop insts executed
+system.cpu.iew.exec_rate                     0.469692                       # Inst execution rate
+system.cpu.iew.exec_refs                         4584                       # number of memory reference insts executed
+system.cpu.iew.exec_stores                       1742                       # Number of stores executed
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.iewBlockCycles                     147                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts                  3044                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                564                       # Number of dispatched non-speculative instructions
@@ -254,103 +246,93 @@ system.cpu.iew.lsq.thread.0.squashedStores          446                       #
 system.cpu.iew.memOrderViolationEvents             30                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          560                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            240                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers                      9307                       # num instructions consuming a value
+system.cpu.iew.wb_count                         17063                       # cumulative count of insts written-back
+system.cpu.iew.wb_fanout                     0.856022                       # average fanout of values written-back
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.wb_producers                      7967                       # num instructions producing a value
+system.cpu.iew.wb_rate                       0.457858                       # insts written-back per cycle
+system.cpu.iew.wb_sent                          17239                       # cumulative count of insts sent to commit
 system.cpu.int_regfile_reads                    28062                       # number of integer regfile reads
 system.cpu.int_regfile_writes                   15640                       # number of integer regfile writes
 system.cpu.ipc                               0.387716                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.387716                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu           13268     73.84%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     73.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead           2908     16.18%     90.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite          1793      9.98%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total            17969                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                   125                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.006956                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu                28     22.40%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead               29     23.20%     45.60% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite              68     54.40%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples        28623                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.627782                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.193207                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0         19805     69.19%     69.19% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1          4241     14.82%     84.01% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2          1891      6.61%     90.62% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3          1717      6.00%     96.61% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4           425      1.48%     98.10% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5           278      0.97%     99.07% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6           172      0.60%     99.67% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7            79      0.28%     99.95% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8            15      0.05%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total        28623                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.482169                       # Inst issue rate
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 13268     73.84%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2908     16.18%     90.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1793      9.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total                  17969                       # Type of FU issued
 system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
 system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt                         125                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006956                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      28     22.40%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     29     23.20%     45.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    68     54.40%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.int_alu_accesses                  18094                       # Number of integer alu accesses
 system.cpu.iq.int_inst_queue_reads              64767                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_wakeup_accesses        17063                       # Number of integer instruction queue wakeup accesses
@@ -362,6 +344,24 @@ system.cpu.iq.iqSquashedInstsExamined            4009                       # Nu
 system.cpu.iq.iqSquashedInstsIssued                81                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             89                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined         3563                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples         28623                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.627782                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.193207                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               19805     69.19%     69.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                4241     14.82%     84.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1891      6.61%     90.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1717      6.00%     96.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 425      1.48%     98.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 278      0.97%     99.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 172      0.60%     99.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  79      0.28%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  15      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           28623                       # Number of insts issued each cycle
+system.cpu.iq.rate                           0.482169                       # Inst issue rate
 system.cpu.l2cache.ReadExReq_accesses              83                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34590.361446                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31451.807229                       # average ReadExReq mshr miss latency
@@ -403,8 +403,8 @@ system.cpu.l2cache.demand_mshr_misses             496                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.007283                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           238.651434                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.007283                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               500                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34360.887097                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31144.153226                       # average overall mshr miss latency
@@ -435,25 +435,25 @@ system.cpu.misc_regfile_writes                    569                       # nu
 system.cpu.numCycles                            37267                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles              254                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps          13832                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles             13492                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents            112                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups          40241                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts           21695                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands        19448                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles               7019                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles            1159                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles            421                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps              5616                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:int_rename_lookups        40241                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles         6278                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts          613                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts               2673                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts          579                       # count of temporary serializing insts renamed
+system.cpu.rename.BlockCycles                     254                       # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps                 13832                       # Number of HB maps that are committed
+system.cpu.rename.IdleCycles                    13492                       # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents                   112                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenameLookups                 40241                       # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts                  21695                       # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands               19448                       # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles                      7019                       # Number of cycles rename is running
+system.cpu.rename.SquashCycles                   1159                       # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles                   421                       # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps                     5616                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.int_rename_lookups            40241                       # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles           6278                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts                613                       # count of serializing insts renamed
+system.cpu.rename.skidInsts                      2673                       # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts            579                       # count of temporary serializing insts renamed
 system.cpu.rob.rob_reads                        46798                       # The number of ROB reads
 system.cpu.rob.rob_writes                       41616                       # The number of ROB writes
 system.cpu.timesIdled                             184                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
+system.cpu.workload.num_syscalls                   18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
index d6e92afd2..c90052363 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:13:50
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:21:33
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index 1a17f9fac..9d1db976c 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  73199                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215552                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
-host_tick_rate                               36700023                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 269642                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195292                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                              134978663                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       15175                       # Number of instructions simulated
 sim_seconds                                  0.000008                       # Number of seconds simulated
@@ -29,6 +29,6 @@ system.cpu.num_int_register_writes              13832                       # nu
 system.cpu.num_load_insts                        2232                       # Number of load instructions
 system.cpu.num_mem_refs                          3684                       # number of memory refs
 system.cpu.num_store_insts                       1452                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
+system.cpu.workload.num_syscalls                   18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
index d782c12d4..e5ac7d1dd 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
index 7fbb77bf6..8aa153829 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:13:38
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:20:31
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index b8651e274..5c515b860 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 286147                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 223356                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
-host_tick_rate                              784088172                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 254283                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203032                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                              698170456                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       15175                       # Number of instructions simulated
 sim_seconds                                  0.000042                       # Number of seconds simulated
@@ -52,8 +52,8 @@ system.cpu.dcache.demand_mshr_misses              138                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.023887                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0             97.842991                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.023887                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses               3668                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -107,8 +107,8 @@ system.cpu.icache.demand_mshr_misses              280                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.074920                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            153.436702                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.074920                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses              15221                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        55700                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        52700                       # average overall mshr miss latency
@@ -172,8 +172,8 @@ system.cpu.l2cache.demand_mshr_misses             416                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.005622                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           184.236128                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.005622                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               418                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -215,6 +215,6 @@ system.cpu.num_int_register_writes              13831                       # nu
 system.cpu.num_load_insts                        2232                       # Number of load instructions
 system.cpu.num_mem_refs                          3684                       # number of memory refs
 system.cpu.num_store_insts                       1452                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
+system.cpu.workload.num_syscalls                   18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 1712ae4de..b9ee6d3dc 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -81,6 +81,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -116,6 +117,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -188,6 +190,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -223,6 +226,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -319,6 +323,7 @@ assoc=8
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
@@ -350,6 +355,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index dcb0b4c2e..9887f002f 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:46:17
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:46:32
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:17:36
+M5 started Apr 19 2011 12:18:19
+M5 executing on maize
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 55bb5b9bd..b94a40430 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1669061                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 312244                       # Number of bytes of host memory used
-host_seconds                                    37.84                       # Real time elapsed on the host
-host_tick_rate                            49429698361                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4662508                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 292496                       # Number of bytes of host memory used
+host_seconds                                    13.55                       # Real time elapsed on the host
+host_tick_rate                           138080405600                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    63154034                       # Number of instructions simulated
 sim_seconds                                  1.870336                       # Number of seconds simulated
@@ -70,8 +70,8 @@ system.cpu0.dcache.demand_mshr_misses               0                       # nu
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0                  0.985990                       # Average percentage of cache occupancy
 system.cpu0.dcache.occ_blocks::0           504.827058                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.985990                       # Average percentage of cache occupancy
 system.cpu0.dcache.overall_accesses::0       14729930                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::total     14729930                       # number of overall (read+write) accesses
@@ -162,8 +162,8 @@ system.cpu0.icache.demand_mshr_misses               0                       # nu
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0                  0.998525                       # Average percentage of cache occupancy
 system.cpu0.icache.occ_blocks::0           511.244754                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.998525                       # Average percentage of cache occupancy
 system.cpu0.icache.overall_accesses::0       57230132                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::total     57230132                       # number of overall (read+write) accesses
@@ -385,8 +385,8 @@ system.cpu1.dcache.demand_mshr_misses               0                       # nu
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0                  0.765530                       # Average percentage of cache occupancy
 system.cpu1.dcache.occ_blocks::0           391.951263                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.765530                       # Average percentage of cache occupancy
 system.cpu1.dcache.overall_accesses::0        1884270                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total      1884270                       # number of overall (read+write) accesses
@@ -477,8 +477,8 @@ system.cpu1.icache.demand_mshr_misses               0                       # nu
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0                  0.834231                       # Average percentage of cache occupancy
 system.cpu1.icache.occ_blocks::0           427.126317                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.834231                       # Average percentage of cache occupancy
 system.cpu1.icache.overall_accesses::0        5935766                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::total      5935766                       # number of overall (read+write) accesses
@@ -677,8 +677,8 @@ system.iocache.demand_mshr_misses                   0                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.027215                       # Average percentage of cache occupancy
 system.iocache.occ_blocks::1                 0.435437                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.027215                       # Average percentage of cache occupancy
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              41727                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
@@ -800,12 +800,12 @@ system.l2c.demand_mshr_misses                       0                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.152888                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.004061                       # Average percentage of cache occupancy
-system.l2c.occ_%::2                          0.363646                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                 10019.673951                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                   266.115685                       # Average occupied blocks per context
 system.l2c.occ_blocks::2                 23831.931773                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.152888                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.004061                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.363646                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                2859320                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                 165593                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 6d9c221c4..ffa9d4df6 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -81,6 +81,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -116,6 +117,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -212,6 +214,7 @@ assoc=8
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
@@ -243,6 +246,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index 644d4ca07..01b553cc1 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:46:17
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:46:32
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:17:36
+M5 started Apr 19 2011 12:18:17
+M5 executing on maize
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 3b6776214..85848a462 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1616180                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 311108                       # Number of bytes of host memory used
-host_seconds                                    37.15                       # Real time elapsed on the host
-host_tick_rate                            49243802130                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4724073                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 291084                       # Number of bytes of host memory used
+host_seconds                                    12.71                       # Real time elapsed on the host
+host_tick_rate                           143937379014                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    60038305                       # Number of instructions simulated
 sim_seconds                                  1.829332                       # Number of seconds simulated
@@ -67,8 +67,8 @@ system.cpu.dcache.demand_mshr_misses                0                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999996                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            511.997802                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999996                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses::0        15682061                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     15682061                       # number of overall (read+write) accesses
@@ -159,8 +159,8 @@ system.cpu.icache.demand_mshr_misses                0                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.998467                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            511.215243                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.998467                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses::0        60050143                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     60050143                       # number of overall (read+write) accesses
@@ -371,8 +371,8 @@ system.iocache.demand_mshr_misses                   0                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.076598                       # Average percentage of cache occupancy
 system.iocache.occ_blocks::1                 1.225570                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.076598                       # Average percentage of cache occupancy
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              41726                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
@@ -465,10 +465,10 @@ system.l2c.demand_mshr_misses                       0                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.155542                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.360312                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                 10193.605493                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                 23613.410409                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.155542                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.360312                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                2963266                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2963266                       # number of overall (read+write) accesses
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 41a7379e1..8d055ed5f 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -78,6 +78,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -113,6 +114,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -182,6 +184,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -217,6 +220,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -313,6 +317,7 @@ assoc=8
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
@@ -344,6 +349,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 8f8e92a25..a027f13fc 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:46:17
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:46:32
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:17:36
+M5 started Apr 19 2011 12:17:43
+M5 executing on maize
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 6e0648c43..58de64347 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 901052                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 309020                       # Number of bytes of host memory used
-host_seconds                                    65.87                       # Real time elapsed on the host
-host_tick_rate                            29733229075                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2296983                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 289272                       # Number of bytes of host memory used
+host_seconds                                    25.84                       # Real time elapsed on the host
+host_tick_rate                            75796433096                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    59355643                       # Number of instructions simulated
 sim_seconds                                  1.958647                       # Number of seconds simulated
@@ -114,10 +114,10 @@ system.cpu0.dcache.demand_mshr_misses         1327637                       # nu
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0                  0.983447                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_%::1                 -0.001953                       # Average percentage of cache occupancy
 system.cpu0.dcache.occ_blocks::0           503.524900                       # Average occupied blocks per context
 system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.983447                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::1           -0.001953                       # Average percentage of cache occupancy
 system.cpu0.dcache.overall_accesses::0       14308776                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::total     14308776                       # number of overall (read+write) accesses
@@ -218,8 +218,8 @@ system.cpu0.icache.demand_mshr_misses          915781                       # nu
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0                  0.993751                       # Average percentage of cache occupancy
 system.cpu0.icache.occ_blocks::0           508.800486                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.993751                       # Average percentage of cache occupancy
 system.cpu0.icache.overall_accesses::0       54081252                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::total     54081252                       # number of overall (read+write) accesses
@@ -484,8 +484,8 @@ system.cpu1.dcache.demand_mshr_misses           57534                       # nu
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0                  0.760784                       # Average percentage of cache occupancy
 system.cpu1.dcache.occ_blocks::0           389.521271                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.760784                       # Average percentage of cache occupancy
 system.cpu1.dcache.overall_accesses::0        1677594                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total      1677594                       # number of overall (read+write) accesses
@@ -586,8 +586,8 @@ system.cpu1.icache.demand_mshr_misses           87005                       # nu
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0                  0.819937                       # Average percentage of cache occupancy
 system.cpu1.icache.occ_blocks::0           419.807616                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.819937                       # Average percentage of cache occupancy
 system.cpu1.icache.overall_accesses::0        5286354                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::total      5286354                       # number of overall (read+write) accesses
@@ -801,8 +801,8 @@ system.iocache.demand_mshr_misses               41726                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.035233                       # Average percentage of cache occupancy
 system.iocache.occ_blocks::1                 0.563721                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.035233                       # Average percentage of cache occupancy
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              41726                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
@@ -977,12 +977,12 @@ system.l2c.demand_mshr_misses                  428511                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.165831                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.003052                       # Average percentage of cache occupancy
-system.l2c.occ_%::2                          0.357359                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                 10867.929163                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                   199.983935                       # Average occupied blocks per context
 system.l2c.occ_blocks::2                 23419.887612                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.165831                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.003052                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.357359                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                2250056                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                 139909                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index f28d4e037..80db30395 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -78,6 +78,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -113,6 +114,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -209,6 +211,7 @@ assoc=8
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
@@ -240,6 +243,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index be2bcef8d..aee40b816 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:46:17
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:46:32
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:17:36
+M5 started Apr 19 2011 12:17:43
+M5 executing on maize
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 5f1750494..397168bed 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1077887                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 307624                       # Number of bytes of host memory used
-host_seconds                                    52.08                       # Real time elapsed on the host
-host_tick_rate                            36780244064                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2410973                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 287860                       # Number of bytes of host memory used
+host_seconds                                    23.28                       # Real time elapsed on the host
+host_tick_rate                            82268225536                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    56137087                       # Number of instructions simulated
 sim_seconds                                  1.915549                       # Number of seconds simulated
@@ -101,8 +101,8 @@ system.cpu.dcache.demand_mshr_misses          1373445                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999969                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            511.984023                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999969                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses::0        15029535                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     15029535                       # number of overall (read+write) accesses
@@ -203,8 +203,8 @@ system.cpu.icache.demand_mshr_misses           928354                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.993597                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            508.721464                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.993597                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses::0        56148907                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     56148907                       # number of overall (read+write) accesses
@@ -435,8 +435,8 @@ system.iocache.demand_mshr_misses               41725                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.083770                       # Average percentage of cache occupancy
 system.iocache.occ_blocks::1                 1.340325                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.083770                       # Average percentage of cache occupancy
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              41725                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
@@ -563,10 +563,10 @@ system.l2c.demand_mshr_misses                  422432                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.171530                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.352641                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                 11241.373247                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                 23110.665097                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.171530                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.352641                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                2318771                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2318771                       # number of overall (read+write) accesses
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 22389fff7..fa239be0f 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -11,7 +11,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t
 boot_cpu_frequency=500
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0 
 init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
+kernel=/dist/m5/system/binaries/vmlinux.arm
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
@@ -169,7 +169,7 @@ type=ExeTracer
 
 [system.diskmem]
 type=PhysicalMemory
-file=/chips/pd/randd/dist/disks/ael-arm.ext2
+file=/dist/m5/system/disks/ael-arm.ext2
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index fcaeba8a4..b43a524ba 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr  4 2011 11:17:23
-M5 started Apr  4 2011 11:17:27
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic
+M5 compiled Apr 19 2011 13:41:05
+M5 started Apr 19 2011 13:41:08
+M5 executing on maize
+command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 26405524500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index ef25e7d53..1d1cbe8c6 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1925695                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 381972                       # Number of bytes of host memory used
-host_seconds                                    27.06                       # Real time elapsed on the host
-host_tick_rate                              975977117                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3981428                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 333640                       # Number of bytes of host memory used
+host_seconds                                    13.09                       # Real time elapsed on the host
+host_tick_rate                             2017840381                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    52100192                       # Number of instructions simulated
 sim_seconds                                  0.026406                       # Number of seconds simulated
@@ -67,8 +67,8 @@ system.cpu.dcache.demand_mshr_misses                0                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999487                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            511.737186                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999487                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses::0        14508425                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     14508425                       # number of overall (read+write) accesses
@@ -164,8 +164,8 @@ system.cpu.icache.demand_mshr_misses                0                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.930522                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            476.427204                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.930522                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses::0        41566870                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     41566870                       # number of overall (read+write) accesses
@@ -374,10 +374,10 @@ system.l2c.demand_mshr_misses                       0                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.076949                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.477056                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                  5042.918302                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                 31264.310783                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.076949                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.477056                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                 843462                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                   6142                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total             849604                       # number of overall (read+write) accesses
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
index 586cb6b73..53b01d583 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
@@ -1 +1 @@
-build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
+build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 5e47cea73..6cf3e5508 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -11,7 +11,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t
 boot_cpu_frequency=500
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0 
 init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
+kernel=/dist/m5/system/binaries/vmlinux.arm
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
@@ -166,7 +166,7 @@ type=ExeTracer
 
 [system.diskmem]
 type=PhysicalMemory
-file=/chips/pd/randd/dist/disks/ael-arm.ext2
+file=/dist/m5/system/disks/ael-arm.ext2
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index fee47a4d1..397e3f68f 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr  4 2011 11:17:23
-M5 started Apr  4 2011 11:17:27
-M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing
+M5 compiled Apr 19 2011 13:41:05
+M5 started Apr 19 2011 13:41:07
+M5 executing on maize
+command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 114405702000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index 6471ce023..1213d5a93 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 936835                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 382000                       # Number of bytes of host memory used
-host_seconds                                    54.69                       # Real time elapsed on the host
-host_tick_rate                             2092010024                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1969505                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 333648                       # Number of bytes of host memory used
+host_seconds                                    26.01                       # Real time elapsed on the host
+host_tick_rate                             4398008175                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    51232482                       # Number of instructions simulated
 sim_seconds                                  0.114406                       # Number of seconds simulated
@@ -101,8 +101,8 @@ system.cpu.dcache.demand_mshr_misses           410569                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.994514                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            509.191392                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.994514                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses::0        14503977                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     14503977                       # number of overall (read+write) accesses
@@ -210,8 +210,8 @@ system.cpu.icache.demand_mshr_misses           434434                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.945963                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            484.333151                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.945963                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses::0        41556337                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     41556337                       # number of overall (read+write) accesses
@@ -454,10 +454,10 @@ system.l2c.demand_mshr_misses                  125930                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.081395                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.478089                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                  5334.310202                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                 31332.032709                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.081395                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.478089                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                 846263                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                   5729                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total             851992                       # number of overall (read+write) accesses
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
index 8953751c2..624e9a5f7 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
@@ -1 +1 @@
-build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED!
+build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED!
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index 46cc1ee8d..1f83b404b 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -99,6 +99,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -141,6 +142,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -172,6 +174,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -224,6 +227,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -632,6 +636,7 @@ assoc=8
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
@@ -663,6 +668,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
index 3d2440746..b12d01305 100755
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 26 2011 16:13:31
-M5 revision 412ef0f728a5 8092 default qtip tip updatefsstats.patch
-M5 started Feb 26 2011 16:13:35
-M5 executing on burrito
-command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic
+M5 compiled Apr 19 2011 12:44:38
+M5 started Apr 19 2011 12:44:44
+M5 executing on maize
+command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5112051446000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 432acc1f0..d1e2ef704 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2446370                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 368136                       # Number of bytes of host memory used
-host_seconds                                   166.22                       # Real time elapsed on the host
-host_tick_rate                            30755543746                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3814417                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 349920                       # Number of bytes of host memory used
+host_seconds                                   106.60                       # Real time elapsed on the host
+host_tick_rate                            47954478135                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   406624458                       # Number of instructions simulated
 sim_seconds                                  5.112051                       # Number of seconds simulated
@@ -56,8 +56,8 @@ system.cpu.dcache.demand_mshr_misses                0                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999999                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            511.999375                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999999                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses::0        21771105                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     21771105                       # number of overall (read+write) accesses
@@ -132,8 +132,8 @@ system.cpu.dtb_walker_cache.demand_mshr_misses            0
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.occ_%::1         0.313148                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.occ_blocks::1     5.010366                       # Average occupied blocks per context
+system.cpu.dtb_walker_cache.occ_percent::1     0.313148                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::1        21821                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::total        21821                       # number of overall (read+write) accesses
@@ -208,8 +208,8 @@ system.cpu.icache.demand_mshr_misses                0                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.997320                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            510.627884                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.997320                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses::0       254189385                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total    254189385                       # number of overall (read+write) accesses
@@ -289,8 +289,8 @@ system.cpu.itb_walker_cache.demand_mshr_misses            0
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.occ_%::1         0.188799                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.occ_blocks::1     3.020778                       # Average occupied blocks per context
+system.cpu.itb_walker_cache.occ_percent::1     0.188799                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::1        12219                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::total        12219                       # number of overall (read+write) accesses
@@ -390,8 +390,8 @@ system.iocache.demand_mshr_misses                   0                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.002653                       # Average percentage of cache occupancy
 system.iocache.occ_blocks::1                 0.042448                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.002653                       # Average percentage of cache occupancy
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              47629                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          47629                       # number of overall (read+write) accesses
@@ -489,10 +489,10 @@ system.l2c.demand_mshr_misses                       0                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.147971                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.414180                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                  9697.448079                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                 27143.733047                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.147971                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.414180                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                2414301                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                  10262                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2424563                       # number of overall (read+write) accesses
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 0541c10f2..f05a137d3 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -96,6 +96,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -138,6 +139,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -169,6 +171,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -221,6 +224,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -629,6 +633,7 @@ assoc=8
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=false
 latency=50000
 max_miss_count=0
 mshrs=20
@@ -660,6 +665,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index 62b97bfb9..f1baa96ff 100755
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 26 2011 16:13:31
-M5 revision 412ef0f728a5 8092 default qtip tip updatefsstats.patch
-M5 started Feb 26 2011 16:13:35
-M5 executing on burrito
-command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing
+M5 compiled Apr 19 2011 12:44:38
+M5 started Apr 19 2011 12:46:29
+M5 executing on maize
+command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5195470393000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 8b571b3ea..5e1d5b2a8 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1546136                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 364716                       # Number of bytes of host memory used
-host_seconds                                   170.97                       # Real time elapsed on the host
-host_tick_rate                            30388572127                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2432424                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 346476                       # Number of bytes of host memory used
+host_seconds                                   108.67                       # Real time elapsed on the host
+host_tick_rate                            47808116930                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   264339287                       # Number of instructions simulated
 sim_seconds                                  5.195470                       # Number of seconds simulated
@@ -80,8 +80,8 @@ system.cpu.dcache.demand_mshr_misses          1626168                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999995                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            511.997312                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999995                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses::0        21635359                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     21635359                       # number of overall (read+write) accesses
@@ -166,8 +166,8 @@ system.cpu.dtb_walker_cache.demand_mshr_misses         8896
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.occ_%::1         0.315775                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.occ_blocks::1     5.052403                       # Average occupied blocks per context
+system.cpu.dtb_walker_cache.occ_percent::1     0.315775                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::1        21947                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::total        21947                       # number of overall (read+write) accesses
@@ -252,8 +252,8 @@ system.cpu.icache.demand_mshr_misses           788658                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.996799                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            510.361283                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.996799                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses::0       159222590                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total    159222590                       # number of overall (read+write) accesses
@@ -343,8 +343,8 @@ system.cpu.itb_walker_cache.demand_mshr_misses         4602
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.occ_%::1         0.191913                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.occ_blocks::1     3.070606                       # Average occupied blocks per context
+system.cpu.itb_walker_cache.occ_percent::1     0.191913                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::1        12223                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::total        12223                       # number of overall (read+write) accesses
@@ -464,8 +464,8 @@ system.iocache.demand_mshr_misses               47564                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.007537                       # Average percentage of cache occupancy
 system.iocache.occ_blocks::1                 0.120586                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.007537                       # Average percentage of cache occupancy
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              47564                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          47564                       # number of overall (read+write) accesses
@@ -597,10 +597,10 @@ system.l2c.demand_mshr_misses                  170998                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.120711                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.358261                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                  7910.895776                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                 23478.999694                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.120711                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.358261                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                2411815                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                   9584                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2421399                       # number of overall (read+write) accesses
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
index 5ef0286ce..4c837ce08 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:49
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:24
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
index e65e62021..aaf712409 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1417565                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214360                       # Number of bytes of host memory used
-host_seconds                                     0.35                       # Real time elapsed on the host
-host_tick_rate                              708232428                       # Simulator tick rate (ticks/s)
+host_inst_rate                                5358491                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 194108                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
+host_tick_rate                             2674844665                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500001                       # Number of instructions simulated
 sim_seconds                                  0.000250                       # Number of seconds simulated
@@ -61,6 +61,6 @@ system.cpu.num_int_register_writes             371542                       # nu
 system.cpu.num_load_insts                      124443                       # Number of load instructions
 system.cpu.num_mem_refs                        180793                       # number of memory refs
 system.cpu.num_store_insts                      56350                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
+system.cpu.workload.num_syscalls                   18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 466dd444b..5293d87cb 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -51,6 +51,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -86,6 +87,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
@@ -121,6 +123,7 @@ assoc=2
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
index 2fab9f5ba..596eb6dd7 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:48
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:24
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
index 3dc7b5670..e27e0bfbf 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 663064                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 222076                       # Number of bytes of host memory used
-host_seconds                                     0.75                       # Real time elapsed on the host
-host_tick_rate                              964960959                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2553874                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201796                       # Number of bytes of host memory used
+host_seconds                                     0.20                       # Real time elapsed on the host
+host_tick_rate                             3714828011                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500001                       # Number of instructions simulated
 sim_seconds                                  0.000728                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses              454                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.070111                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_blocks::0            287.175167                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.070111                       # Average percentage of cache occupancy
 system.cpu.dcache.overall_accesses             180775                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses              403                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.129371                       # Average percentage of cache occupancy
 system.cpu.icache.occ_blocks::0            264.952126                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.129371                       # Average percentage of cache occupancy
 system.cpu.icache.overall_accesses             500020                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -201,8 +201,8 @@ system.cpu.l2cache.demand_mshr_misses             857                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.014692                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_blocks::0           481.419470                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.014692                       # Average percentage of cache occupancy
 system.cpu.l2cache.overall_accesses               857                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
@@ -244,6 +244,6 @@ system.cpu.num_int_register_writes             371542                       # nu
 system.cpu.num_load_insts                      124443                       # Number of load instructions
 system.cpu.num_mem_refs                        180793                       # number of memory refs
 system.cpu.num_store_insts                      56350                       # Number of store instructions
-system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
+system.cpu.workload.num_syscalls                   18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
index 9f134009a..63867abf6 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
@@ -54,6 +54,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -89,6 +90,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -166,6 +168,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -201,6 +204,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -278,6 +282,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -313,6 +318,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -390,6 +396,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -425,6 +432,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -473,6 +481,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
index 98d9eda34..c3b5cc937 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
@@ -7,9 +7,6 @@ For more information see: http://www.m5sim.org/warn/3e0eccba
 hack: be nice to actually delete the event here
 
 gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
+stdout: Broken pipe
 
 gzip: stdout: Broken pipe
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index 174fa89ad..6bbd017e9 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:48
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:24
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index 9f848a332..f73f5744f 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1366260                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1147168                       # Number of bytes of host memory used
-host_seconds                                     1.46                       # Real time elapsed on the host
-host_tick_rate                              170760827                       # Simulator tick rate (ticks/s)
+host_inst_rate                                5241411                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1126944                       # Number of bytes of host memory used
+host_seconds                                     0.38                       # Real time elapsed on the host
+host_tick_rate                              654880397                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                     2000004                       # Number of instructions simulated
 sim_seconds                                  0.000250                       # Number of seconds simulated
@@ -38,8 +38,8 @@ system.cpu0.dcache.demand_mshr_misses               0                       # nu
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0                  0.540766                       # Average percentage of cache occupancy
 system.cpu0.dcache.occ_blocks::0           276.872320                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.540766                       # Average percentage of cache occupancy
 system.cpu0.dcache.overall_accesses            180775                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -103,8 +103,8 @@ system.cpu0.icache.demand_mshr_misses               0                       # nu
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0                  0.425950                       # Average percentage of cache occupancy
 system.cpu0.icache.occ_blocks::0           218.086151                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.425950                       # Average percentage of cache occupancy
 system.cpu0.icache.overall_accesses            500019                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -163,7 +163,7 @@ system.cpu0.num_int_register_writes            371542                       # nu
 system.cpu0.num_load_insts                     124443                       # Number of load instructions
 system.cpu0.num_mem_refs                       180793                       # number of memory refs
 system.cpu0.num_store_insts                     56350                       # Number of store instructions
-system.cpu0.workload.PROG:num_syscalls             18                       # Number of system calls
+system.cpu0.workload.num_syscalls                  18                       # Number of system calls
 system.cpu1.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_hits                124111                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_miss_rate         0.002604                       # miss rate for ReadReq accesses
@@ -194,8 +194,8 @@ system.cpu1.dcache.demand_mshr_misses               0                       # nu
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0                  0.540766                       # Average percentage of cache occupancy
 system.cpu1.dcache.occ_blocks::0           276.872320                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.540766                       # Average percentage of cache occupancy
 system.cpu1.dcache.overall_accesses            180775                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -259,8 +259,8 @@ system.cpu1.icache.demand_mshr_misses               0                       # nu
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0                  0.425950                       # Average percentage of cache occupancy
 system.cpu1.icache.occ_blocks::0           218.086151                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.425950                       # Average percentage of cache occupancy
 system.cpu1.icache.overall_accesses            500019                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -319,7 +319,7 @@ system.cpu1.num_int_register_writes            371542                       # nu
 system.cpu1.num_load_insts                     124443                       # Number of load instructions
 system.cpu1.num_mem_refs                       180793                       # number of memory refs
 system.cpu1.num_store_insts                     56350                       # Number of store instructions
-system.cpu1.workload.PROG:num_syscalls             18                       # Number of system calls
+system.cpu1.workload.num_syscalls                  18                       # Number of system calls
 system.cpu2.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
 system.cpu2.dcache.ReadReq_hits                124111                       # number of ReadReq hits
 system.cpu2.dcache.ReadReq_miss_rate         0.002604                       # miss rate for ReadReq accesses
@@ -350,8 +350,8 @@ system.cpu2.dcache.demand_mshr_misses               0                       # nu
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.occ_%::0                  0.540766                       # Average percentage of cache occupancy
 system.cpu2.dcache.occ_blocks::0           276.872320                       # Average occupied blocks per context
+system.cpu2.dcache.occ_percent::0            0.540766                       # Average percentage of cache occupancy
 system.cpu2.dcache.overall_accesses            180775                       # number of overall (read+write) accesses
 system.cpu2.dcache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu2.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -415,8 +415,8 @@ system.cpu2.icache.demand_mshr_misses               0                       # nu
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.icache.occ_%::0                  0.425950                       # Average percentage of cache occupancy
 system.cpu2.icache.occ_blocks::0           218.086151                       # Average occupied blocks per context
+system.cpu2.icache.occ_percent::0            0.425950                       # Average percentage of cache occupancy
 system.cpu2.icache.overall_accesses            500019                       # number of overall (read+write) accesses
 system.cpu2.icache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu2.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -475,7 +475,7 @@ system.cpu2.num_int_register_writes            371542                       # nu
 system.cpu2.num_load_insts                     124443                       # Number of load instructions
 system.cpu2.num_mem_refs                       180793                       # number of memory refs
 system.cpu2.num_store_insts                     56350                       # Number of store instructions
-system.cpu2.workload.PROG:num_syscalls             18                       # Number of system calls
+system.cpu2.workload.num_syscalls                  18                       # Number of system calls
 system.cpu3.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
 system.cpu3.dcache.ReadReq_hits                124111                       # number of ReadReq hits
 system.cpu3.dcache.ReadReq_miss_rate         0.002604                       # miss rate for ReadReq accesses
@@ -506,8 +506,8 @@ system.cpu3.dcache.demand_mshr_misses               0                       # nu
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.occ_%::0                  0.540766                       # Average percentage of cache occupancy
 system.cpu3.dcache.occ_blocks::0           276.872320                       # Average occupied blocks per context
+system.cpu3.dcache.occ_percent::0            0.540766                       # Average percentage of cache occupancy
 system.cpu3.dcache.overall_accesses            180775                       # number of overall (read+write) accesses
 system.cpu3.dcache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu3.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -571,8 +571,8 @@ system.cpu3.icache.demand_mshr_misses               0                       # nu
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.icache.occ_%::0                  0.425950                       # Average percentage of cache occupancy
 system.cpu3.icache.occ_blocks::0           218.086151                       # Average occupied blocks per context
+system.cpu3.icache.occ_percent::0            0.425950                       # Average percentage of cache occupancy
 system.cpu3.icache.overall_accesses            500019                       # number of overall (read+write) accesses
 system.cpu3.icache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu3.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -631,7 +631,7 @@ system.cpu3.num_int_register_writes            371542                       # nu
 system.cpu3.num_load_insts                     124443                       # Number of load instructions
 system.cpu3.num_mem_refs                       180793                       # number of memory refs
 system.cpu3.num_store_insts                     56350                       # Number of store instructions
-system.cpu3.workload.PROG:num_syscalls             18                       # Number of system calls
+system.cpu3.workload.num_syscalls                  18                       # Number of system calls
 system.l2c.ReadExReq_accesses::0                  139                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::1                  139                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::2                  139                       # number of ReadExReq accesses(hits+misses)
@@ -717,16 +717,16 @@ system.l2c.demand_mshr_misses                       0                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.007421                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.007421                       # Average percentage of cache occupancy
-system.l2c.occ_%::2                          0.007421                       # Average percentage of cache occupancy
-system.l2c.occ_%::3                          0.007421                       # Average percentage of cache occupancy
-system.l2c.occ_%::4                          0.000267                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                   486.328367                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                   486.328367                       # Average occupied blocks per context
 system.l2c.occ_blocks::2                   486.328367                       # Average occupied blocks per context
 system.l2c.occ_blocks::3                   486.328367                       # Average occupied blocks per context
 system.l2c.occ_blocks::4                    17.466765                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.007421                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.007421                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.007421                       # Average percentage of cache occupancy
+system.l2c.occ_percent::3                    0.007421                       # Average percentage of cache occupancy
+system.l2c.occ_percent::4                    0.000267                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                    926                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                    926                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                    926                       # number of overall (read+write) accesses
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index 9ec264236..fcea1bc67 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -51,6 +51,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -86,6 +87,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -160,6 +162,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -195,6 +198,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -269,6 +273,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -304,6 +309,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -378,6 +384,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -413,6 +420,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -461,6 +469,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
index fa3024167..98d9eda34 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
@@ -8,8 +8,8 @@ hack: be nice to actually delete the event here
 
 gzip: stdout: Broken pipe
 
-gzip: 
 gzip: stdout: Broken pipe
-stdout: Broken pipe
+
+gzip: stdout: Broken pipe
 
 gzip: stdout: Broken pipe
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index af5204214..7540f8e27 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:37
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:04:57
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index 9dfa01a0d..16349cad5 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 730494                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 229664                       # Number of bytes of host memory used
-host_seconds                                     2.74                       # Real time elapsed on the host
-host_tick_rate                              266213751                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2200513                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209452                       # Number of bytes of host memory used
+host_seconds                                     0.91                       # Real time elapsed on the host
+host_tick_rate                              801856981                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                     1999954                       # Number of instructions simulated
 sim_seconds                                  0.000729                       # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu0.dcache.demand_mshr_misses             463                       # nu
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0                  0.534216                       # Average percentage of cache occupancy
 system.cpu0.dcache.occ_blocks::0           273.518805                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.534216                       # Average percentage of cache occupancy
 system.cpu0.dcache.overall_accesses            180775                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_avg_miss_latency 55244.060475                       # average overall miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency 52244.060475                       # average overall mshr miss latency
@@ -121,8 +121,8 @@ system.cpu0.icache.demand_mshr_misses             463                       # nu
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0                  0.422639                       # Average percentage of cache occupancy
 system.cpu0.icache.occ_blocks::0           216.390931                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.422639                       # Average percentage of cache occupancy
 system.cpu0.icache.overall_accesses            500020                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_avg_miss_latency 50699.784017                       # average overall miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency 47699.784017                       # average overall mshr miss latency
@@ -181,7 +181,7 @@ system.cpu0.num_int_register_writes            371542                       # nu
 system.cpu0.num_load_insts                     124443                       # Number of load instructions
 system.cpu0.num_mem_refs                       180793                       # number of memory refs
 system.cpu0.num_store_insts                     56350                       # Number of store instructions
-system.cpu0.workload.PROG:num_syscalls             18                       # Number of system calls
+system.cpu0.workload.num_syscalls                  18                       # Number of system calls
 system.cpu1.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_avg_miss_latency 54891.975309                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51891.975309                       # average ReadReq mshr miss latency
@@ -224,8 +224,8 @@ system.cpu1.dcache.demand_mshr_misses             463                       # nu
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0                  0.534204                       # Average percentage of cache occupancy
 system.cpu1.dcache.occ_blocks::0           273.512548                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.534204                       # Average percentage of cache occupancy
 system.cpu1.dcache.overall_accesses            180774                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_avg_miss_latency 55265.658747                       # average overall miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency 52265.658747                       # average overall mshr miss latency
@@ -295,8 +295,8 @@ system.cpu1.icache.demand_mshr_misses             463                       # nu
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0                  0.422630                       # Average percentage of cache occupancy
 system.cpu1.icache.occ_blocks::0           216.386658                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.422630                       # Average percentage of cache occupancy
 system.cpu1.icache.overall_accesses            500012                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_avg_miss_latency 50697.624190                       # average overall miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency 47697.624190                       # average overall mshr miss latency
@@ -355,7 +355,7 @@ system.cpu1.num_int_register_writes            371536                       # nu
 system.cpu1.num_load_insts                     124443                       # Number of load instructions
 system.cpu1.num_mem_refs                       180792                       # number of memory refs
 system.cpu1.num_store_insts                     56349                       # Number of store instructions
-system.cpu1.workload.PROG:num_syscalls             18                       # Number of system calls
+system.cpu1.workload.num_syscalls                  18                       # Number of system calls
 system.cpu2.dcache.ReadReq_accesses            124433                       # number of ReadReq accesses(hits+misses)
 system.cpu2.dcache.ReadReq_avg_miss_latency 54919.753086                       # average ReadReq miss latency
 system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51919.753086                       # average ReadReq mshr miss latency
@@ -398,8 +398,8 @@ system.cpu2.dcache.demand_mshr_misses             463                       # nu
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.occ_%::0                  0.534196                       # Average percentage of cache occupancy
 system.cpu2.dcache.occ_blocks::0           273.508588                       # Average occupied blocks per context
+system.cpu2.dcache.occ_percent::0            0.534196                       # Average percentage of cache occupancy
 system.cpu2.dcache.overall_accesses            180772                       # number of overall (read+write) accesses
 system.cpu2.dcache.overall_avg_miss_latency 55272.138229                       # average overall miss latency
 system.cpu2.dcache.overall_avg_mshr_miss_latency 52272.138229                       # average overall mshr miss latency
@@ -469,8 +469,8 @@ system.cpu2.icache.demand_mshr_misses             463                       # nu
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.icache.occ_%::0                  0.422624                       # Average percentage of cache occupancy
 system.cpu2.icache.occ_blocks::0           216.383557                       # Average occupied blocks per context
+system.cpu2.icache.occ_percent::0            0.422624                       # Average percentage of cache occupancy
 system.cpu2.icache.overall_accesses            500001                       # number of overall (read+write) accesses
 system.cpu2.icache.overall_avg_miss_latency 50719.222462                       # average overall miss latency
 system.cpu2.icache.overall_avg_mshr_miss_latency 47719.222462                       # average overall mshr miss latency
@@ -529,7 +529,7 @@ system.cpu2.num_int_register_writes            371526                       # nu
 system.cpu2.num_load_insts                     124440                       # Number of load instructions
 system.cpu2.num_mem_refs                       180789                       # number of memory refs
 system.cpu2.num_store_insts                     56349                       # Number of store instructions
-system.cpu2.workload.PROG:num_syscalls             18                       # Number of system calls
+system.cpu2.workload.num_syscalls                  18                       # Number of system calls
 system.cpu3.dcache.ReadReq_accesses            124431                       # number of ReadReq accesses(hits+misses)
 system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827                       # average ReadReq miss latency
 system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51910.493827                       # average ReadReq mshr miss latency
@@ -572,8 +572,8 @@ system.cpu3.dcache.demand_mshr_misses             463                       # nu
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.occ_%::0                  0.534191                       # Average percentage of cache occupancy
 system.cpu3.dcache.occ_blocks::0           273.505617                       # Average occupied blocks per context
+system.cpu3.dcache.occ_percent::0            0.534191                       # Average percentage of cache occupancy
 system.cpu3.dcache.overall_accesses            180770                       # number of overall (read+write) accesses
 system.cpu3.dcache.overall_avg_miss_latency 55265.658747                       # average overall miss latency
 system.cpu3.dcache.overall_avg_mshr_miss_latency 52265.658747                       # average overall mshr miss latency
@@ -643,8 +643,8 @@ system.cpu3.icache.demand_mshr_misses             463                       # nu
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.icache.occ_%::0                  0.422621                       # Average percentage of cache occupancy
 system.cpu3.icache.occ_blocks::0           216.381810                       # Average occupied blocks per context
+system.cpu3.icache.occ_percent::0            0.422621                       # Average percentage of cache occupancy
 system.cpu3.icache.overall_accesses            499997                       # number of overall (read+write) accesses
 system.cpu3.icache.overall_avg_miss_latency 50738.660907                       # average overall miss latency
 system.cpu3.icache.overall_avg_mshr_miss_latency 47738.660907                       # average overall mshr miss latency
@@ -703,7 +703,7 @@ system.cpu3.num_int_register_writes            371523                       # nu
 system.cpu3.num_load_insts                     124438                       # Number of load instructions
 system.cpu3.num_mem_refs                       180787                       # number of memory refs
 system.cpu3.num_store_insts                     56349                       # Number of store instructions
-system.cpu3.workload.PROG:num_syscalls             18                       # Number of system calls
+system.cpu3.workload.num_syscalls                  18                       # Number of system calls
 system.l2c.ReadExReq_accesses::0                  139                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::1                  139                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::2                  139                       # number of ReadExReq accesses(hits+misses)
@@ -817,16 +817,16 @@ system.l2c.demand_mshr_misses                    3428                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.007348                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.007347                       # Average percentage of cache occupancy
-system.l2c.occ_%::2                          0.007347                       # Average percentage of cache occupancy
-system.l2c.occ_%::3                          0.007347                       # Average percentage of cache occupancy
-system.l2c.occ_%::4                          0.000263                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                   481.530369                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                   481.519672                       # Average occupied blocks per context
 system.l2c.occ_blocks::2                   481.512310                       # Average occupied blocks per context
 system.l2c.occ_blocks::3                   481.507730                       # Average occupied blocks per context
 system.l2c.occ_blocks::4                    17.228456                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.007348                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.007347                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.007347                       # Average percentage of cache occupancy
+system.l2c.occ_percent::3                    0.007347                       # Average percentage of cache occupancy
+system.l2c.occ_percent::4                    0.000263                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                    926                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                    926                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                    926                       # number of overall (read+write) accesses
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index a3508244c..138610412 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -25,6 +25,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
@@ -472,6 +474,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
@@ -900,6 +904,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
@@ -1328,6 +1334,8 @@ BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
 LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
 RASSize=16
 SQEntries=32
 SSITSize=1024
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 7a384b968..c40feed46 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 17 2011 23:04:27
-M5 started Mar 17 2011 23:09:03
-M5 executing on zizzer
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:19:52
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 60b4e57e2..2fc95f0fc 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 134273                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 216692                       # Number of bytes of host memory used
-host_seconds                                     8.59                       # Real time elapsed on the host
-host_tick_rate                               13675054                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 211769                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214500                       # Number of bytes of host memory used
+host_seconds                                     5.45                       # Real time elapsed on the host
+host_tick_rate                               21567548                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                     1153138                       # Number of instructions simulated
 sim_seconds                                  0.000117                       # Number of seconds simulated
@@ -16,38 +16,38 @@ system.cpu0.BPredUnit.condIncorrect              1075                       # Nu
 system.cpu0.BPredUnit.condPredicted             92336                       # Number of conditional branches predicted
 system.cpu0.BPredUnit.lookups                   92336                       # Number of BP lookups
 system.cpu0.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
-system.cpu0.commit.COM:branches                 89544                       # Number of branches committed
-system.cpu0.commit.COM:bw_lim_events              223                       # number cycles where commit BW limit reached
-system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
-system.cpu0.commit.COM:committed_per_cycle::samples       214748                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::mean     2.488931                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::stdev     2.121519                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::0        33657     15.67%     15.67% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::1        90653     42.21%     57.89% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::2         2478      1.15%     59.04% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::3          734      0.34%     59.38% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::4          738      0.34%     59.73% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::5        85720     39.92%     99.64% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::6          469      0.22%     99.86% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::7           76      0.04%     99.90% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::8          223      0.10%    100.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::total       214748                       # Number of insts commited each cycle
-system.cpu0.commit.COM:count                   534493                       # Number of instructions committed
-system.cpu0.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
-system.cpu0.commit.COM:function_calls               0                       # Number of function calls committed.
-system.cpu0.commit.COM:int_insts               359762                       # Number of committed integer instructions.
-system.cpu0.commit.COM:loads                   174300                       # Number of loads committed
-system.cpu0.commit.COM:membars                     84                       # Number of memory barriers committed
-system.cpu0.commit.COM:refs                    261956                       # Number of memory references committed
-system.cpu0.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
 system.cpu0.commit.branchMispredicts             1075                       # The number of times a branch was mispredicted
+system.cpu0.commit.branches                     89544                       # Number of branches committed
+system.cpu0.commit.bw_lim_events                  223                       # number cycles where commit BW limit reached
+system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu0.commit.commitCommittedInsts        534493                       # The number of committed instructions
 system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu0.commit.commitSquashedInsts           9438                       # The number of squashed insts skipped by commit
+system.cpu0.commit.committed_per_cycle::samples       214748                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     2.488931                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     2.121519                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0        33657     15.67%     15.67% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1        90653     42.21%     57.89% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2         2478      1.15%     59.04% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3          734      0.34%     59.38% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4          738      0.34%     59.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5        85720     39.92%     99.64% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6          469      0.22%     99.86% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7           76      0.04%     99.90% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8          223      0.10%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::total       214748                       # Number of insts commited each cycle
+system.cpu0.commit.count                       534493                       # Number of instructions committed
+system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
+system.cpu0.commit.function_calls                   0                       # Number of function calls committed.
+system.cpu0.commit.int_insts                   359762                       # Number of committed integer instructions.
+system.cpu0.commit.loads                       174300                       # Number of loads committed
+system.cpu0.commit.membars                         84                       # Number of memory barriers committed
+system.cpu0.commit.refs                        261956                       # Number of memory references committed
+system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
 system.cpu0.committedInsts                     448134                       # Number of Instructions Simulated
 system.cpu0.committedInsts_total               448134                       # Number of Instructions Simulated
 system.cpu0.cpi                              0.524156                       # CPI: Cycles Per Instruction
@@ -106,10 +106,10 @@ system.cpu0.dcache.demand_mshr_misses             357                       # nu
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0                  0.275966                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_%::1                 -0.002190                       # Average percentage of cache occupancy
 system.cpu0.dcache.occ_blocks::0           141.294426                       # Average occupied blocks per context
 system.cpu0.dcache.occ_blocks::1            -1.121239                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.275966                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::1           -0.002190                       # Average percentage of cache occupancy
 system.cpu0.dcache.overall_accesses            177108                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_avg_miss_latency 37059.207767                       # average overall miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency 32315.126050                       # average overall mshr miss latency
@@ -131,12 +131,12 @@ system.cpu0.dcache.tagsinuse               140.173187                       # Cy
 system.cpu0.dcache.total_refs                  105795                       # Total number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu0.dcache.writebacks                       6                       # number of writebacks
-system.cpu0.decode.DECODE:BlockedCycles         13474                       # Number of cycles decode is blocked
-system.cpu0.decode.DECODE:DecodedInsts         548904                       # Number of instructions handled by decode
-system.cpu0.decode.DECODE:IdleCycles            20013                       # Number of cycles decode is idle
-system.cpu0.decode.DECODE:RunCycles            181043                       # Number of cycles decode is running
-system.cpu0.decode.DECODE:SquashCycles           2044                       # Number of cycles decode is squashing
-system.cpu0.decode.DECODE:UnblockCycles           201                       # Number of cycles decode is unblocking
+system.cpu0.decode.BlockedCycles                13474                       # Number of cycles decode is blocked
+system.cpu0.decode.DecodedInsts                548904                       # Number of instructions handled by decode
+system.cpu0.decode.IdleCycles                   20013                       # Number of cycles decode is idle
+system.cpu0.decode.RunCycles                   181043                       # Number of cycles decode is running
+system.cpu0.decode.SquashCycles                  2044                       # Number of cycles decode is squashing
+system.cpu0.decode.UnblockCycles                  201                       # Number of cycles decode is unblocking
 system.cpu0.fetch.Branches                      92336                       # Number of branches that fetch encountered
 system.cpu0.fetch.CacheLines                     5242                       # Number of cache lines fetched
 system.cpu0.fetch.Cycles                       181487                       # Number of cycles fetch has run and was not squashing or blocked
@@ -199,8 +199,8 @@ system.cpu0.icache.demand_mshr_misses             609                       # nu
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0                  0.502878                       # Average percentage of cache occupancy
 system.cpu0.icache.occ_blocks::0           257.473705                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.502878                       # Average percentage of cache occupancy
 system.cpu0.icache.overall_accesses              5242                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_avg_miss_latency 39013.262599                       # average overall miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency 36995.894910                       # average overall mshr miss latency
@@ -223,21 +223,13 @@ system.cpu0.icache.total_refs                    4488                       # To
 system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.writebacks                       0                       # number of writebacks
 system.cpu0.idleCycles                          18117                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.iew.EXEC:branches                   90345                       # Number of branches executed
-system.cpu0.iew.EXEC:nop                        86733                       # number of nop insts executed
-system.cpu0.iew.EXEC:rate                    1.932437                       # Inst execution rate
-system.cpu0.iew.EXEC:refs                      263598                       # number of memory reference insts executed
-system.cpu0.iew.EXEC:stores                     88173                       # Number of stores executed
-system.cpu0.iew.EXEC:swp                            0                       # number of swp insts executed
-system.cpu0.iew.WB:consumers                   270902                       # num instructions consuming a value
-system.cpu0.iew.WB:count                       453315                       # cumulative count of insts written-back
-system.cpu0.iew.WB:fanout                    0.992949                       # average fanout of values written-back
-system.cpu0.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.iew.WB:producers                   268992                       # num instructions producing a value
-system.cpu0.iew.WB:rate                      1.929887                       # insts written-back per cycle
-system.cpu0.iew.WB:sent                        453561                       # cumulative count of insts sent to commit
 system.cpu0.iew.branchMispredicts                1242                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.exec_branches                   90345                       # Number of branches executed
+system.cpu0.iew.exec_nop                        86733                       # number of nop insts executed
+system.cpu0.iew.exec_rate                    1.932437                       # Inst execution rate
+system.cpu0.iew.exec_refs                      263598                       # number of memory reference insts executed
+system.cpu0.iew.exec_stores                     88173                       # Number of stores executed
+system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu0.iew.iewBlockCycles                    823                       # Number of cycles IEW is blocking
 system.cpu0.iew.iewDispLoadInsts               175971                       # Number of dispatched load instructions
 system.cpu0.iew.iewDispNonSpecInsts               722                       # Number of dispatched non-speculative instructions
@@ -265,103 +257,93 @@ system.cpu0.iew.lsq.thread.0.squashedStores         1054                       #
 system.cpu0.iew.memOrderViolationEvents            44                       # Number of memory order violations
 system.cpu0.iew.predictedNotTakenIncorrect          817                       # Number of branches that were predicted not taken incorrectly
 system.cpu0.iew.predictedTakenIncorrect           425                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.wb_consumers                   270902                       # num instructions consuming a value
+system.cpu0.iew.wb_count                       453315                       # cumulative count of insts written-back
+system.cpu0.iew.wb_fanout                    0.992949                       # average fanout of values written-back
+system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu0.iew.wb_producers                   268992                       # num instructions producing a value
+system.cpu0.iew.wb_rate                      1.929887                       # insts written-back per cycle
+system.cpu0.iew.wb_sent                        453561                       # cumulative count of insts sent to commit
 system.cpu0.int_regfile_reads                  812740                       # number of integer regfile reads
 system.cpu0.int_regfile_writes                 365710                       # number of integer regfile writes
 system.cpu0.ipc                              1.907830                       # IPC: Instructions Per Cycle
 system.cpu0.ipc_total                        1.907830                       # IPC: Total IPC of All Threads
-system.cpu0.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntAlu         190821     41.95%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntMult             0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     41.95% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemRead        175718     38.63%     80.59% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemWrite        88285     19.41%    100.00% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::total          454824                       # Type of FU issued
-system.cpu0.iq.ISSUE:fu_busy_cnt                  223                       # FU busy when requested
-system.cpu0.iq.ISSUE:fu_busy_rate            0.000490                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntAlu               33     14.80%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntMult               0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntDiv                0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatAdd              0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatCmp              0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatCvt              0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatMult             0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatDiv              0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatSqrt             0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdAdd               0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdAlu               0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdCmp               0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdCvt               0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdMisc              0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdMult              0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdShift             0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdSqrt              0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     14.80% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemRead              81     36.32%     51.12% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemWrite            109     48.88%    100.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:issued_per_cycle::samples       216775                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::mean     2.098139                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.056899                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::0        33322     15.37%     15.37% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::1         5647      2.61%     17.98% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::2        88171     40.67%     58.65% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::3        87126     40.19%     98.84% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::4         1486      0.69%     99.53% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::5          733      0.34%     99.87% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::6          191      0.09%     99.95% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::7           90      0.04%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::8            9      0.00%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::total       216775                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:rate                    1.936311                       # Inst issue rate
+system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu               190821     41.95%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     41.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead              175718     38.63%     80.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite              88285     19.41%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::total                454824                       # Type of FU issued
 system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
 system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
 system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
+system.cpu0.iq.fu_busy_cnt                        223                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.000490                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                     33     14.80%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     14.80% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                    81     36.32%     51.12% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite                  109     48.88%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.int_alu_accesses                455047                       # Number of integer alu accesses
 system.cpu0.iq.int_inst_queue_reads           1126736                       # Number of integer instruction queue reads
 system.cpu0.iq.int_inst_queue_wakeup_accesses       453315                       # Number of integer instruction queue wakeup accesses
@@ -373,6 +355,24 @@ system.cpu0.iq.iqSquashedInstsExamined           8136                       # Nu
 system.cpu0.iq.iqSquashedInstsIssued               90                       # Number of squashed instructions issued
 system.cpu0.iq.iqSquashedNonSpecRemoved           261                       # Number of squashed non-spec instructions that were removed
 system.cpu0.iq.iqSquashedOperandsExamined         6774                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.issued_per_cycle::samples       216775                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        2.098139                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.056899                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0              33322     15.37%     15.37% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1               5647      2.61%     17.98% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2              88171     40.67%     58.65% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3              87126     40.19%     98.84% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4               1486      0.69%     99.53% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                733      0.34%     99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6                191      0.09%     99.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7                 90      0.04%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8                  9      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total         216775                       # Number of insts issued each cycle
+system.cpu0.iq.rate                          1.936311                       # Inst issue rate
 system.cpu0.memDep0.conflictingLoads            86214                       # Number of conflicting loads.
 system.cpu0.memDep0.conflictingStores           86089                       # Number of conflicting stores.
 system.cpu0.memDep0.insertedLoads              175971                       # Number of loads inserted to the mem dependence unit.
@@ -382,27 +382,27 @@ system.cpu0.misc_regfile_writes                   564                       # nu
 system.cpu0.numCycles                          234892                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.rename.RENAME:BlockCycles            1209                       # Number of cycles rename is blocking
-system.cpu0.rename.RENAME:CommittedMaps        361432                       # Number of HB maps that are committed
-system.cpu0.rename.RENAME:IQFullEvents              6                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.RENAME:IdleCycles            20699                       # Number of cycles rename is idle
-system.cpu0.rename.RENAME:LSQFullEvents           289                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RENAME:RenameLookups       1088795                       # Number of register rename lookups that rename has made
-system.cpu0.rename.RENAME:RenamedInsts         545750                       # Number of instructions processed by rename
-system.cpu0.rename.RENAME:RenamedOperands       371672                       # Number of destination operands rename has renamed
-system.cpu0.rename.RENAME:RunCycles            180600                       # Number of cycles rename is running
-system.cpu0.rename.RENAME:SquashCycles           2044                       # Number of cycles rename is squashing
-system.cpu0.rename.RENAME:UnblockCycles           697                       # Number of cycles rename is unblocking
-system.cpu0.rename.RENAME:UndoneMaps            10240                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.RENAME:int_rename_lookups      1088795                       # Number of integer rename lookups
-system.cpu0.rename.RENAME:serializeStallCycles        11526                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RENAME:serializingInsts          803                       # count of serializing insts renamed
-system.cpu0.rename.RENAME:skidInsts              4179                       # count of insts added to the skid buffer
-system.cpu0.rename.RENAME:tempSerializingInsts          807                       # count of temporary serializing insts renamed
+system.cpu0.rename.BlockCycles                   1209                       # Number of cycles rename is blocking
+system.cpu0.rename.CommittedMaps               361432                       # Number of HB maps that are committed
+system.cpu0.rename.IQFullEvents                     6                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.IdleCycles                   20699                       # Number of cycles rename is idle
+system.cpu0.rename.LSQFullEvents                  289                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenameLookups              1088795                       # Number of register rename lookups that rename has made
+system.cpu0.rename.RenamedInsts                545750                       # Number of instructions processed by rename
+system.cpu0.rename.RenamedOperands             371672                       # Number of destination operands rename has renamed
+system.cpu0.rename.RunCycles                   180600                       # Number of cycles rename is running
+system.cpu0.rename.SquashCycles                  2044                       # Number of cycles rename is squashing
+system.cpu0.rename.UnblockCycles                  697                       # Number of cycles rename is unblocking
+system.cpu0.rename.UndoneMaps                   10240                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.int_rename_lookups         1088795                       # Number of integer rename lookups
+system.cpu0.rename.serializeStallCycles         11526                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.serializingInsts               803                       # count of serializing insts renamed
+system.cpu0.rename.skidInsts                     4179                       # count of insts added to the skid buffer
+system.cpu0.rename.tempSerializingInsts           807                       # count of temporary serializing insts renamed
 system.cpu0.rob.rob_reads                      757295                       # The number of ROB reads
 system.cpu0.rob.rob_writes                    1089916                       # The number of ROB writes
 system.cpu0.timesIdled                            338                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.workload.PROG:num_syscalls             89                       # Number of system calls
+system.cpu0.workload.num_syscalls                  89                       # Number of system calls
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu1.BPredUnit.BTBHits                   53298                       # Number of BTB hits
 system.cpu1.BPredUnit.BTBLookups                55521                       # Number of BTB lookups
@@ -411,38 +411,38 @@ system.cpu1.BPredUnit.condIncorrect              1087                       # Nu
 system.cpu1.BPredUnit.condPredicted             55616                       # Number of conditional branches predicted
 system.cpu1.BPredUnit.lookups                   55616                       # Number of BP lookups
 system.cpu1.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
-system.cpu1.commit.COM:branches                 52878                       # Number of branches committed
-system.cpu1.commit.COM:bw_lim_events              488                       # number cycles where commit BW limit reached
-system.cpu1.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
-system.cpu1.commit.COM:committed_per_cycle::samples       188159                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::mean     1.583331                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::stdev     1.956493                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::0        78134     41.53%     41.53% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::1        53655     28.52%     70.04% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::2         7488      3.98%     74.02% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::3         7425      3.95%     77.97% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::4         2454      1.30%     79.27% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::5        37926     20.16%     99.43% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::6          461      0.25%     99.67% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::7          128      0.07%     99.74% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::8          488      0.26%    100.00% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::total       188159                       # Number of insts commited each cycle
-system.cpu1.commit.COM:count                   297918                       # Number of instructions committed
-system.cpu1.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
-system.cpu1.commit.COM:function_calls               0                       # Number of function calls committed.
-system.cpu1.commit.COM:int_insts               203433                       # Number of committed integer instructions.
-system.cpu1.commit.COM:loads                    87419                       # Number of loads committed
-system.cpu1.commit.COM:membars                   5903                       # Number of memory barriers committed
-system.cpu1.commit.COM:refs                    128431                       # Number of memory references committed
-system.cpu1.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
 system.cpu1.commit.branchMispredicts             1087                       # The number of times a branch was mispredicted
+system.cpu1.commit.branches                     52878                       # Number of branches committed
+system.cpu1.commit.bw_lim_events                  488                       # number cycles where commit BW limit reached
+system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu1.commit.commitCommittedInsts        297918                       # The number of committed instructions
 system.cpu1.commit.commitNonSpecStalls           6615                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu1.commit.commitSquashedInsts           8048                       # The number of squashed insts skipped by commit
+system.cpu1.commit.committed_per_cycle::samples       188159                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     1.583331                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.956493                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0        78134     41.53%     41.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1        53655     28.52%     70.04% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2         7488      3.98%     74.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3         7425      3.95%     77.97% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4         2454      1.30%     79.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        37926     20.16%     99.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6          461      0.25%     99.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7          128      0.07%     99.74% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8          488      0.26%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::total       188159                       # Number of insts commited each cycle
+system.cpu1.commit.count                       297918                       # Number of instructions committed
+system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
+system.cpu1.commit.function_calls                   0                       # Number of function calls committed.
+system.cpu1.commit.int_insts                   203433                       # Number of committed integer instructions.
+system.cpu1.commit.loads                        87419                       # Number of loads committed
+system.cpu1.commit.membars                       5903                       # Number of memory barriers committed
+system.cpu1.commit.refs                        128431                       # Number of memory references committed
+system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
 system.cpu1.committedInsts                     248345                       # Number of Instructions Simulated
 system.cpu1.committedInsts_total               248345                       # Number of Instructions Simulated
 system.cpu1.cpi                              0.804816                       # CPI: Cycles Per Instruction
@@ -501,10 +501,10 @@ system.cpu1.dcache.demand_mshr_misses             265                       # nu
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0                  0.048953                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_%::1                 -0.017597                       # Average percentage of cache occupancy
 system.cpu1.dcache.occ_blocks::0            25.063911                       # Average occupied blocks per context
 system.cpu1.dcache.occ_blocks::1            -9.009839                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.048953                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::1           -0.017597                       # Average percentage of cache occupancy
 system.cpu1.dcache.overall_accesses             91955                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_avg_miss_latency 21558.058925                       # average overall miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency 14532.075472                       # average overall mshr miss latency
@@ -526,12 +526,12 @@ system.cpu1.dcache.tagsinuse                16.054072                       # Cy
 system.cpu1.dcache.total_refs                   46754                       # Total number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu1.dcache.writebacks                       1                       # number of writebacks
-system.cpu1.decode.DECODE:BlockedCycles         20803                       # Number of cycles decode is blocked
-system.cpu1.decode.DECODE:DecodedInsts         309923                       # Number of instructions handled by decode
-system.cpu1.decode.DECODE:IdleCycles            54694                       # Number of cycles decode is idle
-system.cpu1.decode.DECODE:RunCycles            107191                       # Number of cycles decode is running
-system.cpu1.decode.DECODE:SquashCycles           1741                       # Number of cycles decode is squashing
-system.cpu1.decode.DECODE:UnblockCycles          5470                       # Number of cycles decode is unblocking
+system.cpu1.decode.BlockedCycles                20803                       # Number of cycles decode is blocked
+system.cpu1.decode.DecodedInsts                309923                       # Number of instructions handled by decode
+system.cpu1.decode.IdleCycles                   54694                       # Number of cycles decode is idle
+system.cpu1.decode.RunCycles                   107191                       # Number of cycles decode is running
+system.cpu1.decode.SquashCycles                  1741                       # Number of cycles decode is squashing
+system.cpu1.decode.UnblockCycles                 5470                       # Number of cycles decode is unblocking
 system.cpu1.fetch.Branches                      55616                       # Number of branches that fetch encountered
 system.cpu1.fetch.CacheLines                    20621                       # Number of cache lines fetched
 system.cpu1.fetch.Cycles                       113033                       # Number of cycles fetch has run and was not squashing or blocked
@@ -594,8 +594,8 @@ system.cpu1.icache.demand_mshr_misses             440                       # nu
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0                  0.172715                       # Average percentage of cache occupancy
 system.cpu1.icache.occ_blocks::0            88.430285                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.172715                       # Average percentage of cache occupancy
 system.cpu1.icache.overall_accesses             20621                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_avg_miss_latency 15456.066946                       # average overall miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency 12612.500000                       # average overall mshr miss latency
@@ -618,21 +618,13 @@ system.cpu1.icache.total_refs                   20143                       # To
 system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu1.icache.writebacks                       0                       # number of writebacks
 system.cpu1.idleCycles                           3374                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.iew.EXEC:branches                   53426                       # Number of branches executed
-system.cpu1.iew.EXEC:nop                        44397                       # number of nop insts executed
-system.cpu1.iew.EXEC:rate                    1.290846                       # Inst execution rate
-system.cpu1.iew.EXEC:refs                      129529                       # number of memory reference insts executed
-system.cpu1.iew.EXEC:stores                     41363                       # Number of stores executed
-system.cpu1.iew.EXEC:swp                            0                       # number of swp insts executed
-system.cpu1.iew.WB:consumers                   149591                       # num instructions consuming a value
-system.cpu1.iew.WB:count                       257643                       # cumulative count of insts written-back
-system.cpu1.iew.WB:fanout                    0.975567                       # average fanout of values written-back
-system.cpu1.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.iew.WB:producers                   145936                       # num instructions producing a value
-system.cpu1.iew.WB:rate                      1.289040                       # insts written-back per cycle
-system.cpu1.iew.WB:sent                        257774                       # cumulative count of insts sent to commit
 system.cpu1.iew.branchMispredicts                1186                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.exec_branches                   53426                       # Number of branches executed
+system.cpu1.iew.exec_nop                        44397                       # number of nop insts executed
+system.cpu1.iew.exec_rate                    1.290846                       # Inst execution rate
+system.cpu1.iew.exec_refs                      129529                       # number of memory reference insts executed
+system.cpu1.iew.exec_stores                     41363                       # Number of stores executed
+system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu1.iew.iewBlockCycles                   1504                       # Number of cycles IEW is blocking
 system.cpu1.iew.iewDispLoadInsts                88859                       # Number of dispatched load instructions
 system.cpu1.iew.iewDispNonSpecInsts               932                       # Number of dispatched non-speculative instructions
@@ -660,103 +652,93 @@ system.cpu1.iew.lsq.thread.0.squashedStores          770                       #
 system.cpu1.iew.memOrderViolationEvents            29                       # Number of memory order violations
 system.cpu1.iew.predictedNotTakenIncorrect          196                       # Number of branches that were predicted not taken incorrectly
 system.cpu1.iew.predictedTakenIncorrect           990                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.wb_consumers                   149591                       # num instructions consuming a value
+system.cpu1.iew.wb_count                       257643                       # cumulative count of insts written-back
+system.cpu1.iew.wb_fanout                    0.975567                       # average fanout of values written-back
+system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu1.iew.wb_producers                   145936                       # num instructions producing a value
+system.cpu1.iew.wb_rate                      1.289040                       # insts written-back per cycle
+system.cpu1.iew.wb_sent                        257774                       # cumulative count of insts sent to commit
 system.cpu1.int_regfile_reads                  446126                       # number of integer regfile reads
 system.cpu1.int_regfile_writes                 206677                       # number of integer regfile writes
 system.cpu1.ipc                              1.242520                       # IPC: Instructions Per Cycle
 system.cpu1.ipc_total                        1.242520                       # IPC: Total IPC of All Threads
-system.cpu1.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntAlu         123325     47.62%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntMult             0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     47.62% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemRead         94249     36.39%     84.02% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemWrite        41394     15.98%    100.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::total          258968                       # Type of FU issued
-system.cpu1.iq.ISSUE:fu_busy_cnt                  195                       # FU busy when requested
-system.cpu1.iq.ISSUE:fu_busy_rate            0.000753                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntAlu               11      5.64%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntMult               0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntDiv                0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatAdd              0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCmp              0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCvt              0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatMult             0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatDiv              0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAdd               0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAlu               0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdCmp               0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdCvt               0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMisc              0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMult              0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdShift             0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      5.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemRead              53     27.18%     32.82% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemWrite            131     67.18%    100.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:issued_per_cycle::samples       196498                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::mean     1.317917                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.287238                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::0        79641     40.53%     40.53% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::1        27330     13.91%     54.44% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::2        43586     22.18%     76.62% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::3        41460     21.10%     97.72% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::4         2668      1.36%     99.08% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::5         1566      0.80%     99.87% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::6          155      0.08%     99.95% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::7           82      0.04%     99.99% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::8           10      0.01%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::total       196498                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:rate                    1.295669                       # Inst issue rate
+system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu               123325     47.62%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead               94249     36.39%     84.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite              41394     15.98%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::total                258968                       # Type of FU issued
 system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
 system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
+system.cpu1.iq.fu_busy_cnt                        195                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.000753                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                     11      5.64%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      5.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                    53     27.18%     32.82% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                  131     67.18%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.int_alu_accesses                259163                       # Number of integer alu accesses
 system.cpu1.iq.int_inst_queue_reads            714631                       # Number of integer instruction queue reads
 system.cpu1.iq.int_inst_queue_wakeup_accesses       257643                       # Number of integer instruction queue wakeup accesses
@@ -768,6 +750,24 @@ system.cpu1.iq.iqSquashedInstsExamined           6422                       # Nu
 system.cpu1.iq.iqSquashedInstsIssued                2                       # Number of squashed instructions issued
 system.cpu1.iq.iqSquashedNonSpecRemoved           561                       # Number of squashed non-spec instructions that were removed
 system.cpu1.iq.iqSquashedOperandsExamined         5912                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.issued_per_cycle::samples       196498                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        1.317917                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.287238                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0              79641     40.53%     40.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1              27330     13.91%     54.44% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2              43586     22.18%     76.62% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3              41460     21.10%     97.72% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4               2668      1.36%     99.08% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               1566      0.80%     99.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6                155      0.08%     99.95% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7                 82      0.04%     99.99% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8                 10      0.01%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total         196498                       # Number of insts issued each cycle
+system.cpu1.iq.rate                          1.295669                       # Inst issue rate
 system.cpu1.memDep0.conflictingLoads            43433                       # Number of conflicting loads.
 system.cpu1.memDep0.conflictingStores           37289                       # Number of conflicting stores.
 system.cpu1.memDep0.insertedLoads               88859                       # Number of loads inserted to the mem dependence unit.
@@ -777,23 +777,23 @@ system.cpu1.misc_regfile_writes                   646                       # nu
 system.cpu1.numCycles                          199872                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.rename.RENAME:BlockCycles            7004                       # Number of cycles rename is blocking
-system.cpu1.rename.RENAME:CommittedMaps        204047                       # Number of HB maps that are committed
-system.cpu1.rename.RENAME:IQFullEvents             57                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.RENAME:IdleCycles            55307                       # Number of cycles rename is idle
-system.cpu1.rename.RENAME:LSQFullEvents            48                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RENAME:RenameLookups        588542                       # Number of register rename lookups that rename has made
-system.cpu1.rename.RENAME:RenamedInsts         308173                       # Number of instructions processed by rename
-system.cpu1.rename.RENAME:RenamedOperands       212215                       # Number of destination operands rename has renamed
-system.cpu1.rename.RENAME:RunCycles            112201                       # Number of cycles rename is running
-system.cpu1.rename.RENAME:SquashCycles           1741                       # Number of cycles rename is squashing
-system.cpu1.rename.RENAME:UnblockCycles           589                       # Number of cycles rename is unblocking
-system.cpu1.rename.RENAME:UndoneMaps             8168                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.RENAME:int_rename_lookups       588542                       # Number of integer rename lookups
-system.cpu1.rename.RENAME:serializeStallCycles        13057                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RENAME:serializingInsts          954                       # count of serializing insts renamed
-system.cpu1.rename.RENAME:skidInsts              2780                       # count of insts added to the skid buffer
-system.cpu1.rename.RENAME:tempSerializingInsts         1009                       # count of temporary serializing insts renamed
+system.cpu1.rename.BlockCycles                   7004                       # Number of cycles rename is blocking
+system.cpu1.rename.CommittedMaps               204047                       # Number of HB maps that are committed
+system.cpu1.rename.IQFullEvents                    57                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.IdleCycles                   55307                       # Number of cycles rename is idle
+system.cpu1.rename.LSQFullEvents                   48                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenameLookups               588542                       # Number of register rename lookups that rename has made
+system.cpu1.rename.RenamedInsts                308173                       # Number of instructions processed by rename
+system.cpu1.rename.RenamedOperands             212215                       # Number of destination operands rename has renamed
+system.cpu1.rename.RunCycles                   112201                       # Number of cycles rename is running
+system.cpu1.rename.SquashCycles                  1741                       # Number of cycles rename is squashing
+system.cpu1.rename.UnblockCycles                  589                       # Number of cycles rename is unblocking
+system.cpu1.rename.UndoneMaps                    8168                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.int_rename_lookups          588542                       # Number of integer rename lookups
+system.cpu1.rename.serializeStallCycles         13057                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.serializingInsts               954                       # count of serializing insts renamed
+system.cpu1.rename.skidInsts                     2780                       # count of insts added to the skid buffer
+system.cpu1.rename.tempSerializingInsts          1009                       # count of temporary serializing insts renamed
 system.cpu1.rob.rob_reads                      493050                       # The number of ROB reads
 system.cpu1.rob.rob_writes                     613675                       # The number of ROB writes
 system.cpu1.timesIdled                            291                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -805,38 +805,38 @@ system.cpu2.BPredUnit.condIncorrect              1096                       # Nu
 system.cpu2.BPredUnit.condPredicted             58228                       # Number of conditional branches predicted
 system.cpu2.BPredUnit.lookups                   58228                       # Number of BP lookups
 system.cpu2.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
-system.cpu2.commit.COM:branches                 55433                       # Number of branches committed
-system.cpu2.commit.COM:bw_lim_events              499                       # number cycles where commit BW limit reached
-system.cpu2.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
-system.cpu2.commit.COM:committed_per_cycle::samples       185729                       # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::mean     1.698900                       # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::stdev     1.997080                       # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::0        70586     38.00%     38.00% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::1        56238     30.28%     68.28% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::2         7477      4.03%     72.31% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::3         6262      3.37%     75.68% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::4         2451      1.32%     77.00% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::5        41665     22.43%     99.43% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::6          421      0.23%     99.66% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::7          130      0.07%     99.73% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::8          499      0.27%    100.00% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.COM:committed_per_cycle::total       185729                       # Number of insts commited each cycle
-system.cpu2.commit.COM:count                   315535                       # Number of instructions committed
-system.cpu2.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
-system.cpu2.commit.COM:function_calls               0                       # Number of function calls committed.
-system.cpu2.commit.COM:int_insts               215944                       # Number of committed integer instructions.
-system.cpu2.commit.COM:loads                    93671                       # Number of loads committed
-system.cpu2.commit.COM:membars                   4747                       # Number of memory barriers committed
-system.cpu2.commit.COM:refs                    138392                       # Number of memory references committed
-system.cpu2.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
 system.cpu2.commit.branchMispredicts             1096                       # The number of times a branch was mispredicted
+system.cpu2.commit.branches                     55433                       # Number of branches committed
+system.cpu2.commit.bw_lim_events                  499                       # number cycles where commit BW limit reached
+system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu2.commit.commitCommittedInsts        315535                       # The number of committed instructions
 system.cpu2.commit.commitNonSpecStalls           5463                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu2.commit.commitSquashedInsts           8360                       # The number of squashed insts skipped by commit
+system.cpu2.commit.committed_per_cycle::samples       185729                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.698900                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.997080                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0        70586     38.00%     38.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1        56238     30.28%     68.28% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2         7477      4.03%     72.31% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3         6262      3.37%     75.68% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4         2451      1.32%     77.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5        41665     22.43%     99.43% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6          421      0.23%     99.66% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7          130      0.07%     99.73% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8          499      0.27%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::total       185729                       # Number of insts commited each cycle
+system.cpu2.commit.count                       315535                       # Number of instructions committed
+system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
+system.cpu2.commit.function_calls                   0                       # Number of function calls committed.
+system.cpu2.commit.int_insts                   215944                       # Number of committed integer instructions.
+system.cpu2.commit.loads                        93671                       # Number of loads committed
+system.cpu2.commit.membars                       4747                       # Number of memory barriers committed
+system.cpu2.commit.refs                        138392                       # Number of memory references committed
+system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
 system.cpu2.committedInsts                     264567                       # Number of Instructions Simulated
 system.cpu2.committedInsts_total               264567                       # Number of Instructions Simulated
 system.cpu2.cpi                              0.754365                       # CPI: Cycles Per Instruction
@@ -895,10 +895,10 @@ system.cpu2.dcache.demand_mshr_misses             267                       # nu
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.occ_%::0                  0.052897                       # Average percentage of cache occupancy
-system.cpu2.dcache.occ_%::1                 -0.018338                       # Average percentage of cache occupancy
 system.cpu2.dcache.occ_blocks::0            27.083354                       # Average occupied blocks per context
 system.cpu2.dcache.occ_blocks::1            -9.389236                       # Average occupied blocks per context
+system.cpu2.dcache.occ_percent::0            0.052897                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::1           -0.018338                       # Average percentage of cache occupancy
 system.cpu2.dcache.overall_accesses             98234                       # number of overall (read+write) accesses
 system.cpu2.dcache.overall_avg_miss_latency 22740.237691                       # average overall miss latency
 system.cpu2.dcache.overall_avg_mshr_miss_latency 15338.951311                       # average overall mshr miss latency
@@ -920,12 +920,12 @@ system.cpu2.dcache.tagsinuse                17.694118                       # Cy
 system.cpu2.dcache.total_refs                   50483                       # Total number of references to valid blocks.
 system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu2.dcache.writebacks                       1                       # number of writebacks
-system.cpu2.decode.DECODE:BlockedCycles         20050                       # Number of cycles decode is blocked
-system.cpu2.decode.DECODE:DecodedInsts         327820                       # Number of instructions handled by decode
-system.cpu2.decode.DECODE:IdleCycles            49005                       # Number of cycles decode is idle
-system.cpu2.decode.DECODE:RunCycles            112255                       # Number of cycles decode is running
-system.cpu2.decode.DECODE:SquashCycles           1781                       # Number of cycles decode is squashing
-system.cpu2.decode.DECODE:UnblockCycles          4418                       # Number of cycles decode is unblocking
+system.cpu2.decode.BlockedCycles                20050                       # Number of cycles decode is blocked
+system.cpu2.decode.DecodedInsts                327820                       # Number of instructions handled by decode
+system.cpu2.decode.IdleCycles                   49005                       # Number of cycles decode is idle
+system.cpu2.decode.RunCycles                   112255                       # Number of cycles decode is running
+system.cpu2.decode.SquashCycles                  1781                       # Number of cycles decode is squashing
+system.cpu2.decode.UnblockCycles                 4418                       # Number of cycles decode is unblocking
 system.cpu2.fetch.Branches                      58228                       # Number of branches that fetch encountered
 system.cpu2.fetch.CacheLines                    18194                       # Number of cache lines fetched
 system.cpu2.fetch.Cycles                       117037                       # Number of cycles fetch has run and was not squashing or blocked
@@ -988,8 +988,8 @@ system.cpu2.icache.demand_mshr_misses             440                       # nu
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.icache.occ_%::0                  0.176645                       # Average percentage of cache occupancy
 system.cpu2.icache.occ_blocks::0            90.442244                       # Average occupied blocks per context
+system.cpu2.icache.occ_percent::0            0.176645                       # Average percentage of cache occupancy
 system.cpu2.icache.overall_accesses             18194                       # number of overall (read+write) accesses
 system.cpu2.icache.overall_avg_miss_latency 21635.330579                       # average overall miss latency
 system.cpu2.icache.overall_avg_mshr_miss_latency 18220.454545                       # average overall mshr miss latency
@@ -1012,21 +1012,13 @@ system.cpu2.icache.total_refs                   17710                       # To
 system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu2.icache.writebacks                       0                       # number of writebacks
 system.cpu2.idleCycles                           5466                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.iew.EXEC:branches                   55984                       # Number of branches executed
-system.cpu2.iew.EXEC:nop                        47025                       # number of nop insts executed
-system.cpu2.iew.EXEC:rate                    1.368298                       # Inst execution rate
-system.cpu2.iew.EXEC:refs                      139522                       # number of memory reference insts executed
-system.cpu2.iew.EXEC:stores                     45069                       # Number of stores executed
-system.cpu2.iew.EXEC:swp                            0                       # number of swp insts executed
-system.cpu2.iew.WB:consumers                   159565                       # num instructions consuming a value
-system.cpu2.iew.WB:count                       272710                       # cumulative count of insts written-back
-system.cpu2.iew.WB:fanout                    0.977063                       # average fanout of values written-back
-system.cpu2.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.iew.WB:producers                   155905                       # num instructions producing a value
-system.cpu2.iew.WB:rate                      1.366419                       # insts written-back per cycle
-system.cpu2.iew.WB:sent                        272842                       # cumulative count of insts sent to commit
 system.cpu2.iew.branchMispredicts                1198                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.exec_branches                   55984                       # Number of branches executed
+system.cpu2.iew.exec_nop                        47025                       # number of nop insts executed
+system.cpu2.iew.exec_rate                    1.368298                       # Inst execution rate
+system.cpu2.iew.exec_refs                      139522                       # number of memory reference insts executed
+system.cpu2.iew.exec_stores                     45069                       # Number of stores executed
+system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu2.iew.iewBlockCycles                   1731                       # Number of cycles IEW is blocking
 system.cpu2.iew.iewDispLoadInsts                95225                       # Number of dispatched load instructions
 system.cpu2.iew.iewDispNonSpecInsts               927                       # Number of dispatched non-speculative instructions
@@ -1054,103 +1046,93 @@ system.cpu2.iew.lsq.thread.0.squashedStores          772                       #
 system.cpu2.iew.memOrderViolationEvents            29                       # Number of memory order violations
 system.cpu2.iew.predictedNotTakenIncorrect          202                       # Number of branches that were predicted not taken incorrectly
 system.cpu2.iew.predictedTakenIncorrect           996                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.wb_consumers                   159565                       # num instructions consuming a value
+system.cpu2.iew.wb_count                       272710                       # cumulative count of insts written-back
+system.cpu2.iew.wb_fanout                    0.977063                       # average fanout of values written-back
+system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu2.iew.wb_producers                   155905                       # num instructions producing a value
+system.cpu2.iew.wb_rate                      1.366419                       # insts written-back per cycle
+system.cpu2.iew.wb_sent                        272842                       # cumulative count of insts sent to commit
 system.cpu2.int_regfile_reads                  476036                       # number of integer regfile reads
 system.cpu2.int_regfile_writes                 220349                       # number of integer regfile writes
 system.cpu2.ipc                              1.325619                       # IPC: Instructions Per Cycle
 system.cpu2.ipc_total                        1.325619                       # IPC: Total IPC of All Threads
-system.cpu2.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::IntAlu         129561     47.28%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::IntMult             0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     47.28% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::MemRead         99383     36.27%     83.54% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::MemWrite        45100     16.46%    100.00% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.ISSUE:FU_type_0::total          274044                       # Type of FU issued
-system.cpu2.iq.ISSUE:fu_busy_cnt                  205                       # FU busy when requested
-system.cpu2.iq.ISSUE:fu_busy_rate            0.000748                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::IntAlu               12      5.85%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::IntMult               0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::IntDiv                0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatAdd              0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatCmp              0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatCvt              0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatMult             0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatDiv              0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdAdd               0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdAlu               0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdCmp               0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdCvt               0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdMisc              0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdMult              0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdShift             0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::MemRead              62     30.24%     36.10% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::MemWrite            131     63.90%    100.00% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:issued_per_cycle::samples       194114                       # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::mean     1.411768                       # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::stdev     1.293131                       # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::0        73286     37.75%     37.75% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::1        23867     12.30%     50.05% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::2        47309     24.37%     74.42% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::3        45216     23.29%     97.71% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::4         2634      1.36%     99.07% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::5         1540      0.79%     99.87% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::6          168      0.09%     99.95% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::7           85      0.04%    100.00% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::8            9      0.00%    100.00% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::total       194114                       # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:rate                    1.373104                       # Inst issue rate
+system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu               129561     47.28%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead               99383     36.27%     83.54% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite              45100     16.46%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::total                274044                       # Type of FU issued
 system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
 system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
 system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
+system.cpu2.iq.fu_busy_cnt                        205                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.000748                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                     12      5.85%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      5.85% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                    62     30.24%     36.10% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                  131     63.90%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.int_alu_accesses                274249                       # Number of integer alu accesses
 system.cpu2.iq.int_inst_queue_reads            742408                       # Number of integer instruction queue reads
 system.cpu2.iq.int_inst_queue_wakeup_accesses       272710                       # Number of integer instruction queue wakeup accesses
@@ -1162,6 +1144,24 @@ system.cpu2.iq.iqSquashedInstsExamined           6661                       # Nu
 system.cpu2.iq.iqSquashedInstsIssued                1                       # Number of squashed instructions issued
 system.cpu2.iq.iqSquashedNonSpecRemoved           601                       # Number of squashed non-spec instructions that were removed
 system.cpu2.iq.iqSquashedOperandsExamined         6335                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.issued_per_cycle::samples       194114                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.411768                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.293131                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0              73286     37.75%     37.75% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1              23867     12.30%     50.05% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2              47309     24.37%     74.42% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3              45216     23.29%     97.71% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4               2634      1.36%     99.07% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5               1540      0.79%     99.87% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6                168      0.09%     99.95% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7                 85      0.04%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8                  9      0.00%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total         194114                       # Number of insts issued each cycle
+system.cpu2.iq.rate                          1.373104                       # Inst issue rate
 system.cpu2.memDep0.conflictingLoads            46039                       # Number of conflicting loads.
 system.cpu2.memDep0.conflictingStores           41011                       # Number of conflicting stores.
 system.cpu2.memDep0.insertedLoads               95225                       # Number of loads inserted to the mem dependence unit.
@@ -1171,23 +1171,23 @@ system.cpu2.misc_regfile_writes                   646                       # nu
 system.cpu2.numCycles                          199580                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.rename.RENAME:BlockCycles            6241                       # Number of cycles rename is blocking
-system.cpu2.rename.RENAME:CommittedMaps        217715                       # Number of HB maps that are committed
-system.cpu2.rename.RENAME:IQFullEvents             58                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.RENAME:IdleCycles            49628                       # Number of cycles rename is idle
-system.cpu2.rename.RENAME:LSQFullEvents            58                       # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RENAME:RenameLookups        628783                       # Number of register rename lookups that rename has made
-system.cpu2.rename.RENAME:RenamedInsts         326092                       # Number of instructions processed by rename
-system.cpu2.rename.RENAME:RenamedOperands       225995                       # Number of destination operands rename has renamed
-system.cpu2.rename.RENAME:RunCycles            116192                       # Number of cycles rename is running
-system.cpu2.rename.RENAME:SquashCycles           1781                       # Number of cycles rename is squashing
-system.cpu2.rename.RENAME:UnblockCycles           614                       # Number of cycles rename is unblocking
-system.cpu2.rename.RENAME:UndoneMaps             8280                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.RENAME:int_rename_lookups       628783                       # Number of integer rename lookups
-system.cpu2.rename.RENAME:serializeStallCycles        13053                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RENAME:serializingInsts          948                       # count of serializing insts renamed
-system.cpu2.rename.RENAME:skidInsts              2856                       # count of insts added to the skid buffer
-system.cpu2.rename.RENAME:tempSerializingInsts         1003                       # count of temporary serializing insts renamed
+system.cpu2.rename.BlockCycles                   6241                       # Number of cycles rename is blocking
+system.cpu2.rename.CommittedMaps               217715                       # Number of HB maps that are committed
+system.cpu2.rename.IQFullEvents                    58                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.IdleCycles                   49628                       # Number of cycles rename is idle
+system.cpu2.rename.LSQFullEvents                   58                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenameLookups               628783                       # Number of register rename lookups that rename has made
+system.cpu2.rename.RenamedInsts                326092                       # Number of instructions processed by rename
+system.cpu2.rename.RenamedOperands             225995                       # Number of destination operands rename has renamed
+system.cpu2.rename.RunCycles                   116192                       # Number of cycles rename is running
+system.cpu2.rename.SquashCycles                  1781                       # Number of cycles rename is squashing
+system.cpu2.rename.UnblockCycles                  614                       # Number of cycles rename is unblocking
+system.cpu2.rename.UndoneMaps                    8280                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.int_rename_lookups          628783                       # Number of integer rename lookups
+system.cpu2.rename.serializeStallCycles         13053                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.serializingInsts               948                       # count of serializing insts renamed
+system.cpu2.rename.skidInsts                     2856                       # count of insts added to the skid buffer
+system.cpu2.rename.tempSerializingInsts          1003                       # count of temporary serializing insts renamed
 system.cpu2.rob.rob_reads                      508538                       # The number of ROB reads
 system.cpu2.rob.rob_writes                     649574                       # The number of ROB writes
 system.cpu2.timesIdled                            302                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -1199,38 +1199,38 @@ system.cpu3.BPredUnit.condIncorrect              1096                       # Nu
 system.cpu3.BPredUnit.condPredicted             46026                       # Number of conditional branches predicted
 system.cpu3.BPredUnit.lookups                   46026                       # Number of BP lookups
 system.cpu3.BPredUnit.usedRAS                       0                       # Number of times the RAS was used to get a target.
-system.cpu3.commit.COM:branches                 43201                       # Number of branches committed
-system.cpu3.commit.COM:bw_lim_events              486                       # number cycles where commit BW limit reached
-system.cpu3.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
-system.cpu3.commit.COM:committed_per_cycle::samples       187492                       # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::mean     1.251248                       # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::stdev     1.795283                       # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::0        96787     51.62%     51.62% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::1        44013     23.47%     75.10% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::2         7489      3.99%     79.09% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::3        10030      5.35%     84.44% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::4         2457      1.31%     85.75% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::5        25706     13.71%     99.46% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::6          396      0.21%     99.67% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::7          128      0.07%     99.74% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::8          486      0.26%    100.00% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.COM:committed_per_cycle::total       187492                       # Number of insts commited each cycle
-system.cpu3.commit.COM:count                   234599                       # Number of instructions committed
-system.cpu3.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
-system.cpu3.commit.COM:function_calls               0                       # Number of function calls committed.
-system.cpu3.commit.COM:int_insts               159474                       # Number of committed integer instructions.
-system.cpu3.commit.COM:loads                    65432                       # Number of loads committed
-system.cpu3.commit.COM:membars                   8520                       # Number of memory barriers committed
-system.cpu3.commit.COM:refs                     94154                       # Number of memory references committed
-system.cpu3.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
 system.cpu3.commit.branchMispredicts             1096                       # The number of times a branch was mispredicted
+system.cpu3.commit.branches                     43201                       # Number of branches committed
+system.cpu3.commit.bw_lim_events                  486                       # number cycles where commit BW limit reached
+system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
 system.cpu3.commit.commitCommittedInsts        234599                       # The number of committed instructions
 system.cpu3.commit.commitNonSpecStalls           9238                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu3.commit.commitSquashedInsts           8312                       # The number of squashed insts skipped by commit
+system.cpu3.commit.committed_per_cycle::samples       187492                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     1.251248                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.795283                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0        96787     51.62%     51.62% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1        44013     23.47%     75.10% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2         7489      3.99%     79.09% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3        10030      5.35%     84.44% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4         2457      1.31%     85.75% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5        25706     13.71%     99.46% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6          396      0.21%     99.67% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7          128      0.07%     99.74% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8          486      0.26%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::total       187492                       # Number of insts commited each cycle
+system.cpu3.commit.count                       234599                       # Number of instructions committed
+system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
+system.cpu3.commit.function_calls                   0                       # Number of function calls committed.
+system.cpu3.commit.int_insts                   159474                       # Number of committed integer instructions.
+system.cpu3.commit.loads                        65432                       # Number of loads committed
+system.cpu3.commit.membars                       8520                       # Number of memory barriers committed
+system.cpu3.commit.refs                         94154                       # Number of memory references committed
+system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
 system.cpu3.committedInsts                     192092                       # Number of Instructions Simulated
 system.cpu3.committedInsts_total               192092                       # Number of Instructions Simulated
 system.cpu3.cpi                              1.037576                       # CPI: Cycles Per Instruction
@@ -1289,10 +1289,10 @@ system.cpu3.dcache.demand_mshr_misses             267                       # nu
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.occ_%::0                  0.047232                       # Average percentage of cache occupancy
-system.cpu3.dcache.occ_%::1                 -0.016274                       # Average percentage of cache occupancy
 system.cpu3.dcache.occ_blocks::0            24.182757                       # Average occupied blocks per context
 system.cpu3.dcache.occ_blocks::1            -8.332061                       # Average occupied blocks per context
+system.cpu3.dcache.occ_percent::0            0.047232                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::1           -0.016274                       # Average percentage of cache occupancy
 system.cpu3.dcache.overall_accesses             69946                       # number of overall (read+write) accesses
 system.cpu3.dcache.overall_avg_miss_latency 22662.639405                       # average overall miss latency
 system.cpu3.dcache.overall_avg_mshr_miss_latency 14578.651685                       # average overall mshr miss latency
@@ -1314,12 +1314,12 @@ system.cpu3.dcache.tagsinuse                15.850697                       # Cy
 system.cpu3.dcache.total_refs                   34503                       # Total number of references to valid blocks.
 system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu3.dcache.writebacks                       1                       # number of writebacks
-system.cpu3.decode.DECODE:BlockedCycles         23404                       # Number of cycles decode is blocked
-system.cpu3.decode.DECODE:DecodedInsts         246917                       # Number of instructions handled by decode
-system.cpu3.decode.DECODE:IdleCycles            67894                       # Number of cycles decode is idle
-system.cpu3.decode.DECODE:RunCycles             88329                       # Number of cycles decode is running
-system.cpu3.decode.DECODE:SquashCycles           1781                       # Number of cycles decode is squashing
-system.cpu3.decode.DECODE:UnblockCycles          7864                       # Number of cycles decode is unblocking
+system.cpu3.decode.BlockedCycles                23404                       # Number of cycles decode is blocked
+system.cpu3.decode.DecodedInsts                246917                       # Number of instructions handled by decode
+system.cpu3.decode.IdleCycles                   67894                       # Number of cycles decode is idle
+system.cpu3.decode.RunCycles                    88329                       # Number of cycles decode is running
+system.cpu3.decode.SquashCycles                  1781                       # Number of cycles decode is squashing
+system.cpu3.decode.UnblockCycles                 7864                       # Number of cycles decode is unblocking
 system.cpu3.fetch.Branches                      46026                       # Number of branches that fetch encountered
 system.cpu3.fetch.CacheLines                    26017                       # Number of cache lines fetched
 system.cpu3.fetch.Cycles                        96566                       # Number of cycles fetch has run and was not squashing or blocked
@@ -1382,8 +1382,8 @@ system.cpu3.icache.demand_mshr_misses             443                       # nu
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.icache.occ_%::0                  0.166919                       # Average percentage of cache occupancy
 system.cpu3.icache.occ_blocks::0            85.462768                       # Average occupied blocks per context
+system.cpu3.icache.occ_percent::0            0.166919                       # Average percentage of cache occupancy
 system.cpu3.icache.overall_accesses             26017                       # number of overall (read+write) accesses
 system.cpu3.icache.overall_avg_miss_latency 14208.939709                       # average overall miss latency
 system.cpu3.icache.overall_avg_mshr_miss_latency 11549.661400                       # average overall mshr miss latency
@@ -1406,21 +1406,13 @@ system.cpu3.icache.total_refs                   25536                       # To
 system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu3.icache.writebacks                       0                       # number of writebacks
 system.cpu3.idleCycles                           3421                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.iew.EXEC:branches                   43744                       # Number of branches executed
-system.cpu3.iew.EXEC:nop                        34814                       # number of nop insts executed
-system.cpu3.iew.EXEC:rate                    1.024765                       # Inst execution rate
-system.cpu3.iew.EXEC:refs                       95207                       # number of memory reference insts executed
-system.cpu3.iew.EXEC:stores                     29059                       # Number of stores executed
-system.cpu3.iew.EXEC:swp                            0                       # number of swp insts executed
-system.cpu3.iew.WB:consumers                   115240                       # num instructions consuming a value
-system.cpu3.iew.WB:count                       203888                       # cumulative count of insts written-back
-system.cpu3.iew.WB:fanout                    0.968327                       # average fanout of values written-back
-system.cpu3.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.iew.WB:producers                   111590                       # num instructions producing a value
-system.cpu3.iew.WB:rate                      1.022969                       # insts written-back per cycle
-system.cpu3.iew.WB:sent                        204019                       # cumulative count of insts sent to commit
 system.cpu3.iew.branchMispredicts                1193                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.exec_branches                   43744                       # Number of branches executed
+system.cpu3.iew.exec_nop                        34814                       # number of nop insts executed
+system.cpu3.iew.exec_rate                    1.024765                       # Inst execution rate
+system.cpu3.iew.exec_refs                       95207                       # number of memory reference insts executed
+system.cpu3.iew.exec_stores                     29059                       # Number of stores executed
+system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu3.iew.iewBlockCycles                   1619                       # Number of cycles IEW is blocking
 system.cpu3.iew.iewDispLoadInsts                66949                       # Number of dispatched load instructions
 system.cpu3.iew.iewDispNonSpecInsts               934                       # Number of dispatched non-speculative instructions
@@ -1448,103 +1440,93 @@ system.cpu3.iew.lsq.thread.0.squashedStores          742                       #
 system.cpu3.iew.memOrderViolationEvents            29                       # Number of memory order violations
 system.cpu3.iew.predictedNotTakenIncorrect          182                       # Number of branches that were predicted not taken incorrectly
 system.cpu3.iew.predictedTakenIncorrect          1011                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.wb_consumers                   115240                       # num instructions consuming a value
+system.cpu3.iew.wb_count                       203888                       # cumulative count of insts written-back
+system.cpu3.iew.wb_fanout                    0.968327                       # average fanout of values written-back
+system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
+system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu3.iew.wb_producers                   111590                       # num instructions producing a value
+system.cpu3.iew.wb_rate                      1.022969                       # insts written-back per cycle
+system.cpu3.iew.wb_sent                        204019                       # cumulative count of insts sent to commit
 system.cpu3.int_regfile_reads                  343072                       # number of integer regfile reads
 system.cpu3.int_regfile_writes                 159978                       # number of integer regfile writes
 system.cpu3.ipc                              0.963785                       # IPC: Instructions Per Cycle
 system.cpu3.ipc_total                        0.963785                       # IPC: Total IPC of All Threads
-system.cpu3.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::IntAlu         101269     49.35%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::IntMult             0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatAdd            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatDiv            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     49.35% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::MemRead         74848     36.47%     85.82% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::MemWrite        29089     14.18%    100.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.ISSUE:FU_type_0::total          205206                       # Type of FU issued
-system.cpu3.iq.ISSUE:fu_busy_cnt                  188                       # FU busy when requested
-system.cpu3.iq.ISSUE:fu_busy_rate            0.000916                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::IntAlu               11      5.85%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::IntMult               0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::IntDiv                0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatAdd              0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatCmp              0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatCvt              0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatMult             0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatDiv              0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdAdd               0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdAlu               0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdCmp               0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdCvt               0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdMisc              0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdMult              0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdShift             0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      5.85% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::MemRead              46     24.47%     30.32% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::MemWrite            131     69.68%    100.00% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:issued_per_cycle::samples       195889                       # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::mean     1.047563                       # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::stdev     1.235617                       # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::0        95806     48.91%     48.91% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::1        35106     17.92%     66.83% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::2        31374     16.02%     82.85% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::3        29208     14.91%     97.76% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::4         2591      1.32%     99.08% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::5         1562      0.80%     99.88% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::6          150      0.08%     99.95% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::7           82      0.04%     99.99% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::8           10      0.01%    100.00% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::total       195889                       # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:rate                    1.029582                       # Inst issue rate
+system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu               101269     49.35%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.35% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead               74848     36.47%     85.82% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite              29089     14.18%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::total                205206                       # Type of FU issued
 system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
 system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
 system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
+system.cpu3.iq.fu_busy_cnt                        188                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.000916                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                     11      5.85%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      5.85% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                    46     24.47%     30.32% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite                  131     69.68%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.int_alu_accesses                205394                       # Number of integer alu accesses
 system.cpu3.iq.int_inst_queue_reads            606491                       # Number of integer instruction queue reads
 system.cpu3.iq.int_inst_queue_wakeup_accesses       203888                       # Number of integer instruction queue wakeup accesses
@@ -1556,6 +1538,24 @@ system.cpu3.iq.iqSquashedInstsExamined           6590                       # Nu
 system.cpu3.iq.iqSquashedInstsIssued                2                       # Number of squashed instructions issued
 system.cpu3.iq.iqSquashedNonSpecRemoved           673                       # Number of squashed non-spec instructions that were removed
 system.cpu3.iq.iqSquashedOperandsExamined         6253                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.issued_per_cycle::samples       195889                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        1.047563                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.235617                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0              95806     48.91%     48.91% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1              35106     17.92%     66.83% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2              31374     16.02%     82.85% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3              29208     14.91%     97.76% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4               2591      1.32%     99.08% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5               1562      0.80%     99.88% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6                150      0.08%     99.95% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7                 82      0.04%     99.99% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8                 10      0.01%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total         195889                       # Number of insts issued each cycle
+system.cpu3.iq.rate                          1.029582                       # Inst issue rate
 system.cpu3.memDep0.conflictingLoads            33826                       # Number of conflicting loads.
 system.cpu3.memDep0.conflictingStores           24974                       # Number of conflicting stores.
 system.cpu3.memDep0.insertedLoads               66949                       # Number of loads inserted to the mem dependence unit.
@@ -1565,23 +1565,23 @@ system.cpu3.misc_regfile_writes                   646                       # nu
 system.cpu3.numCycles                          199310                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.rename.RENAME:BlockCycles            9536                       # Number of cycles rename is blocking
-system.cpu3.rename.RENAME:CommittedMaps        157468                       # Number of HB maps that are committed
-system.cpu3.rename.RENAME:IQFullEvents             52                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.RENAME:IdleCycles            68516                       # Number of cycles rename is idle
-system.cpu3.rename.RENAME:LSQFullEvents            39                       # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RENAME:RenameLookups        451555                       # Number of register rename lookups that rename has made
-system.cpu3.rename.RENAME:RenamedInsts         245166                       # Number of instructions processed by rename
-system.cpu3.rename.RENAME:RenamedOperands       165603                       # Number of destination operands rename has renamed
-system.cpu3.rename.RENAME:RunCycles             95731                       # Number of cycles rename is running
-system.cpu3.rename.RENAME:SquashCycles           1781                       # Number of cycles rename is squashing
-system.cpu3.rename.RENAME:UnblockCycles           570                       # Number of cycles rename is unblocking
-system.cpu3.rename.RENAME:UndoneMaps             8135                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.RENAME:int_rename_lookups       451555                       # Number of integer rename lookups
-system.cpu3.rename.RENAME:serializeStallCycles        13138                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RENAME:serializingInsts          958                       # count of serializing insts renamed
-system.cpu3.rename.RENAME:skidInsts              2735                       # count of insts added to the skid buffer
-system.cpu3.rename.RENAME:tempSerializingInsts         1009                       # count of temporary serializing insts renamed
+system.cpu3.rename.BlockCycles                   9536                       # Number of cycles rename is blocking
+system.cpu3.rename.CommittedMaps               157468                       # Number of HB maps that are committed
+system.cpu3.rename.IQFullEvents                    52                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.IdleCycles                   68516                       # Number of cycles rename is idle
+system.cpu3.rename.LSQFullEvents                   39                       # Number of times rename has blocked due to LSQ full
+system.cpu3.rename.RenameLookups               451555                       # Number of register rename lookups that rename has made
+system.cpu3.rename.RenamedInsts                245166                       # Number of instructions processed by rename
+system.cpu3.rename.RenamedOperands             165603                       # Number of destination operands rename has renamed
+system.cpu3.rename.RunCycles                    95731                       # Number of cycles rename is running
+system.cpu3.rename.SquashCycles                  1781                       # Number of cycles rename is squashing
+system.cpu3.rename.UnblockCycles                  570                       # Number of cycles rename is unblocking
+system.cpu3.rename.UndoneMaps                    8135                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.int_rename_lookups          451555                       # Number of integer rename lookups
+system.cpu3.rename.serializeStallCycles         13138                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.serializingInsts               958                       # count of serializing insts renamed
+system.cpu3.rename.skidInsts                     2735                       # count of insts added to the skid buffer
+system.cpu3.rename.tempSerializingInsts          1009                       # count of temporary serializing insts renamed
 system.cpu3.rob.rob_reads                      429330                       # The number of ROB reads
 system.cpu3.rob.rob_writes                     487605                       # The number of ROB writes
 system.cpu3.timesIdled                            294                       # Number of times that the entire CPU went into an idle state and unscheduled itself
@@ -1730,16 +1730,16 @@ system.l2c.demand_mshr_misses                     674                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.005562                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.000156                       # Average percentage of cache occupancy
-system.l2c.occ_%::2                          0.000959                       # Average percentage of cache occupancy
-system.l2c.occ_%::3                          0.000038                       # Average percentage of cache occupancy
-system.l2c.occ_%::4                          0.000079                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                   364.492731                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                    10.237276                       # Average occupied blocks per context
 system.l2c.occ_blocks::2                    62.878855                       # Average occupied blocks per context
 system.l2c.occ_blocks::3                     2.477387                       # Average occupied blocks per context
 system.l2c.occ_blocks::4                     5.202251                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.005562                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.000156                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.000959                       # Average percentage of cache occupancy
+system.l2c.occ_percent::3                    0.000038                       # Average percentage of cache occupancy
+system.l2c.occ_percent::4                    0.000079                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                    783                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                    465                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                    467                       # number of overall (read+write) accesses
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index 01c43d58b..ecad4bd59 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -54,6 +54,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -89,6 +90,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -175,6 +177,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -210,6 +213,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -277,6 +281,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -312,6 +317,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -379,6 +385,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -414,6 +421,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -452,6 +460,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index 2f8db50d8..6a0f61930 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:13:36
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:20:42
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 2fa9a2da1..15dcb1cbd 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 813548                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1149396                       # Number of bytes of host memory used
-host_seconds                                     0.83                       # Real time elapsed on the host
-host_tick_rate                              105315075                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1383029                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1129216                       # Number of bytes of host memory used
+host_seconds                                     0.49                       # Real time elapsed on the host
+host_tick_rate                              179022754                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      677340                       # Number of instructions simulated
 sim_seconds                                  0.000088                       # Number of seconds simulated
@@ -42,8 +42,8 @@ system.cpu0.dcache.demand_mshr_misses               0                       # nu
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0                  0.284595                       # Average percentage of cache occupancy
 system.cpu0.dcache.occ_blocks::0           145.712770                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.284595                       # Average percentage of cache occupancy
 system.cpu0.dcache.overall_accesses             82337                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -91,8 +91,8 @@ system.cpu0.icache.demand_mshr_misses               0                       # nu
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0                  0.435073                       # Average percentage of cache occupancy
 system.cpu0.icache.occ_blocks::0           222.757301                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.435073                       # Average percentage of cache occupancy
 system.cpu0.icache.overall_accesses            175401                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -135,7 +135,7 @@ system.cpu0.num_int_register_writes            121996                       # nu
 system.cpu0.num_load_insts                      54592                       # Number of load instructions
 system.cpu0.num_mem_refs                        82398                       # number of memory refs
 system.cpu0.num_store_insts                     27806                       # Number of store instructions
-system.cpu0.workload.PROG:num_syscalls             89                       # Number of system calls
+system.cpu0.workload.num_syscalls                  89                       # Number of system calls
 system.cpu1.dcache.ReadReq_accesses             40644                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_hits                 40468                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_miss_rate         0.004330                       # miss rate for ReadReq accesses
@@ -170,8 +170,8 @@ system.cpu1.dcache.demand_mshr_misses               0                       # nu
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0                  0.056783                       # Average percentage of cache occupancy
 system.cpu1.dcache.occ_blocks::0            29.073016                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.056783                       # Average percentage of cache occupancy
 system.cpu1.dcache.overall_accesses             53313                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -219,8 +219,8 @@ system.cpu1.icache.demand_mshr_misses               0                       # nu
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0                  0.149895                       # Average percentage of cache occupancy
 system.cpu1.icache.occ_blocks::0            76.746014                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.149895                       # Average percentage of cache occupancy
 system.cpu1.icache.overall_accesses            167430                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -297,8 +297,8 @@ system.cpu2.dcache.demand_mshr_misses               0                       # nu
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.occ_%::0                  0.055509                       # Average percentage of cache occupancy
 system.cpu2.dcache.occ_blocks::0            28.420699                       # Average occupied blocks per context
+system.cpu2.dcache.occ_percent::0            0.055509                       # Average percentage of cache occupancy
 system.cpu2.dcache.overall_accesses             58461                       # number of overall (read+write) accesses
 system.cpu2.dcache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu2.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -346,8 +346,8 @@ system.cpu2.icache.demand_mshr_misses               0                       # nu
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.icache.occ_%::0                  0.146046                       # Average percentage of cache occupancy
 system.cpu2.icache.occ_blocks::0            74.775474                       # Average occupied blocks per context
+system.cpu2.icache.occ_percent::0            0.146046                       # Average percentage of cache occupancy
 system.cpu2.icache.overall_accesses            167366                       # number of overall (read+write) accesses
 system.cpu2.icache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu2.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -424,8 +424,8 @@ system.cpu3.dcache.demand_mshr_misses               0                       # nu
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.occ_%::0                  0.053884                       # Average percentage of cache occupancy
 system.cpu3.dcache.occ_blocks::0            27.588376                       # Average occupied blocks per context
+system.cpu3.dcache.occ_percent::0            0.053884                       # Average percentage of cache occupancy
 system.cpu3.dcache.overall_accesses             55820                       # number of overall (read+write) accesses
 system.cpu3.dcache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu3.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -473,8 +473,8 @@ system.cpu3.icache.demand_mshr_misses               0                       # nu
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.icache.occ_%::0                  0.142322                       # Average percentage of cache occupancy
 system.cpu3.icache.occ_blocks::0            72.869097                       # Average occupied blocks per context
+system.cpu3.icache.occ_percent::0            0.142322                       # Average percentage of cache occupancy
 system.cpu3.icache.overall_accesses            167301                       # number of overall (read+write) accesses
 system.cpu3.icache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu3.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
@@ -619,16 +619,16 @@ system.l2c.demand_mshr_misses                       0                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.004495                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.001011                       # Average percentage of cache occupancy
-system.l2c.occ_%::2                          0.000044                       # Average percentage of cache occupancy
-system.l2c.occ_%::3                          0.000029                       # Average percentage of cache occupancy
-system.l2c.occ_%::4                          0.000098                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                   294.613840                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                    66.228089                       # Average occupied blocks per context
 system.l2c.occ_blocks::2                     2.865859                       # Average occupied blocks per context
 system.l2c.occ_blocks::3                     1.883074                       # Average occupied blocks per context
 system.l2c.occ_blocks::4                     6.390048                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.004495                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.001011                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.000044                       # Average percentage of cache occupancy
+system.l2c.occ_percent::3                    0.000029                       # Average percentage of cache occupancy
+system.l2c.occ_percent::4                    0.000098                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                    637                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                    383                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                    382                       # number of overall (read+write) accesses
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index 8968b20fc..55707ec59 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -51,6 +51,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -86,6 +87,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -169,6 +171,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -204,6 +207,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -268,6 +272,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -303,6 +308,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -367,6 +373,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -402,6 +409,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -440,6 +448,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index 14a3c411f..64cea276f 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 02:13:30
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 02:16:15
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:19:46
+M5 started Apr 19 2011 12:20:58
+M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index dff846f53..42ad4fedc 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 414570                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 231892                       # Number of bytes of host memory used
-host_seconds                                     1.57                       # Real time elapsed on the host
-host_tick_rate                              167151874                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1033305                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211712                       # Number of bytes of host memory used
+host_seconds                                     0.63                       # Real time elapsed on the host
+host_tick_rate                              416577686                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      650423                       # Number of instructions simulated
 sim_seconds                                  0.000262                       # Number of seconds simulated
@@ -60,8 +60,8 @@ system.cpu0.dcache.demand_mshr_misses             345                       # nu
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0                  0.275846                       # Average percentage of cache occupancy
 system.cpu0.dcache.occ_blocks::0           141.233241                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.275846                       # Average percentage of cache occupancy
 system.cpu0.dcache.overall_accesses             73844                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_avg_miss_latency 34553.623188                       # average overall miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency 31553.623188                       # average overall mshr miss latency
@@ -115,8 +115,8 @@ system.cpu0.icache.demand_mshr_misses             467                       # nu
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0                  0.414998                       # Average percentage of cache occupancy
 system.cpu0.icache.occ_blocks::0           212.478999                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.414998                       # Average percentage of cache occupancy
 system.cpu0.icache.overall_accesses            158416                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_avg_miss_latency 39665.952891                       # average overall miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency 36665.952891                       # average overall mshr miss latency
@@ -159,7 +159,7 @@ system.cpu0.num_int_register_writes            110671                       # nu
 system.cpu0.num_load_insts                      48930                       # Number of load instructions
 system.cpu0.num_mem_refs                        73905                       # number of memory refs
 system.cpu0.num_store_insts                     24975                       # Number of store instructions
-system.cpu0.workload.PROG:num_syscalls             89                       # Number of system calls
+system.cpu0.workload.num_syscalls                  89                       # Number of system calls
 system.cpu1.dcache.ReadReq_accesses             38632                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_avg_miss_latency 20316.666667                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 17316.666667                       # average ReadReq mshr miss latency
@@ -212,10 +212,10 @@ system.cpu1.dcache.demand_mshr_misses             276                       # nu
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0                  0.052024                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_%::1                 -0.007792                       # Average percentage of cache occupancy
 system.cpu1.dcache.occ_blocks::0            26.636390                       # Average occupied blocks per context
 system.cpu1.dcache.occ_blocks::1            -3.989577                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.052024                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::1           -0.007792                       # Average percentage of cache occupancy
 system.cpu1.dcache.overall_accesses             46826                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_avg_miss_latency 19681.159420                       # average overall miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency 16681.159420                       # average overall mshr miss latency
@@ -269,8 +269,8 @@ system.cpu1.icache.demand_mshr_misses             358                       # nu
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0                  0.136637                       # Average percentage of cache occupancy
 system.cpu1.icache.occ_blocks::0            69.958167                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.136637                       # Average percentage of cache occupancy
 system.cpu1.icache.overall_accesses            168396                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_avg_miss_latency 21104.748603                       # average overall miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency 18103.351955                       # average overall mshr miss latency
@@ -365,10 +365,10 @@ system.cpu2.dcache.demand_mshr_misses             262                       # nu
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.occ_%::0                  0.048606                       # Average percentage of cache occupancy
-system.cpu2.dcache.occ_%::1                 -0.003199                       # Average percentage of cache occupancy
 system.cpu2.dcache.occ_blocks::0            24.886220                       # Average occupied blocks per context
 system.cpu2.dcache.occ_blocks::1            -1.638018                       # Average occupied blocks per context
+system.cpu2.dcache.occ_percent::0            0.048606                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::1           -0.003199                       # Average percentage of cache occupancy
 system.cpu2.dcache.overall_accesses             56889                       # number of overall (read+write) accesses
 system.cpu2.dcache.overall_avg_miss_latency 16950.381679                       # average overall miss latency
 system.cpu2.dcache.overall_avg_mshr_miss_latency 13950.381679                       # average overall mshr miss latency
@@ -422,8 +422,8 @@ system.cpu2.icache.demand_mshr_misses             358                       # nu
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.icache.occ_%::0                  0.127896                       # Average percentage of cache occupancy
 system.cpu2.icache.occ_blocks::0            65.482956                       # Average occupied blocks per context
+system.cpu2.icache.occ_percent::0            0.127896                       # Average percentage of cache occupancy
 system.cpu2.icache.overall_accesses            161568                       # number of overall (read+write) accesses
 system.cpu2.icache.overall_avg_miss_latency 14758.379888                       # average overall miss latency
 system.cpu2.icache.overall_avg_mshr_miss_latency 11758.379888                       # average overall mshr miss latency
@@ -518,10 +518,10 @@ system.cpu3.dcache.demand_mshr_misses             262                       # nu
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.occ_%::0                  0.050054                       # Average percentage of cache occupancy
-system.cpu3.dcache.occ_%::1                 -0.007034                       # Average percentage of cache occupancy
 system.cpu3.dcache.occ_blocks::0            25.627740                       # Average occupied blocks per context
 system.cpu3.dcache.occ_blocks::1            -3.601472                       # Average occupied blocks per context
+system.cpu3.dcache.occ_percent::0            0.050054                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::1           -0.007034                       # Average percentage of cache occupancy
 system.cpu3.dcache.overall_accesses             56189                       # number of overall (read+write) accesses
 system.cpu3.dcache.overall_avg_miss_latency 17095.419847                       # average overall miss latency
 system.cpu3.dcache.overall_avg_mshr_miss_latency 14095.419847                       # average overall mshr miss latency
@@ -575,8 +575,8 @@ system.cpu3.icache.demand_mshr_misses             359                       # nu
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.icache.occ_%::0                  0.132070                       # Average percentage of cache occupancy
 system.cpu3.icache.occ_blocks::0            67.619703                       # Average occupied blocks per context
+system.cpu3.icache.occ_percent::0            0.132070                       # Average percentage of cache occupancy
 system.cpu3.icache.overall_accesses            162202                       # number of overall (read+write) accesses
 system.cpu3.icache.overall_avg_miss_latency 14391.364903                       # average overall miss latency
 system.cpu3.icache.overall_avg_mshr_miss_latency 11391.364903                       # average overall mshr miss latency
@@ -764,16 +764,16 @@ system.l2c.demand_mshr_misses                     559                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.004365                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.000881                       # Average percentage of cache occupancy
-system.l2c.occ_%::2                          0.000040                       # Average percentage of cache occupancy
-system.l2c.occ_%::3                          0.000026                       # Average percentage of cache occupancy
-system.l2c.occ_%::4                          0.000085                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                   286.079338                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                    57.730266                       # Average occupied blocks per context
 system.l2c.occ_blocks::2                     2.608262                       # Average occupied blocks per context
 system.l2c.occ_blocks::3                     1.731871                       # Average occupied blocks per context
 system.l2c.occ_blocks::4                     5.597892                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.004365                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.000881                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.000040                       # Average percentage of cache occupancy
+system.l2c.occ_percent::3                    0.000026                       # Average percentage of cache occupancy
+system.l2c.occ_percent::4                    0.000085                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                    637                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                    383                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                    382                       # number of overall (read+write) accesses
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
index 296040009..9b858b847 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
@@ -507,6 +507,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
@@ -520,6 +521,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl1.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=1
 physMemPort=system.physmem.port[1]
@@ -533,6 +535,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl2.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=2
 physMemPort=system.physmem.port[2]
@@ -546,6 +549,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl3.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=3
 physMemPort=system.physmem.port[3]
@@ -559,6 +563,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl4.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=4
 physMemPort=system.physmem.port[4]
@@ -572,6 +577,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl5.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=5
 physMemPort=system.physmem.port[5]
@@ -585,6 +591,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl6.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=6
 physMemPort=system.physmem.port[6]
@@ -598,6 +605,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl7.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=7
 physMemPort=system.physmem.port[7]
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
index 4d13c8032..39ff9f957 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/08/2011 17:40:23
+Real time: Apr/19/2011 12:16:59
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 508
-Elapsed_time_in_minutes: 8.46667
-Elapsed_time_in_hours: 0.141111
-Elapsed_time_in_days: 0.00587963
+Elapsed_time_in_seconds: 259
+Elapsed_time_in_minutes: 4.31667
+Elapsed_time_in_hours: 0.0719444
+Elapsed_time_in_days: 0.00299769
 
-Virtual_time_in_seconds: 508.81
-Virtual_time_in_minutes: 8.48017
-Virtual_time_in_hours:   0.141336
-Virtual_time_in_days:    0.005889
+Virtual_time_in_seconds: 259.28
+Virtual_time_in_minutes: 4.32133
+Virtual_time_in_hours:   0.0720222
+Virtual_time_in_days:    0.00300093
 
 Ruby_current_time: 44606455
 Ruby_start_time: 0
 Ruby_cycles: 44606455
 
-mbytes_resident: 36.0898
-mbytes_total: 338.191
-resident_ratio: 0.106749
+mbytes_resident: 38.1133
+mbytes_total: 336.488
+resident_ratio: 0.113279
 
 ruby_cycles_executed: [ 44606456 44606456 44606456 44606456 44606456 44606456 44606456 44606456 ]
 
@@ -116,13 +116,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 1 count: 6455267 average: 5.1276e-05
 Resource Usage
 --------------
 page_size: 4096
-user_time: 508
+user_time: 259
 system_time: 0
-page_reclaims: 10505
+page_reclaims: 10092
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 216
 
 Network Stats
 -------------
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
index 959d8910e..cd85f5db7 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 17:31:51
-M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip
-M5 started Feb  8 2011 17:31:55
-M5 executing on SC2B0617
+M5 compiled Apr 19 2011 12:12:36
+M5 started Apr 19 2011 12:12:40
+M5 executing on maize
 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
index 393bd8a0f..c440dc6d4 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 346312                       # Number of bytes of host memory used
-host_seconds                                   508.61                       # Real time elapsed on the host
-host_tick_rate                                  87702                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 344568                       # Number of bytes of host memory used
+host_seconds                                   259.17                       # Real time elapsed on the host
+host_tick_rate                                 172115                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.044606                       # Number of seconds simulated
 sim_ticks                                    44606455                       # Number of ticks simulated
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
index d4f28799b..8991c3c8f 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
@@ -489,6 +489,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
@@ -502,6 +503,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl1.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=1
 physMemPort=system.physmem.port[1]
@@ -515,6 +517,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl2.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=2
 physMemPort=system.physmem.port[2]
@@ -528,6 +531,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl3.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=3
 physMemPort=system.physmem.port[3]
@@ -541,6 +545,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl4.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=4
 physMemPort=system.physmem.port[4]
@@ -554,6 +559,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl5.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=5
 physMemPort=system.physmem.port[5]
@@ -567,6 +573,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl6.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=6
 physMemPort=system.physmem.port[6]
@@ -580,6 +587,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl7.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=7
 physMemPort=system.physmem.port[7]
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
index 76098d4be..98b9d915b 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/08/2011 17:50:03
+Real time: Apr/19/2011 12:19:09
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 500
-Elapsed_time_in_minutes: 8.33333
-Elapsed_time_in_hours: 0.138889
-Elapsed_time_in_days: 0.00578704
+Elapsed_time_in_seconds: 257
+Elapsed_time_in_minutes: 4.28333
+Elapsed_time_in_hours: 0.0713889
+Elapsed_time_in_days: 0.00297454
 
-Virtual_time_in_seconds: 500.11
-Virtual_time_in_minutes: 8.33517
-Virtual_time_in_hours:   0.138919
-Virtual_time_in_days:    0.00578831
+Virtual_time_in_seconds: 257.26
+Virtual_time_in_minutes: 4.28767
+Virtual_time_in_hours:   0.0714611
+Virtual_time_in_days:    0.00297755
 
 Ruby_current_time: 38939096
 Ruby_start_time: 0
 Ruby_cycles: 38939096
 
-mbytes_resident: 36.1992
-mbytes_total: 338.434
-resident_ratio: 0.106984
+mbytes_resident: 38.2109
+mbytes_total: 336.34
+resident_ratio: 0.11362
 
 ruby_cycles_executed: [ 38939097 38939097 38939097 38939097 38939097 38939097 38939097 38939097 ]
 
@@ -116,13 +116,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
 Resource Usage
 --------------
 page_size: 4096
-user_time: 499
+user_time: 257
 system_time: 0
-page_reclaims: 10514
+page_reclaims: 10115
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 176
 
 Network Stats
 -------------
@@ -735,6 +735,7 @@ Writeback_Ack [1201719 ] 1201719
 Writeback_Nack [0 ] 0
 Unblock [21977 ] 21977
 Exclusive_Unblock [1213749 ] 1213749
+DmaAck [0 ] 0
 L2_Replacement [1209622 ] 1209622
 
  - Transitions -
@@ -1484,6 +1485,76 @@ ILSI  All_Acks [0 ] 0
 ILSI  Writeback_Ack [0 ] 0
 ILSI  L2_Replacement [0 ] 0
 
+ILOSD  L1_GETS [0 ] 0
+ILOSD  L1_GETX [0 ] 0
+ILOSD  L1_PUTO [0 ] 0
+ILOSD  L1_PUTX [0 ] 0
+ILOSD  L1_PUTS_only [0 ] 0
+ILOSD  L1_PUTS [0 ] 0
+ILOSD  Fwd_GETX [0 ] 0
+ILOSD  Fwd_GETS [0 ] 0
+ILOSD  Fwd_DMA [0 ] 0
+ILOSD  Own_GETX [0 ] 0
+ILOSD  Inv [0 ] 0
+ILOSD  DmaAck [0 ] 0
+ILOSD  L2_Replacement [0 ] 0
+
+ILOSXD  L1_GETS [0 ] 0
+ILOSXD  L1_GETX [0 ] 0
+ILOSXD  L1_PUTO [0 ] 0
+ILOSXD  L1_PUTX [0 ] 0
+ILOSXD  L1_PUTS_only [0 ] 0
+ILOSXD  L1_PUTS [0 ] 0
+ILOSXD  Fwd_GETX [0 ] 0
+ILOSXD  Fwd_GETS [0 ] 0
+ILOSXD  Fwd_DMA [0 ] 0
+ILOSXD  Own_GETX [0 ] 0
+ILOSXD  Inv [0 ] 0
+ILOSXD  DmaAck [0 ] 0
+ILOSXD  L2_Replacement [0 ] 0
+
+ILOD  L1_GETS [0 ] 0
+ILOD  L1_GETX [0 ] 0
+ILOD  L1_PUTO [0 ] 0
+ILOD  L1_PUTX [0 ] 0
+ILOD  L1_PUTS_only [0 ] 0
+ILOD  L1_PUTS [0 ] 0
+ILOD  Fwd_GETX [0 ] 0
+ILOD  Fwd_GETS [0 ] 0
+ILOD  Fwd_DMA [0 ] 0
+ILOD  Own_GETX [0 ] 0
+ILOD  Inv [0 ] 0
+ILOD  DmaAck [0 ] 0
+ILOD  L2_Replacement [0 ] 0
+
+ILXD  L1_GETS [0 ] 0
+ILXD  L1_GETX [0 ] 0
+ILXD  L1_PUTO [0 ] 0
+ILXD  L1_PUTX [0 ] 0
+ILXD  L1_PUTS_only [0 ] 0
+ILXD  L1_PUTS [0 ] 0
+ILXD  Fwd_GETX [0 ] 0
+ILXD  Fwd_GETS [0 ] 0
+ILXD  Fwd_DMA [0 ] 0
+ILXD  Own_GETX [0 ] 0
+ILXD  Inv [0 ] 0
+ILXD  DmaAck [0 ] 0
+ILXD  L2_Replacement [0 ] 0
+
+ILOXD  L1_GETS [0 ] 0
+ILOXD  L1_GETX [0 ] 0
+ILOXD  L1_PUTO [0 ] 0
+ILOXD  L1_PUTX [0 ] 0
+ILOXD  L1_PUTS_only [0 ] 0
+ILOXD  L1_PUTS [0 ] 0
+ILOXD  Fwd_GETX [0 ] 0
+ILOXD  Fwd_GETS [0 ] 0
+ILOXD  Fwd_DMA [0 ] 0
+ILOXD  Own_GETX [0 ] 0
+ILOXD  Inv [0 ] 0
+ILOXD  DmaAck [0 ] 0
+ILOXD  L2_Replacement [0 ] 0
+
 Memory controller: system.dir_cntrl0.memBuffer:
   memory_total_requests: 1633762
   memory_reads: 1206708
@@ -1520,6 +1591,7 @@ Memory_Data [1206704 ] 1206704
 Memory_Ack [427031 ] 427031
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
+DMA_ACK [0 ] 0
 Data [0 ] 0
 
  - Transitions -
@@ -1700,4 +1772,22 @@ OI_D  PUTO [0 ] 0
 OI_D  PUTO_SHARERS [0 ] 0
 OI_D  DMA_READ [0 ] 0
 OI_D  DMA_WRITE [0 ] 0
-OI_D  Data
\ No newline at end of file
+OI_D  Data [0 ] 0
+
+OD  GETX [0 ] 0
+OD  GETS [0 ] 0
+OD  PUTX [0 ] 0
+OD  PUTO [0 ] 0
+OD  PUTO_SHARERS [0 ] 0
+OD  DMA_READ [0 ] 0
+OD  DMA_WRITE [0 ] 0
+OD  DMA_ACK [0 ] 0
+
+MD  GETX [0 ] 0
+MD  GETS [0 ] 0
+MD  PUTX [0 ] 0
+MD  PUTO [0 ] 0
+MD  PUTO_SHARERS [0 ] 0
+MD  DMA_READ [0 ] 0
+MD  DMA_WRITE [0 ] 0
+MD  DMA_ACK
\ No newline at end of file
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
index 3251b74fa..31d2d5c8b 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 17:41:34
-M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
-M5 started Feb  8 2011 17:41:42
-M5 executing on SC2B0617
+M5 compiled Apr 19 2011 12:14:48
+M5 started Apr 19 2011 12:14:52
+M5 executing on maize
 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
index fd4797192..0fe996c73 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 346560                       # Number of bytes of host memory used
-host_seconds                                   500.03                       # Real time elapsed on the host
-host_tick_rate                                  77873                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 344416                       # Number of bytes of host memory used
+host_seconds                                   257.16                       # Real time elapsed on the host
+host_tick_rate                                 151420                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.038939                       # Number of seconds simulated
 sim_ticks                                    38939096                       # Number of ticks simulated
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
index b590b5da6..501bfcf2e 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Mar/26/2011 22:03:29
+Real time: Apr/19/2011 12:19:56
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 165
-Elapsed_time_in_minutes: 2.75
-Elapsed_time_in_hours: 0.0458333
-Elapsed_time_in_days: 0.00190972
+Elapsed_time_in_seconds: 160
+Elapsed_time_in_minutes: 2.66667
+Elapsed_time_in_hours: 0.0444444
+Elapsed_time_in_days: 0.00185185
 
-Virtual_time_in_seconds: 165.12
-Virtual_time_in_minutes: 2.752
-Virtual_time_in_hours:   0.0458667
-Virtual_time_in_days:    0.00191111
+Virtual_time_in_seconds: 160.29
+Virtual_time_in_minutes: 2.6715
+Virtual_time_in_hours:   0.044525
+Virtual_time_in_days:    0.00185521
 
 Ruby_current_time: 38958200
 Ruby_start_time: 0
 Ruby_cycles: 38958200
 
-mbytes_resident: 36.9609
-mbytes_total: 326.926
-resident_ratio: 0.113068
+mbytes_resident: 37.7383
+mbytes_total: 335.953
+resident_ratio: 0.112344
 
 ruby_cycles_executed: [ 38958201 38958201 38958201 38958201 38958201 38958201 38958201 38958201 ]
 
@@ -125,13 +125,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
 Resource Usage
 --------------
 page_size: 4096
-user_time: 165
+user_time: 160
 system_time: 0
-page_reclaims: 9802
+page_reclaims: 9997
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 120
+block_outputs: 176
 
 Network Stats
 -------------
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
index c1f0f4771..0757f7914 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 26 2011 14:06:20
-M5 started Mar 26 2011 22:00:43
-M5 executing on phenom
+M5 compiled Apr 19 2011 12:17:10
+M5 started Apr 19 2011 12:17:16
+M5 executing on maize
 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
index 4478d8c0a..241434b83 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 334776                       # Number of bytes of host memory used
-host_seconds                                   165.00                       # Real time elapsed on the host
-host_tick_rate                                 236117                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 344020                       # Number of bytes of host memory used
+host_seconds                                   160.21                       # Real time elapsed on the host
+host_tick_rate                                 243168                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.038958                       # Number of seconds simulated
 sim_ticks                                    38958200                       # Number of ticks simulated
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
index a9fd7817d..6af990dcd 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
@@ -568,6 +568,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
@@ -581,6 +582,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl1.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=1
 physMemPort=system.physmem.port[1]
@@ -594,6 +596,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl2.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=2
 physMemPort=system.physmem.port[2]
@@ -607,6 +610,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl3.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=3
 physMemPort=system.physmem.port[3]
@@ -620,6 +624,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl4.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=4
 physMemPort=system.physmem.port[4]
@@ -633,6 +638,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl5.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=5
 physMemPort=system.physmem.port[5]
@@ -646,6 +652,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl6.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=6
 physMemPort=system.physmem.port[6]
@@ -659,6 +666,7 @@ deadlock_threshold=1000000
 icache=system.l1_cntrl7.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=7
 physMemPort=system.physmem.port[7]
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
index 888bd781c..7284a0dce 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/23/2011 14:32:39
+Real time: Apr/19/2011 12:12:06
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 343
-Elapsed_time_in_minutes: 5.71667
-Elapsed_time_in_hours: 0.0952778
-Elapsed_time_in_days: 0.00396991
+Elapsed_time_in_seconds: 136
+Elapsed_time_in_minutes: 2.26667
+Elapsed_time_in_hours: 0.0377778
+Elapsed_time_in_days: 0.00157407
 
-Virtual_time_in_seconds: 266.4
-Virtual_time_in_minutes: 4.44
-Virtual_time_in_hours:   0.074
-Virtual_time_in_days:    0.00308333
+Virtual_time_in_seconds: 135.92
+Virtual_time_in_minutes: 2.26533
+Virtual_time_in_hours:   0.0377556
+Virtual_time_in_days:    0.00157315
 
 Ruby_current_time: 38170519
 Ruby_start_time: 0
 Ruby_cycles: 38170519
 
-mbytes_resident: 35.4453
-mbytes_total: 337.395
-resident_ratio: 0.105079
+mbytes_resident: 37.4531
+mbytes_total: 335.598
+resident_ratio: 0.111613
 
 ruby_cycles_executed: [ 38170520 38170520 38170520 38170520 38170520 38170520 38170520 38170520 ]
 
@@ -124,13 +124,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
 Resource Usage
 --------------
 page_size: 4096
-user_time: 265
+user_time: 135
 system_time: 0
-page_reclaims: 10328
+page_reclaims: 9924
 page_faults: 0
 swaps: 0
-block_inputs: 568
-block_outputs: 0
+block_inputs: 0
+block_outputs: 168
 
 Network Stats
 -------------
@@ -379,7 +379,7 @@ Cache Stats: system.l1_cntrl0.L1DcacheMemory
   system.l1_cntrl0.L1DcacheMemory_request_type_LD:   64.988%
   system.l1_cntrl0.L1DcacheMemory_request_type_ST:   35.012%
 
-  system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode:   153213    100%
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   153213    100%
 
 Cache Stats: system.l1_cntrl0.L2cacheMemory
   system.l1_cntrl0.L2cacheMemory_total_misses: 153213
@@ -391,7 +391,7 @@ Cache Stats: system.l1_cntrl0.L2cacheMemory
   system.l1_cntrl0.L2cacheMemory_request_type_LD:   64.988%
   system.l1_cntrl0.L2cacheMemory_request_type_ST:   35.012%
 
-  system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   153213    100%
+  system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   153213    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -411,13 +411,15 @@ NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 Invalidate [0 0 0 0 0 0 0 0 ] 0
 Ack [1066502 1065611 1070273 1066825 1066414 1070011 1068622 1066110 ] 8540368
 Shared_Ack [115 119 110 96 98 118 109 121 ] 886
-Data [5959 5967 5973 5842 5910 5904 5761 5814 ] 47130
-Shared_Data [2080 2145 2106 2083 2029 2073 2131 2053 ] 16700
+Data [5953 5964 5970 5839 5905 5902 5754 5810 ] 47097
+Shared_Data [2086 2148 2109 2086 2034 2075 2138 2057 ] 16733
 Exclusive_Data [145032 144875 145557 145214 145130 145617 145502 145154 ] 1162081
 Writeback_Ack [144148 143915 144662 144412 144342 144857 144660 144311 ] 1155307
 Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
-All_acks [2183 2248 2197 2165 2115 2175 2229 2160 ] 17472
-All_acks_no_sharers [150891 150740 151440 150974 150955 151420 151165 150862 ] 1208447
+All_acks [2189 2251 2200 2168 2120 2177 2236 2164 ] 17505
+All_acks_no_sharers [150885 150737 151437 150971 150950 151418 151158 150858 ] 1208414
+Flush_line [0 0 0 0 0 0 0 0 ] 0
+Block_Ack [0 0 0 0 0 0 0 0 ] 0
 
  - Transitions -
 I  Load [99750 99564 99937 99608 99480 99765 99511 99345 ] 796960
@@ -432,6 +434,7 @@ I  Other_GETS [693803 693943 693553 693953 693978 693842 694042 694198 ] 5551312
 I  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 I  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 I  Invalidate [0 0 0 0 0 0 0 0 ] 0
+I  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 S  Load [8 4 4 4 3 2 3 3 ] 31
 S  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -445,6 +448,7 @@ S  Other_GETS [112 114 109 105 125 103 116 102 ] 886
 S  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 S  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 S  Invalidate [0 0 0 0 0 0 0 0 ] 0
+S  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 O  Load [0 0 1 0 1 2 2 0 ] 6
 O  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -459,6 +463,7 @@ O  Merged_GETS [3 4 3 5 2 4 7 1 ] 29
 O  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 O  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 O  Invalidate [0 0 0 0 0 0 0 0 ] 0
+O  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 M  Load [47 50 34 38 49 45 60 45 ] 368
 M  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -473,6 +478,7 @@ M  Merged_GETS [2 0 3 5 0 1 4 4 ] 19
 M  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 M  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 M  Invalidate [0 0 0 0 0 0 0 0 ] 0
+M  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 MM  Load [27 16 26 24 17 31 22 21 ] 184
 MM  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -487,6 +493,7 @@ MM  Merged_GETS [3 0 2 3 1 1 2 3 ] 15
 MM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 MM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 MM  Invalidate [0 0 0 0 0 0 0 0 ] 0
+MM  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 IM  Load [0 0 0 0 0 0 0 0 ] 0
 IM  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -501,6 +508,7 @@ IM  Invalidate [0 0 0 0 0 0 0 0 ] 0
 IM  Ack [366480 366723 369003 367797 368111 369500 370499 368866 ] 2946979
 IM  Data [2025 2055 2056 2044 2059 2123 2028 2074 ] 16464
 IM  Exclusive_Data [51296 51369 51643 51488 51528 51709 51856 51601 ] 412490
+IM  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 SM  Load [0 0 0 0 0 0 0 0 ] 0
 SM  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -515,6 +523,7 @@ SM  Invalidate [0 0 0 0 0 0 0 0 ] 0
 SM  Ack [7 7 14 7 12 0 7 14 ] 68
 SM  Data [1 1 2 1 2 0 1 2 ] 10
 SM  Exclusive_Data [0 0 0 0 0 0 0 0 ] 0
+SM  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 OM  Load [0 0 0 0 0 0 0 0 ] 0
 OM  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -530,6 +539,7 @@ OM  Invalidate [0 0 0 0 0 0 0 0 ] 0
 OM  Ack [21 7 7 0 7 7 0 7 ] 56
 OM  All_acks [0 0 0 0 0 0 0 0 ] 0
 OM  All_acks_no_sharers [3 1 1 0 1 1 0 1 ] 8
+OM  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 ISM  Load [0 0 0 0 0 0 0 0 ] 0
 ISM  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -538,6 +548,7 @@ ISM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
 ISM  L1_to_L2 [17 6 0 0 0 0 0 0 ] 23
 ISM  Ack [66 76 43 31 35 38 34 51 ] 374
 ISM  All_acks_no_sharers [2026 2056 2058 2045 2061 2123 2029 2076 ] 16474
+ISM  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 M_W  Load [0 0 0 0 0 0 0 0 ] 0
 M_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -546,6 +557,7 @@ M_W  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
 M_W  L1_to_L2 [38 69 88 42 90 112 70 83 ] 592
 M_W  Ack [3352 3658 3551 3465 3460 3459 3415 3426 ] 27786
 M_W  All_acks_no_sharers [93736 93506 93914 93726 93602 93908 93646 93553 ] 749591
+M_W  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 MM_W  Load [0 0 0 0 0 0 0 0 ] 0
 MM_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -554,6 +566,7 @@ MM_W  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
 MM_W  L1_to_L2 [72 120 137 81 70 152 83 104 ] 819
 MM_W  Ack [5046 5371 5115 5121 5255 5486 4940 5149 ] 41483
 MM_W  All_acks_no_sharers [51296 51369 51643 51488 51528 51709 51856 51601 ] 412490
+MM_W  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 IS  Load [0 0 0 0 0 0 0 0 ] 0
 IS  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -567,9 +580,10 @@ IS  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 IS  Invalidate [0 0 0 0 0 0 0 0 ] 0
 IS  Ack [685197 683360 686266 683975 683583 685323 683273 682541 ] 5473518
 IS  Shared_Ack [107 110 101 89 94 113 104 114 ] 832
-IS  Data [3933 3911 3915 3797 3849 3781 3732 3738 ] 30656
-IS  Shared_Data [2080 2145 2106 2083 2029 2073 2131 2053 ] 16700
+IS  Data [3927 3908 3912 3794 3844 3779 3725 3734 ] 30623
+IS  Shared_Data [2086 2148 2109 2086 2034 2075 2138 2057 ] 16733
 IS  Exclusive_Data [93736 93506 93914 93726 93602 93908 93646 93553 ] 749591
+IS  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 SS  Load [0 0 0 0 0 0 0 0 ] 0
 SS  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -578,8 +592,9 @@ SS  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
 SS  L1_to_L2 [85 168 135 117 120 81 154 151 ] 1011
 SS  Ack [6333 6409 6274 6429 5951 6198 6454 6056 ] 50104
 SS  Shared_Ack [8 9 9 7 4 5 5 7 ] 54
-SS  All_acks [2183 2248 2197 2165 2115 2175 2229 2160 ] 17472
-SS  All_acks_no_sharers [3830 3808 3824 3715 3763 3679 3634 3631 ] 29884
+SS  All_acks [2189 2251 2200 2168 2120 2177 2236 2164 ] 17505
+SS  All_acks_no_sharers [3824 3805 3821 3712 3758 3677 3627 3627 ] 29851
+SS  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 OI  Load [1 0 1 0 0 0 1 0 ] 3
 OI  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -593,6 +608,7 @@ OI  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 OI  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 OI  Invalidate [0 0 0 0 0 0 0 0 ] 0
 OI  Writeback_Ack [2057 1993 2064 2063 2153 2000 2031 2064 ] 16425
+OI  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 MI  Load [16 24 21 18 21 11 18 16 ] 145
 MI  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -606,6 +622,7 @@ MI  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 MI  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 MI  Invalidate [0 0 0 0 0 0 0 0 ] 0
 MI  Writeback_Ack [142087 141920 142596 142344 142188 142855 142627 142243 ] 1138860
+MI  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 II  Load [0 0 0 0 0 0 0 0 ] 0
 II  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -619,6 +636,7 @@ II  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 II  Invalidate [0 0 0 0 0 0 0 0 ] 0
 II  Writeback_Ack [4 2 2 5 1 2 2 4 ] 22
 II  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
+II  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 IT  Load [4 3 0 1 0 1 4 1 ] 14
 IT  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -632,6 +650,7 @@ IT  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 IT  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 IT  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 IT  Invalidate [0 0 0 0 0 0 0 0 ] 0
+IT  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 ST  Load [0 1 3 3 1 3 2 0 ] 13
 ST  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -645,6 +664,7 @@ ST  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 ST  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 ST  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 ST  Invalidate [0 0 0 0 0 0 0 0 ] 0
+ST  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 OT  Load [3 0 2 0 0 1 0 1 ] 7
 OT  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -658,6 +678,7 @@ OT  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 OT  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 OT  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 OT  Invalidate [0 0 0 0 0 0 0 0 ] 0
+OT  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 MT  Load [42 47 46 36 41 44 49 36 ] 341
 MT  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -671,6 +692,7 @@ MT  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 MT  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 MT  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 MT  Invalidate [0 0 0 0 0 0 0 0 ] 0
+MT  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 MMT  Load [15 18 18 21 13 24 22 17 ] 148
 MMT  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -684,6 +706,94 @@ MMT  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 MMT  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
 MMT  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 MMT  Invalidate [0 0 0 0 0 0 0 0 ] 0
+MMT  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+MI_F  Load [0 0 0 0 0 0 0 0 ] 0
+MI_F  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MI_F  Store [0 0 0 0 0 0 0 0 ] 0
+MI_F  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+MI_F  Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
+MI_F  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+MM_F  Load [0 0 0 0 0 0 0 0 ] 0
+MM_F  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MM_F  Store [0 0 0 0 0 0 0 0 ] 0
+MM_F  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+MM_F  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+MM_F  Other_GETS [0 0 0 0 0 0 0 0 ] 0
+MM_F  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
+MM_F  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+MM_F  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+MM_F  Invalidate [0 0 0 0 0 0 0 0 ] 0
+MM_F  Ack [0 0 0 0 0 0 0 0 ] 0
+MM_F  All_acks [0 0 0 0 0 0 0 0 ] 0
+MM_F  All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0
+MM_F  Flush_line [0 0 0 0 0 0 0 0 ] 0
+MM_F  Block_Ack [0 0 0 0 0 0 0 0 ] 0
+
+IM_F  Load [0 0 0 0 0 0 0 0 ] 0
+IM_F  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IM_F  Store [0 0 0 0 0 0 0 0 ] 0
+IM_F  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+IM_F  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+IM_F  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+IM_F  Other_GETS [0 0 0 0 0 0 0 0 ] 0
+IM_F  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+IM_F  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+IM_F  Invalidate [0 0 0 0 0 0 0 0 ] 0
+IM_F  Ack [0 0 0 0 0 0 0 0 ] 0
+IM_F  Data [0 0 0 0 0 0 0 0 ] 0
+IM_F  Exclusive_Data [0 0 0 0 0 0 0 0 ] 0
+IM_F  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+ISM_F  Load [0 0 0 0 0 0 0 0 ] 0
+ISM_F  Ifetch [0 0 0 0 0 0 0 0 ] 0
+ISM_F  Store [0 0 0 0 0 0 0 0 ] 0
+ISM_F  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+ISM_F  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+ISM_F  Ack [0 0 0 0 0 0 0 0 ] 0
+ISM_F  All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0
+ISM_F  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+SM_F  Load [0 0 0 0 0 0 0 0 ] 0
+SM_F  Ifetch [0 0 0 0 0 0 0 0 ] 0
+SM_F  Store [0 0 0 0 0 0 0 0 ] 0
+SM_F  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+SM_F  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+SM_F  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+SM_F  Other_GETS [0 0 0 0 0 0 0 0 ] 0
+SM_F  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+SM_F  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+SM_F  Invalidate [0 0 0 0 0 0 0 0 ] 0
+SM_F  Ack [0 0 0 0 0 0 0 0 ] 0
+SM_F  Data [0 0 0 0 0 0 0 0 ] 0
+SM_F  Exclusive_Data [0 0 0 0 0 0 0 0 ] 0
+SM_F  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+OM_F  Load [0 0 0 0 0 0 0 0 ] 0
+OM_F  Ifetch [0 0 0 0 0 0 0 0 ] 0
+OM_F  Store [0 0 0 0 0 0 0 0 ] 0
+OM_F  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+OM_F  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+OM_F  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+OM_F  Other_GETS [0 0 0 0 0 0 0 0 ] 0
+OM_F  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
+OM_F  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+OM_F  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+OM_F  Invalidate [0 0 0 0 0 0 0 0 ] 0
+OM_F  Ack [0 0 0 0 0 0 0 0 ] 0
+OM_F  All_acks [0 0 0 0 0 0 0 0 ] 0
+OM_F  All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0
+OM_F  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+MM_WF  Load [0 0 0 0 0 0 0 0 ] 0
+MM_WF  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MM_WF  Store [0 0 0 0 0 0 0 0 ] 0
+MM_WF  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+MM_WF  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+MM_WF  Ack [0 0 0 0 0 0 0 0 ] 0
+MM_WF  All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0
+MM_WF  Flush_line [0 0 0 0 0 0 0 0 ] 0
 
 Cache Stats: system.l1_cntrl1.L1IcacheMemory
   system.l1_cntrl1.L1IcacheMemory_total_misses: 0
@@ -703,7 +813,7 @@ Cache Stats: system.l1_cntrl1.L1DcacheMemory
   system.l1_cntrl1.L1DcacheMemory_request_type_LD:   64.9565%
   system.l1_cntrl1.L1DcacheMemory_request_type_ST:   35.0435%
 
-  system.l1_cntrl1.L1DcacheMemory_access_mode_type_SupervisorMode:   153763    100%
+  system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor:   153763    100%
 
 Cache Stats: system.l1_cntrl1.L2cacheMemory
   system.l1_cntrl1.L2cacheMemory_total_misses: 153763
@@ -715,7 +825,7 @@ Cache Stats: system.l1_cntrl1.L2cacheMemory
   system.l1_cntrl1.L2cacheMemory_request_type_LD:   64.9565%
   system.l1_cntrl1.L2cacheMemory_request_type_ST:   35.0435%
 
-  system.l1_cntrl1.L2cacheMemory_access_mode_type_SupervisorMode:   153763    100%
+  system.l1_cntrl1.L2cacheMemory_access_mode_type_Supervisor:   153763    100%
 
 Cache Stats: system.l1_cntrl2.L1IcacheMemory
   system.l1_cntrl2.L1IcacheMemory_total_misses: 0
@@ -735,7 +845,7 @@ Cache Stats: system.l1_cntrl2.L1DcacheMemory
   system.l1_cntrl2.L1DcacheMemory_request_type_LD:   64.8703%
   system.l1_cntrl2.L1DcacheMemory_request_type_ST:   35.1297%
 
-  system.l1_cntrl2.L1DcacheMemory_access_mode_type_SupervisorMode:   153588    100%
+  system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor:   153588    100%
 
 Cache Stats: system.l1_cntrl2.L2cacheMemory
   system.l1_cntrl2.L2cacheMemory_total_misses: 153588
@@ -747,7 +857,7 @@ Cache Stats: system.l1_cntrl2.L2cacheMemory
   system.l1_cntrl2.L2cacheMemory_request_type_LD:   64.8703%
   system.l1_cntrl2.L2cacheMemory_request_type_ST:   35.1297%
 
-  system.l1_cntrl2.L2cacheMemory_access_mode_type_SupervisorMode:   153588    100%
+  system.l1_cntrl2.L2cacheMemory_access_mode_type_Supervisor:   153588    100%
 
 Cache Stats: system.l1_cntrl3.L1IcacheMemory
   system.l1_cntrl3.L1IcacheMemory_total_misses: 0
@@ -767,7 +877,7 @@ Cache Stats: system.l1_cntrl3.L1DcacheMemory
   system.l1_cntrl3.L1DcacheMemory_request_type_LD:   64.9158%
   system.l1_cntrl3.L1DcacheMemory_request_type_ST:   35.0842%
 
-  system.l1_cntrl3.L1DcacheMemory_access_mode_type_SupervisorMode:   153177    100%
+  system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor:   153177    100%
 
 Cache Stats: system.l1_cntrl3.L2cacheMemory
   system.l1_cntrl3.L2cacheMemory_total_misses: 153177
@@ -779,7 +889,7 @@ Cache Stats: system.l1_cntrl3.L2cacheMemory
   system.l1_cntrl3.L2cacheMemory_request_type_LD:   64.9158%
   system.l1_cntrl3.L2cacheMemory_request_type_ST:   35.0842%
 
-  system.l1_cntrl3.L2cacheMemory_access_mode_type_SupervisorMode:   153177    100%
+  system.l1_cntrl3.L2cacheMemory_access_mode_type_Supervisor:   153177    100%
 
 Cache Stats: system.l1_cntrl4.L1IcacheMemory
   system.l1_cntrl4.L1IcacheMemory_total_misses: 0
@@ -799,7 +909,7 @@ Cache Stats: system.l1_cntrl4.L1DcacheMemory
   system.l1_cntrl4.L1DcacheMemory_request_type_LD:   65.1631%
   system.l1_cntrl4.L1DcacheMemory_request_type_ST:   34.8369%
 
-  system.l1_cntrl4.L1DcacheMemory_access_mode_type_SupervisorMode:   153237    100%
+  system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor:   153237    100%
 
 Cache Stats: system.l1_cntrl4.L2cacheMemory
   system.l1_cntrl4.L2cacheMemory_total_misses: 153237
@@ -811,7 +921,7 @@ Cache Stats: system.l1_cntrl4.L2cacheMemory
   system.l1_cntrl4.L2cacheMemory_request_type_LD:   65.1631%
   system.l1_cntrl4.L2cacheMemory_request_type_ST:   34.8369%
 
-  system.l1_cntrl4.L2cacheMemory_access_mode_type_SupervisorMode:   153237    100%
+  system.l1_cntrl4.L2cacheMemory_access_mode_type_Supervisor:   153237    100%
 
 Cache Stats: system.l1_cntrl5.L1IcacheMemory
   system.l1_cntrl5.L1IcacheMemory_total_misses: 0
@@ -831,7 +941,7 @@ Cache Stats: system.l1_cntrl5.L1DcacheMemory
   system.l1_cntrl5.L1DcacheMemory_request_type_LD:   65.0802%
   system.l1_cntrl5.L1DcacheMemory_request_type_ST:   34.9198%
 
-  system.l1_cntrl5.L1DcacheMemory_access_mode_type_SupervisorMode:   153154    100%
+  system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor:   153154    100%
 
 Cache Stats: system.l1_cntrl5.L2cacheMemory
   system.l1_cntrl5.L2cacheMemory_total_misses: 153154
@@ -843,7 +953,7 @@ Cache Stats: system.l1_cntrl5.L2cacheMemory
   system.l1_cntrl5.L2cacheMemory_request_type_LD:   65.0802%
   system.l1_cntrl5.L2cacheMemory_request_type_ST:   34.9198%
 
-  system.l1_cntrl5.L2cacheMemory_access_mode_type_SupervisorMode:   153154    100%
+  system.l1_cntrl5.L2cacheMemory_access_mode_type_Supervisor:   153154    100%
 
 Cache Stats: system.l1_cntrl6.L1IcacheMemory
   system.l1_cntrl6.L1IcacheMemory_total_misses: 0
@@ -863,7 +973,7 @@ Cache Stats: system.l1_cntrl6.L1DcacheMemory
   system.l1_cntrl6.L1DcacheMemory_request_type_LD:   65.0437%
   system.l1_cntrl6.L1DcacheMemory_request_type_ST:   34.9563%
 
-  system.l1_cntrl6.L1DcacheMemory_access_mode_type_SupervisorMode:   153815    100%
+  system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor:   153815    100%
 
 Cache Stats: system.l1_cntrl6.L2cacheMemory
   system.l1_cntrl6.L2cacheMemory_total_misses: 153815
@@ -875,7 +985,7 @@ Cache Stats: system.l1_cntrl6.L2cacheMemory
   system.l1_cntrl6.L2cacheMemory_request_type_LD:   65.0437%
   system.l1_cntrl6.L2cacheMemory_request_type_ST:   34.9563%
 
-  system.l1_cntrl6.L2cacheMemory_access_mode_type_SupervisorMode:   153815    100%
+  system.l1_cntrl6.L2cacheMemory_access_mode_type_Supervisor:   153815    100%
 
 Cache Stats: system.l1_cntrl7.L1IcacheMemory
   system.l1_cntrl7.L1IcacheMemory_total_misses: 0
@@ -895,7 +1005,7 @@ Cache Stats: system.l1_cntrl7.L1DcacheMemory
   system.l1_cntrl7.L1DcacheMemory_request_type_LD:   65.0441%
   system.l1_cntrl7.L1DcacheMemory_request_type_ST:   34.9559%
 
-  system.l1_cntrl7.L1DcacheMemory_access_mode_type_SupervisorMode:   153279    100%
+  system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor:   153279    100%
 
 Cache Stats: system.l1_cntrl7.L2cacheMemory
   system.l1_cntrl7.L2cacheMemory_total_misses: 153279
@@ -907,7 +1017,7 @@ Cache Stats: system.l1_cntrl7.L2cacheMemory
   system.l1_cntrl7.L2cacheMemory_request_type_LD:   65.0441%
   system.l1_cntrl7.L2cacheMemory_request_type_ST:   34.9559%
 
-  system.l1_cntrl7.L2cacheMemory_access_mode_type_SupervisorMode:   153279    100%
+  system.l1_cntrl7.L2cacheMemory_access_mode_type_Supervisor:   153279    100%
 
 Cache Stats: system.dir_cntrl0.probeFilter
   system.dir_cntrl0.probeFilter_total_misses: 0
@@ -963,6 +1073,8 @@ All_acks_and_shared_data [0 ] 0
 All_acks_and_owner_data [0 ] 0
 All_acks_and_data_no_sharers [0 ] 0
 All_Unblocks [64 ] 64
+GETF [0 ] 0
+PUTF [0 ] 0
 
  - Transitions -
 NX  GETX [114 ] 114
@@ -971,6 +1083,7 @@ NX  PUT [16446 ] 16446
 NX  Pf_Replacement [0 ] 0
 NX  DMA_READ [0 ] 0
 NX  DMA_WRITE [0 ] 0
+NX  GETF [0 ] 0
 
 NO  GETX [13808 ] 13808
 NO  GETS [25807 ] 25807
@@ -978,6 +1091,7 @@ NO  PUT [1138861 ] 1138861
 NO  Pf_Replacement [0 ] 0
 NO  DMA_READ [0 ] 0
 NO  DMA_WRITE [0 ] 0
+NO  GETF [0 ] 0
 
 S  GETX [0 ] 0
 S  GETS [0 ] 0
@@ -985,6 +1099,7 @@ S  PUT [0 ] 0
 S  Pf_Replacement [0 ] 0
 S  DMA_READ [0 ] 0
 S  DMA_WRITE [0 ] 0
+S  GETF [0 ] 0
 
 O  GETX [16346 ] 16346
 O  GETS [30623 ] 30623
@@ -992,12 +1107,14 @@ O  PUT [0 ] 0
 O  Pf_Replacement [0 ] 0
 O  DMA_READ [0 ] 0
 O  DMA_WRITE [0 ] 0
+O  GETF [0 ] 0
 
 E  GETX [398716 ] 398716
 E  GETS [740301 ] 740301
 E  PUT [0 ] 0
 E  DMA_READ [0 ] 0
 E  DMA_WRITE [0 ] 0
+E  GETF [0 ] 0
 
 O_R  GETX [0 ] 0
 O_R  GETS [0 ] 0
@@ -1007,6 +1124,7 @@ O_R  DMA_READ [0 ] 0
 O_R  DMA_WRITE [0 ] 0
 O_R  Ack [0 ] 0
 O_R  All_acks_and_data_no_sharers [0 ] 0
+O_R  GETF [0 ] 0
 
 S_R  GETX [0 ] 0
 S_R  GETS [0 ] 0
@@ -1017,6 +1135,7 @@ S_R  DMA_WRITE [0 ] 0
 S_R  Ack [0 ] 0
 S_R  Data [0 ] 0
 S_R  All_acks_and_data_no_sharers [0 ] 0
+S_R  GETF [0 ] 0
 
 NO_R  GETX [0 ] 0
 NO_R  GETS [0 ] 0
@@ -1028,6 +1147,7 @@ NO_R  Ack [0 ] 0
 NO_R  Data [0 ] 0
 NO_R  Exclusive_Data [0 ] 0
 NO_R  All_acks_and_data_no_sharers [0 ] 0
+NO_R  GETF [0 ] 0
 
 NO_B  GETX [31 ] 31
 NO_B  GETS [64 ] 64
@@ -1037,6 +1157,7 @@ NO_B  UnblockM [1178502 ] 1178502
 NO_B  Pf_Replacement [0 ] 0
 NO_B  DMA_READ [0 ] 0
 NO_B  DMA_WRITE [0 ] 0
+NO_B  GETF [0 ] 0
 
 NO_B_X  GETX [0 ] 0
 NO_B_X  GETS [0 ] 0
@@ -1046,6 +1167,7 @@ NO_B_X  UnblockM [26 ] 26
 NO_B_X  Pf_Replacement [0 ] 0
 NO_B_X  DMA_READ [0 ] 0
 NO_B_X  DMA_WRITE [0 ] 0
+NO_B_X  GETF [0 ] 0
 
 NO_B_S  GETX [0 ] 0
 NO_B_S  GETS [0 ] 0
@@ -1055,6 +1177,7 @@ NO_B_S  UnblockM [34 ] 34
 NO_B_S  Pf_Replacement [0 ] 0
 NO_B_S  DMA_READ [0 ] 0
 NO_B_S  DMA_WRITE [0 ] 0
+NO_B_S  GETF [0 ] 0
 
 NO_B_S_W  GETX [0 ] 0
 NO_B_S_W  GETS [0 ] 0
@@ -1064,6 +1187,7 @@ NO_B_S_W  Pf_Replacement [0 ] 0
 NO_B_S_W  DMA_READ [0 ] 0
 NO_B_S_W  DMA_WRITE [0 ] 0
 NO_B_S_W  All_Unblocks [64 ] 64
+NO_B_S_W  GETF [0 ] 0
 
 O_B  GETX [0 ] 0
 O_B  GETS [0 ] 0
@@ -1073,6 +1197,7 @@ O_B  UnblockM [0 ] 0
 O_B  Pf_Replacement [0 ] 0
 O_B  DMA_READ [0 ] 0
 O_B  DMA_WRITE [0 ] 0
+O_B  GETF [0 ] 0
 
 NO_B_W  GETX [3987 ] 3987
 NO_B_W  GETS [7416 ] 7416
@@ -1083,6 +1208,7 @@ NO_B_W  Pf_Replacement [0 ] 0
 NO_B_W  DMA_READ [0 ] 0
 NO_B_W  DMA_WRITE [0 ] 0
 NO_B_W  Memory_Data [1155339 ] 1155339
+NO_B_W  GETF [0 ] 0
 
 O_B_W  GETX [95 ] 95
 O_B_W  GETS [209 ] 209
@@ -1092,6 +1218,7 @@ O_B_W  Pf_Replacement [0 ] 0
 O_B_W  DMA_READ [0 ] 0
 O_B_W  DMA_WRITE [0 ] 0
 O_B_W  Memory_Data [30623 ] 30623
+O_B_W  GETF [0 ] 0
 
 NO_W  GETX [0 ] 0
 NO_W  GETS [0 ] 0
@@ -1100,6 +1227,7 @@ NO_W  Pf_Replacement [0 ] 0
 NO_W  DMA_READ [0 ] 0
 NO_W  DMA_WRITE [0 ] 0
 NO_W  Memory_Data [0 ] 0
+NO_W  GETF [0 ] 0
 
 O_W  GETX [0 ] 0
 O_W  GETS [0 ] 0
@@ -1108,6 +1236,7 @@ O_W  Pf_Replacement [0 ] 0
 O_W  DMA_READ [0 ] 0
 O_W  DMA_WRITE [0 ] 0
 O_W  Memory_Data [0 ] 0
+O_W  GETF [0 ] 0
 
 NO_DW_B_W  GETX [0 ] 0
 NO_DW_B_W  GETS [0 ] 0
@@ -1119,6 +1248,7 @@ NO_DW_B_W  Ack [0 ] 0
 NO_DW_B_W  Data [0 ] 0
 NO_DW_B_W  Exclusive_Data [0 ] 0
 NO_DW_B_W  All_acks_and_data_no_sharers [0 ] 0
+NO_DW_B_W  GETF [0 ] 0
 
 NO_DR_B_W  GETX [0 ] 0
 NO_DR_B_W  GETS [0 ] 0
@@ -1132,6 +1262,7 @@ NO_DR_B_W  Shared_Ack [0 ] 0
 NO_DR_B_W  Shared_Data [0 ] 0
 NO_DR_B_W  Data [0 ] 0
 NO_DR_B_W  Exclusive_Data [0 ] 0
+NO_DR_B_W  GETF [0 ] 0
 
 NO_DR_B_D  GETX [0 ] 0
 NO_DR_B_D  GETS [0 ] 0
@@ -1147,6 +1278,7 @@ NO_DR_B_D  Exclusive_Data [0 ] 0
 NO_DR_B_D  All_acks_and_shared_data [0 ] 0
 NO_DR_B_D  All_acks_and_owner_data [0 ] 0
 NO_DR_B_D  All_acks_and_data_no_sharers [0 ] 0
+NO_DR_B_D  GETF [0 ] 0
 
 NO_DR_B  GETX [0 ] 0
 NO_DR_B  GETS [0 ] 0
@@ -1162,6 +1294,7 @@ NO_DR_B  Exclusive_Data [0 ] 0
 NO_DR_B  All_acks_and_shared_data [0 ] 0
 NO_DR_B  All_acks_and_owner_data [0 ] 0
 NO_DR_B  All_acks_and_data_no_sharers [0 ] 0
+NO_DR_B  GETF [0 ] 0
 
 NO_DW_W  GETX [0 ] 0
 NO_DW_W  GETS [0 ] 0
@@ -1170,6 +1303,7 @@ NO_DW_W  Pf_Replacement [0 ] 0
 NO_DW_W  DMA_READ [0 ] 0
 NO_DW_W  DMA_WRITE [0 ] 0
 NO_DW_W  Memory_Ack [0 ] 0
+NO_DW_W  GETF [0 ] 0
 
 O_DR_B_W  GETX [0 ] 0
 O_DR_B_W  GETS [0 ] 0
@@ -1180,6 +1314,7 @@ O_DR_B_W  DMA_WRITE [0 ] 0
 O_DR_B_W  Memory_Data [0 ] 0
 O_DR_B_W  Ack [0 ] 0
 O_DR_B_W  Shared_Ack [0 ] 0
+O_DR_B_W  GETF [0 ] 0
 
 O_DR_B  GETX [0 ] 0
 O_DR_B  GETS [0 ] 0
@@ -1191,6 +1326,7 @@ O_DR_B  Ack [0 ] 0
 O_DR_B  Shared_Ack [0 ] 0
 O_DR_B  All_acks_and_owner_data [0 ] 0
 O_DR_B  All_acks_and_data_no_sharers [0 ] 0
+O_DR_B  GETF [0 ] 0
 
 WB  GETX [160 ] 160
 WB  GETS [342 ] 342
@@ -1203,6 +1339,7 @@ WB  Writeback_Exclusive_Dirty [423817 ] 423817
 WB  Pf_Replacement [0 ] 0
 WB  DMA_READ [0 ] 0
 WB  DMA_WRITE [0 ] 0
+WB  GETF [0 ] 0
 
 WB_O_W  GETX [2 ] 2
 WB_O_W  GETS [2 ] 2
@@ -1211,6 +1348,7 @@ WB_O_W  Pf_Replacement [0 ] 0
 WB_O_W  DMA_READ [0 ] 0
 WB_O_W  DMA_WRITE [0 ] 0
 WB_O_W  Memory_Ack [178 ] 178
+WB_O_W  GETF [0 ] 0
 
 WB_E_W  GETX [2043 ] 2043
 WB_E_W  GETS [3853 ] 3853
@@ -1218,4 +1356,22 @@ WB_E_W  PUT [0 ] 0
 WB_E_W  Pf_Replacement [0 ] 0
 WB_E_W  DMA_READ [0 ] 0
 WB_E_W  DMA_WRITE [0 ] 0
-WB_E_W  Memory_Ack
\ No newline at end of file
+WB_E_W  Memory_Ack [423803 ] 423803
+WB_E_W  GETF [0 ] 0
+
+NO_F  GETX [0 ] 0
+NO_F  GETS [0 ] 0
+NO_F  PUT [0 ] 0
+NO_F  UnblockM [0 ] 0
+NO_F  Pf_Replacement [0 ] 0
+NO_F  GETF [0 ] 0
+NO_F  PUTF [0 ] 0
+
+NO_F_W  GETX [0 ] 0
+NO_F_W  GETS [0 ] 0
+NO_F_W  PUT [0 ] 0
+NO_F_W  Pf_Replacement [0 ] 0
+NO_F_W  DMA_READ [0 ] 0
+NO_F_W  DMA_WRITE [0 ] 0
+NO_F_W  Memory_Data [0 ] 0
+NO_F_W  GETF
\ No newline at end of file
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
index 0b831185e..6966ae27c 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 23 2011 14:26:24
-M5 revision eb0a69dd3744+ 8057+ default brad/auto_permission_setting qtip tip
-M5 started Feb 23 2011 14:26:56
-M5 executing on svnxelk05
+M5 compiled Apr 19 2011 12:09:47
+M5 started Apr 19 2011 12:09:50
+M5 executing on maize
 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
index cd8805c8c..cbff57068 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 345496                       # Number of bytes of host memory used
-host_seconds                                   342.43                       # Real time elapsed on the host
-host_tick_rate                                 111469                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 343656                       # Number of bytes of host memory used
+host_seconds                                   135.85                       # Real time elapsed on the host
+host_tick_rate                                 280979                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.038171                       # Number of seconds simulated
 sim_ticks                                    38170519                       # Number of ticks simulated
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index 499a69fa0..8241c3c55 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -393,10 +393,11 @@ tracer=system.ruby.tracer
 type=RubySequencer
 access_phys_mem=true
 dcache=system.l1_cntrl0.cacheMemory
-deadlock_threshold=500000
+deadlock_threshold=1000000
 icache=system.l1_cntrl0.cacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
@@ -406,10 +407,11 @@ port=system.cpu0.test
 type=RubySequencer
 access_phys_mem=true
 dcache=system.l1_cntrl1.cacheMemory
-deadlock_threshold=500000
+deadlock_threshold=1000000
 icache=system.l1_cntrl1.cacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=1
 physMemPort=system.physmem.port[1]
@@ -419,10 +421,11 @@ port=system.cpu1.test
 type=RubySequencer
 access_phys_mem=true
 dcache=system.l1_cntrl2.cacheMemory
-deadlock_threshold=500000
+deadlock_threshold=1000000
 icache=system.l1_cntrl2.cacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=2
 physMemPort=system.physmem.port[2]
@@ -432,10 +435,11 @@ port=system.cpu2.test
 type=RubySequencer
 access_phys_mem=true
 dcache=system.l1_cntrl3.cacheMemory
-deadlock_threshold=500000
+deadlock_threshold=1000000
 icache=system.l1_cntrl3.cacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=3
 physMemPort=system.physmem.port[3]
@@ -445,10 +449,11 @@ port=system.cpu3.test
 type=RubySequencer
 access_phys_mem=true
 dcache=system.l1_cntrl4.cacheMemory
-deadlock_threshold=500000
+deadlock_threshold=1000000
 icache=system.l1_cntrl4.cacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=4
 physMemPort=system.physmem.port[4]
@@ -458,10 +463,11 @@ port=system.cpu4.test
 type=RubySequencer
 access_phys_mem=true
 dcache=system.l1_cntrl5.cacheMemory
-deadlock_threshold=500000
+deadlock_threshold=1000000
 icache=system.l1_cntrl5.cacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=5
 physMemPort=system.physmem.port[5]
@@ -471,10 +477,11 @@ port=system.cpu5.test
 type=RubySequencer
 access_phys_mem=true
 dcache=system.l1_cntrl6.cacheMemory
-deadlock_threshold=500000
+deadlock_threshold=1000000
 icache=system.l1_cntrl6.cacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=6
 physMemPort=system.physmem.port[6]
@@ -484,10 +491,11 @@ port=system.cpu6.test
 type=RubySequencer
 access_phys_mem=true
 dcache=system.l1_cntrl7.cacheMemory
-deadlock_threshold=500000
+deadlock_threshold=1000000
 icache=system.l1_cntrl7.cacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=false
 version=7
 physMemPort=system.physmem.port[7]
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
index 86ac84392..e3b1fbd94 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/07/2011 01:50:48
+Real time: Apr/19/2011 11:59:23
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 190
-Elapsed_time_in_minutes: 3.16667
-Elapsed_time_in_hours: 0.0527778
-Elapsed_time_in_days: 0.00219907
+Elapsed_time_in_seconds: 48
+Elapsed_time_in_minutes: 0.8
+Elapsed_time_in_hours: 0.0133333
+Elapsed_time_in_days: 0.000555556
 
-Virtual_time_in_seconds: 99.44
-Virtual_time_in_minutes: 1.65733
-Virtual_time_in_hours:   0.0276222
-Virtual_time_in_days:    0.00115093
+Virtual_time_in_seconds: 47.95
+Virtual_time_in_minutes: 0.799167
+Virtual_time_in_hours:   0.0133194
+Virtual_time_in_days:    0.000554977
 
 Ruby_current_time: 57251340
 Ruby_start_time: 0
 Ruby_cycles: 57251340
 
-mbytes_resident: 36.6133
-mbytes_total: 355.375
-resident_ratio: 0.103038
+mbytes_resident: 37.5156
+mbytes_total: 335.734
+resident_ratio: 0.111754
 
 ruby_cycles_executed: [ 57251341 57251341 57251341 57251341 57251341 57251341 57251341 57251341 ]
 
@@ -118,13 +118,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 2458515 average: 0.00032173
 Resource Usage
 --------------
 page_size: 4096
-user_time: 99
+user_time: 47
 system_time: 0
-page_reclaims: 10455
+page_reclaims: 9943
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 112
+block_outputs: 104
 
 Network Stats
 -------------
@@ -284,7 +284,7 @@ Cache Stats: system.l1_cntrl0.cacheMemory
   system.l1_cntrl0.cacheMemory_request_type_LD:   65.2232%
   system.l1_cntrl0.cacheMemory_request_type_ST:   34.7768%
 
-  system.l1_cntrl0.cacheMemory_access_mode_type_SupervisorMode:   153154    100%
+  system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor:   153154    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -335,7 +335,7 @@ Cache Stats: system.l1_cntrl1.cacheMemory
   system.l1_cntrl1.cacheMemory_request_type_LD:   64.9786%
   system.l1_cntrl1.cacheMemory_request_type_ST:   35.0214%
 
-  system.l1_cntrl1.cacheMemory_access_mode_type_SupervisorMode:   153355    100%
+  system.l1_cntrl1.cacheMemory_access_mode_type_Supervisor:   153355    100%
 
 Cache Stats: system.l1_cntrl2.cacheMemory
   system.l1_cntrl2.cacheMemory_total_misses: 153381
@@ -347,7 +347,7 @@ Cache Stats: system.l1_cntrl2.cacheMemory
   system.l1_cntrl2.cacheMemory_request_type_LD:   65.0433%
   system.l1_cntrl2.cacheMemory_request_type_ST:   34.9567%
 
-  system.l1_cntrl2.cacheMemory_access_mode_type_SupervisorMode:   153381    100%
+  system.l1_cntrl2.cacheMemory_access_mode_type_Supervisor:   153381    100%
 
 Cache Stats: system.l1_cntrl3.cacheMemory
   system.l1_cntrl3.cacheMemory_total_misses: 153389
@@ -359,7 +359,7 @@ Cache Stats: system.l1_cntrl3.cacheMemory
   system.l1_cntrl3.cacheMemory_request_type_LD:   64.9884%
   system.l1_cntrl3.cacheMemory_request_type_ST:   35.0116%
 
-  system.l1_cntrl3.cacheMemory_access_mode_type_SupervisorMode:   153389    100%
+  system.l1_cntrl3.cacheMemory_access_mode_type_Supervisor:   153389    100%
 
 Cache Stats: system.l1_cntrl4.cacheMemory
   system.l1_cntrl4.cacheMemory_total_misses: 153758
@@ -371,7 +371,7 @@ Cache Stats: system.l1_cntrl4.cacheMemory
   system.l1_cntrl4.cacheMemory_request_type_LD:   64.9436%
   system.l1_cntrl4.cacheMemory_request_type_ST:   35.0564%
 
-  system.l1_cntrl4.cacheMemory_access_mode_type_SupervisorMode:   153758    100%
+  system.l1_cntrl4.cacheMemory_access_mode_type_Supervisor:   153758    100%
 
 Cache Stats: system.l1_cntrl5.cacheMemory
   system.l1_cntrl5.cacheMemory_total_misses: 153613
@@ -383,7 +383,7 @@ Cache Stats: system.l1_cntrl5.cacheMemory
   system.l1_cntrl5.cacheMemory_request_type_LD:   65.1%
   system.l1_cntrl5.cacheMemory_request_type_ST:   34.9%
 
-  system.l1_cntrl5.cacheMemory_access_mode_type_SupervisorMode:   153613    100%
+  system.l1_cntrl5.cacheMemory_access_mode_type_Supervisor:   153613    100%
 
 Cache Stats: system.l1_cntrl6.cacheMemory
   system.l1_cntrl6.cacheMemory_total_misses: 153962
@@ -395,7 +395,7 @@ Cache Stats: system.l1_cntrl6.cacheMemory
   system.l1_cntrl6.cacheMemory_request_type_LD:   64.8465%
   system.l1_cntrl6.cacheMemory_request_type_ST:   35.1535%
 
-  system.l1_cntrl6.cacheMemory_access_mode_type_SupervisorMode:   153962    100%
+  system.l1_cntrl6.cacheMemory_access_mode_type_Supervisor:   153962    100%
 
 Cache Stats: system.l1_cntrl7.cacheMemory
   system.l1_cntrl7.cacheMemory_total_misses: 152712
@@ -407,7 +407,7 @@ Cache Stats: system.l1_cntrl7.cacheMemory
   system.l1_cntrl7.cacheMemory_request_type_LD:   64.9484%
   system.l1_cntrl7.cacheMemory_request_type_ST:   35.0516%
 
-  system.l1_cntrl7.cacheMemory_access_mode_type_SupervisorMode:   152712    100%
+  system.l1_cntrl7.cacheMemory_access_mode_type_Supervisor:   152712    100%
 
 Memory controller: system.dir_cntrl0.memBuffer:
   memory_total_requests: 2421588
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
index 1c1816479..521945e53 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:38
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:35
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index 4df469f73..25988127e 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 363908                       # Number of bytes of host memory used
-host_seconds                                   189.81                       # Real time elapsed on the host
-host_tick_rate                                 301617                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 343796                       # Number of bytes of host memory used
+host_seconds                                    47.85                       # Real time elapsed on the host
+host_tick_rate                                1196434                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.057251                       # Number of seconds simulated
 sim_ticks                                    57251340                       # Number of ticks simulated
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
index 4e966d986..fd178ee5f 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -42,6 +42,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
@@ -90,6 +91,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
@@ -138,6 +140,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
@@ -186,6 +189,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
@@ -234,6 +238,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
@@ -282,6 +287,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
@@ -330,6 +336,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
@@ -378,6 +385,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
@@ -419,6 +427,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
index f3966712d..7ecac9f9f 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:38
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:24
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
index cebf442c3..740dd0fe1 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 349812                       # Number of bytes of host memory used
-host_seconds                                   357.32                       # Real time elapsed on the host
-host_tick_rate                                 737410                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 329728                       # Number of bytes of host memory used
+host_seconds                                   115.41                       # Real time elapsed on the host
+host_tick_rate                                2283081                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000263                       # Number of seconds simulated
 sim_ticks                                   263488655                       # Number of ticks simulated
@@ -52,10 +52,10 @@ system.cpu0.l1c.demand_mshr_misses              60481                       # nu
 system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu0.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu0.l1c.occ_%::0                     0.678383                       # Average percentage of cache occupancy
-system.cpu0.l1c.occ_%::1                    -0.477715                       # Average percentage of cache occupancy
 system.cpu0.l1c.occ_blocks::0              347.331950                       # Average occupied blocks per context
 system.cpu0.l1c.occ_blocks::1             -244.589945                       # Average occupied blocks per context
+system.cpu0.l1c.occ_percent::0               0.678383                       # Average percentage of cache occupancy
+system.cpu0.l1c.occ_percent::1              -0.477715                       # Average percentage of cache occupancy
 system.cpu0.l1c.overall_accesses                69070                       # number of overall (read+write) accesses
 system.cpu0.l1c.overall_avg_miss_latency 38047.907822                       # average overall miss latency
 system.cpu0.l1c.overall_avg_mshr_miss_latency 37044.022156                       # average overall mshr miss latency
@@ -126,10 +126,10 @@ system.cpu1.l1c.demand_mshr_misses              60385                       # nu
 system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu1.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu1.l1c.occ_%::0                     0.675110                       # Average percentage of cache occupancy
-system.cpu1.l1c.occ_%::1                    -0.493432                       # Average percentage of cache occupancy
 system.cpu1.l1c.occ_blocks::0              345.656340                       # Average occupied blocks per context
 system.cpu1.l1c.occ_blocks::1             -252.637366                       # Average occupied blocks per context
+system.cpu1.l1c.occ_percent::0               0.675110                       # Average percentage of cache occupancy
+system.cpu1.l1c.occ_percent::1              -0.493432                       # Average percentage of cache occupancy
 system.cpu1.l1c.overall_accesses                68880                       # number of overall (read+write) accesses
 system.cpu1.l1c.overall_avg_miss_latency 38354.853291                       # average overall miss latency
 system.cpu1.l1c.overall_avg_mshr_miss_latency 37351.034793                       # average overall mshr miss latency
@@ -200,10 +200,10 @@ system.cpu2.l1c.demand_mshr_misses              60029                       # nu
 system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu2.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu2.l1c.occ_%::0                     0.674668                       # Average percentage of cache occupancy
-system.cpu2.l1c.occ_%::1                    -0.509877                       # Average percentage of cache occupancy
 system.cpu2.l1c.occ_blocks::0              345.430231                       # Average occupied blocks per context
 system.cpu2.l1c.occ_blocks::1             -261.057119                       # Average occupied blocks per context
+system.cpu2.l1c.occ_percent::0               0.674668                       # Average percentage of cache occupancy
+system.cpu2.l1c.occ_percent::1              -0.509877                       # Average percentage of cache occupancy
 system.cpu2.l1c.overall_accesses                68674                       # number of overall (read+write) accesses
 system.cpu2.l1c.overall_avg_miss_latency 38222.283080                       # average overall miss latency
 system.cpu2.l1c.overall_avg_mshr_miss_latency 37218.448733                       # average overall mshr miss latency
@@ -274,10 +274,10 @@ system.cpu3.l1c.demand_mshr_misses              60410                       # nu
 system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu3.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu3.l1c.occ_%::0                     0.678857                       # Average percentage of cache occupancy
-system.cpu3.l1c.occ_%::1                    -0.475386                       # Average percentage of cache occupancy
 system.cpu3.l1c.occ_blocks::0              347.574885                       # Average occupied blocks per context
 system.cpu3.l1c.occ_blocks::1             -243.397586                       # Average occupied blocks per context
+system.cpu3.l1c.occ_percent::0               0.678857                       # Average percentage of cache occupancy
+system.cpu3.l1c.occ_percent::1              -0.475386                       # Average percentage of cache occupancy
 system.cpu3.l1c.overall_accesses                69040                       # number of overall (read+write) accesses
 system.cpu3.l1c.overall_avg_miss_latency 38198.189340                       # average overall miss latency
 system.cpu3.l1c.overall_avg_mshr_miss_latency 37194.354047                       # average overall mshr miss latency
@@ -348,10 +348,10 @@ system.cpu4.l1c.demand_mshr_misses              60188                       # nu
 system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu4.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu4.l1c.occ_%::0                     0.678968                       # Average percentage of cache occupancy
-system.cpu4.l1c.occ_%::1                    -0.494043                       # Average percentage of cache occupancy
 system.cpu4.l1c.occ_blocks::0              347.631602                       # Average occupied blocks per context
 system.cpu4.l1c.occ_blocks::1             -252.949959                       # Average occupied blocks per context
+system.cpu4.l1c.occ_percent::0               0.678968                       # Average percentage of cache occupancy
+system.cpu4.l1c.occ_percent::1              -0.494043                       # Average percentage of cache occupancy
 system.cpu4.l1c.overall_accesses                68997                       # number of overall (read+write) accesses
 system.cpu4.l1c.overall_avg_miss_latency 38173.099970                       # average overall miss latency
 system.cpu4.l1c.overall_avg_mshr_miss_latency 37169.248222                       # average overall mshr miss latency
@@ -422,10 +422,10 @@ system.cpu5.l1c.demand_mshr_misses              60362                       # nu
 system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu5.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu5.l1c.occ_%::0                     0.677357                       # Average percentage of cache occupancy
-system.cpu5.l1c.occ_%::1                    -0.494726                       # Average percentage of cache occupancy
 system.cpu5.l1c.occ_blocks::0              346.806811                       # Average occupied blocks per context
 system.cpu5.l1c.occ_blocks::1             -253.299577                       # Average occupied blocks per context
+system.cpu5.l1c.occ_percent::0               0.677357                       # Average percentage of cache occupancy
+system.cpu5.l1c.occ_percent::1              -0.494726                       # Average percentage of cache occupancy
 system.cpu5.l1c.overall_accesses                69080                       # number of overall (read+write) accesses
 system.cpu5.l1c.overall_avg_miss_latency 37941.708625                       # average overall miss latency
 system.cpu5.l1c.overall_avg_mshr_miss_latency 36937.823349                       # average overall mshr miss latency
@@ -496,10 +496,10 @@ system.cpu6.l1c.demand_mshr_misses              60251                       # nu
 system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu6.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu6.l1c.occ_%::0                     0.678299                       # Average percentage of cache occupancy
-system.cpu6.l1c.occ_%::1                    -0.502932                       # Average percentage of cache occupancy
 system.cpu6.l1c.occ_blocks::0              347.289326                       # Average occupied blocks per context
 system.cpu6.l1c.occ_blocks::1             -257.501227                       # Average occupied blocks per context
+system.cpu6.l1c.occ_percent::0               0.678299                       # Average percentage of cache occupancy
+system.cpu6.l1c.occ_percent::1              -0.502932                       # Average percentage of cache occupancy
 system.cpu6.l1c.overall_accesses                68913                       # number of overall (read+write) accesses
 system.cpu6.l1c.overall_avg_miss_latency 38432.141740                       # average overall miss latency
 system.cpu6.l1c.overall_avg_mshr_miss_latency 37428.256992                       # average overall mshr miss latency
@@ -570,10 +570,10 @@ system.cpu7.l1c.demand_mshr_misses              60276                       # nu
 system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu7.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu7.l1c.occ_%::0                     0.675965                       # Average percentage of cache occupancy
-system.cpu7.l1c.occ_%::1                    -0.511413                       # Average percentage of cache occupancy
 system.cpu7.l1c.occ_blocks::0              346.094259                       # Average occupied blocks per context
 system.cpu7.l1c.occ_blocks::1             -261.843648                       # Average occupied blocks per context
+system.cpu7.l1c.occ_percent::0               0.675965                       # Average percentage of cache occupancy
+system.cpu7.l1c.occ_percent::1              -0.511413                       # Average percentage of cache occupancy
 system.cpu7.l1c.overall_accesses                68980                       # number of overall (read+write) accesses
 system.cpu7.l1c.overall_avg_miss_latency 38046.102147                       # average overall miss latency
 system.cpu7.l1c.overall_avg_mshr_miss_latency 37042.233808                       # average overall mshr miss latency
@@ -853,15 +853,6 @@ system.l2c.demand_mshr_misses                   84625                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.023513                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.023339                       # Average percentage of cache occupancy
-system.l2c.occ_%::2                          0.023014                       # Average percentage of cache occupancy
-system.l2c.occ_%::3                          0.023888                       # Average percentage of cache occupancy
-system.l2c.occ_%::4                          0.023463                       # Average percentage of cache occupancy
-system.l2c.occ_%::5                          0.022624                       # Average percentage of cache occupancy
-system.l2c.occ_%::6                          0.022944                       # Average percentage of cache occupancy
-system.l2c.occ_%::7                          0.022464                       # Average percentage of cache occupancy
-system.l2c.occ_%::8                          0.457051                       # Average percentage of cache occupancy
 system.l2c.occ_blocks::0                    24.077198                       # Average occupied blocks per context
 system.l2c.occ_blocks::1                    23.899612                       # Average occupied blocks per context
 system.l2c.occ_blocks::2                    23.566419                       # Average occupied blocks per context
@@ -871,6 +862,15 @@ system.l2c.occ_blocks::5                    23.167376                       # Av
 system.l2c.occ_blocks::6                    23.494200                       # Average occupied blocks per context
 system.l2c.occ_blocks::7                    23.002994                       # Average occupied blocks per context
 system.l2c.occ_blocks::8                   468.019905                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.023513                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.023339                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.023014                       # Average percentage of cache occupancy
+system.l2c.occ_percent::3                    0.023888                       # Average percentage of cache occupancy
+system.l2c.occ_percent::4                    0.023463                       # Average percentage of cache occupancy
+system.l2c.occ_percent::5                    0.022624                       # Average percentage of cache occupancy
+system.l2c.occ_percent::6                    0.022944                       # Average percentage of cache occupancy
+system.l2c.occ_percent::7                    0.022464                       # Average percentage of cache occupancy
+system.l2c.occ_percent::8                    0.457051                       # Average percentage of cache occupancy
 system.l2c.overall_accesses::0                  23997                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                  24183                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                  24119                       # number of overall (read+write) accesses
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
index f899b1907..132fc2ab1 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
@@ -145,6 +145,7 @@ deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=true
 version=0
 physMemPort=system.physmem.port[0]
@@ -230,6 +231,7 @@ warmup_length=100000
 
 [system.tester]
 type=RubyTester
+check_flush=false
 checks_to_complete=100
 deadlock_threshold=50000
 wakeup_frequency=10
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
index 48846b6c8..69466063c 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/08/2011 17:31:55
+Real time: Apr/19/2011 12:12:40
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.79
-Virtual_time_in_minutes: 0.0131667
-Virtual_time_in_hours:   0.000219444
-Virtual_time_in_days:    9.14352e-06
+Virtual_time_in_seconds: 0.36
+Virtual_time_in_minutes: 0.006
+Virtual_time_in_hours:   0.0001
+Virtual_time_in_days:    4.16667e-06
 
 Ruby_current_time: 352261
 Ruby_start_time: 0
 Ruby_cycles: 352261
 
-mbytes_resident: 33.6719
-mbytes_total: 208.004
-resident_ratio: 0.161956
+mbytes_resident: 35.7031
+mbytes_total: 206.043
+resident_ratio: 0.173299
 
 ruby_cycles_executed: [ 352262 ]
 
@@ -71,9 +71,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 16 count: 986 average: 15.8337
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 256 max: 33636 count: 971 average: 5617.58 | standard deviation: 7479.54 | 86 25 67 61 60 60 59 49 37 31 22 33 21 30 13 6 17 12 14 11 11 7 4 2 6 3 6 6 4 2 3 2 4 4 1 1 2 1 0 1 0 1 2 1 0 1 1 0 2 5 0 3 0 1 0 3 2 5 3 5 2 2 4 3 6 4 3 3 2 4 2 4 3 4 5 7 1 2 5 5 5 4 0 3 2 8 5 5 2 7 2 2 4 1 2 1 0 2 3 2 2 1 0 0 3 2 2 2 0 1 0 0 0 0 1 0 1 0 0 0 0 2 0 1 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 16 max: 2135 count: 46 average: 937.935 | standard deviation: 408.53 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 1 1 1 0 0 2 0 1 0 0 1 0 0 0 3 3 1 0 0 0 0 2 1 1 1 0 0 2 0 0 3 0 1 2 0 0 0 0 0 0 1 2 1 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD: [binsize: 256 max: 26910 count: 54 average: 5436.72 | standard deviation: 7279.79 | 4 1 3 3 5 5 2 1 3 1 2 5 1 2 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST: [binsize: 256 max: 33636 count: 871 average: 5875.94 | standard deviation: 7609.86 | 82 18 51 47 46 53 53 48 33 30 20 28 20 28 12 5 16 12 14 11 11 6 4 2 6 3 5 6 4 2 3 2 4 4 1 1 2 1 0 1 0 1 1 1 0 1 1 0 2 5 0 3 0 1 0 3 2 5 2 5 1 1 4 3 6 3 3 3 2 3 2 4 3 3 5 7 1 2 5 5 5 4 0 3 2 8 5 5 1 7 1 2 4 1 1 1 0 2 3 2 2 1 0 0 3 1 2 2 0 1 0 0 0 0 1 0 1 0 0 0 0 2 0 1 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 16 max: 2135 count: 46 average: 937.935 | standard deviation: 408.53 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 1 1 1 0 0 2 0 1 0 0 1 0 0 0 3 3 1 0 0 0 0 2 1 1 1 0 0 2 0 0 3 0 1 2 0 0 0 0 0 0 1 2 1 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_NULL: [binsize: 256 max: 33636 count: 971 average: 5617.58 | standard deviation: 7479.54 | 86 25 67 61 60 60 59 49 37 31 22 33 21 30 13 6 17 12 14 11 11 7 4 2 6 3 6 6 4 2 3 2 4 4 1 1 2 1 0 1 0 1 2 1 0 1 1 0 2 5 0 3 0 1 0 3 2 5 3 5 2 2 4 3 6 4 3 3 2 4 2 4 3 4 5 7 1 2 5 5 5 4 0 3 2 8 5 5 2 7 2 2 4 1 2 1 0 2 3 2 2 1 0 0 3 2 2 2 0 1 0 0 0 0 1 0 1 0 0 0 0 2 0 1 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -85,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 imcomplete_dir_Times: 0
-miss_latency_IFETCH_NULL: [binsize: 16 max: 2135 count: 46 average: 937.935 | standard deviation: 408.53 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 1 1 1 0 0 2 0 1 0 0 1 0 0 0 3 3 1 0 0 0 0 2 1 1 1 0 0 2 0 0 3 0 1 2 0 0 0 0 0 0 1 2 1 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD_NULL: [binsize: 256 max: 26910 count: 54 average: 5436.72 | standard deviation: 7279.79 | 4 1 3 3 5 5 2 1 3 1 2 5 1 2 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_NULL: [binsize: 256 max: 33636 count: 871 average: 5875.94 | standard deviation: 7609.86 | 82 18 51 47 46 53 53 48 33 30 20 28 20 28 12 5 16 12 14 11 11 6 4 2 6 3 5 6 4 2 3 2 4 4 1 1 2 1 0 1 0 1 1 1 0 1 1 0 2 5 0 3 0 1 0 3 2 5 2 5 1 1 4 3 6 3 3 3 2 3 2 4 3 3 5 7 1 2 5 5 5 4 0 3 2 8 5 5 1 7 1 2 4 1 1 1 0 2 3 2 2 1 0 0 3 1 2 2 0 1 0 0 0 0 1 0 1 0 0 0 0 2 0 1 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_NULL: [binsize: 16 max: 2135 count: 46 average: 937.935 | standard deviation: 408.53 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 1 1 1 0 0 2 0 1 0 0 1 0 0 0 3 3 1 0 0 0 0 2 1 1 1 0 0 2 0 0 3 0 1 2 0 0 0 0 0 0 1 2 1 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9831
+page_reclaims: 9430
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 48
 
 Network Stats
 -------------
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
index b6aef8b2e..ae6fd6f72 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 17:31:51
-M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip
-M5 started Feb  8 2011 17:31:55
-M5 executing on SC2B0617
+M5 compiled Apr 19 2011 12:12:36
+M5 started Apr 19 2011 12:12:40
+M5 executing on maize
 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
index bf0d1f08a..a413d4c87 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 213000                       # Number of bytes of host memory used
-host_seconds                                     0.47                       # Real time elapsed on the host
-host_tick_rate                                 753338                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210992                       # Number of bytes of host memory used
+host_seconds                                     0.25                       # Real time elapsed on the host
+host_tick_rate                                1396782                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000352                       # Number of seconds simulated
 sim_ticks                                      352261                       # Number of ticks simulated
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
index 326e421d1..b92c57f9b 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
@@ -141,6 +141,7 @@ deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=true
 version=0
 physMemPort=system.physmem.port[0]
@@ -226,6 +227,7 @@ warmup_length=100000
 
 [system.tester]
 type=RubyTester
+check_flush=false
 checks_to_complete=100
 deadlock_threshold=50000
 wakeup_frequency=10
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
index 034586735..b7a61f99e 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/08/2011 17:41:43
+Real time: Apr/19/2011 12:14:52
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.8
-Virtual_time_in_minutes: 0.0133333
-Virtual_time_in_hours:   0.000222222
-Virtual_time_in_days:    9.25926e-06
+Virtual_time_in_seconds: 0.38
+Virtual_time_in_minutes: 0.00633333
+Virtual_time_in_hours:   0.000105556
+Virtual_time_in_days:    4.39815e-06
 
 Ruby_current_time: 372291
 Ruby_start_time: 0
 Ruby_cycles: 372291
 
-mbytes_resident: 33.7734
-mbytes_total: 208.148
-resident_ratio: 0.162313
+mbytes_resident: 35.7773
+mbytes_total: 206.145
+resident_ratio: 0.173574
 
 ruby_cycles_executed: [ 372292 ]
 
@@ -71,9 +71,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1034 average: 15.8404
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 256 max: 31997 count: 1019 average: 5668.53 | standard deviation: 8073.92 | 94 34 102 118 76 61 60 39 35 29 18 16 23 15 9 14 7 5 5 5 5 5 2 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 2 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 8 2 7 1 3 9 10 7 6 6 7 4 5 7 6 8 5 3 2 5 7 3 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 2 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 8 max: 1286 count: 55 average: 671.836 | standard deviation: 242.921 | 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 2 2 0 0 1 0 0 1 0 0 1 0 2 3 1 4 1 0 0 1 0 0 0 0 1 0 1 2 2 1 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_LD: [binsize: 256 max: 28569 count: 45 average: 4874.44 | standard deviation: 7882.18 | 6 2 5 9 2 2 3 2 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST: [binsize: 256 max: 31997 count: 919 average: 6006.46 | standard deviation: 8225.99 | 86 24 69 94 73 58 57 37 35 29 17 15 23 15 9 13 7 5 5 4 4 5 1 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 1 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 7 2 7 1 2 8 10 6 6 6 7 4 5 7 5 8 5 3 2 5 7 2 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 1 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 8 max: 1286 count: 55 average: 671.836 | standard deviation: 242.921 | 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 2 2 0 0 1 0 0 1 0 0 1 0 2 3 1 4 1 0 0 1 0 0 0 0 1 0 1 2 2 1 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_NULL: [binsize: 256 max: 31997 count: 1019 average: 5668.53 | standard deviation: 8073.92 | 94 34 102 118 76 61 60 39 35 29 18 16 23 15 9 14 7 5 5 5 5 5 2 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 2 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 8 2 7 1 3 9 10 7 6 6 7 4 5 7 6 8 5 3 2 5 7 3 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 2 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -85,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 imcomplete_dir_Times: 0
-miss_latency_IFETCH_NULL: [binsize: 8 max: 1286 count: 55 average: 671.836 | standard deviation: 242.921 | 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 2 2 0 0 1 0 0 1 0 0 1 0 2 3 1 4 1 0 0 1 0 0 0 0 1 0 1 2 2 1 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_LD_NULL: [binsize: 256 max: 28569 count: 45 average: 4874.44 | standard deviation: 7882.18 | 6 2 5 9 2 2 3 2 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_NULL: [binsize: 256 max: 31997 count: 919 average: 6006.46 | standard deviation: 8225.99 | 86 24 69 94 73 58 57 37 35 29 17 15 23 15 9 13 7 5 5 4 4 5 1 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 1 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 7 2 7 1 2 8 10 6 6 6 7 4 5 7 5 8 5 3 2 5 7 2 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 1 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_NULL: [binsize: 8 max: 1286 count: 55 average: 671.836 | standard deviation: 242.921 | 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 2 2 0 0 1 0 0 1 0 0 1 0 2 3 1 4 1 0 0 1 0 0 0 0 1 0 1 2 2 1 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -119,11 +119,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9846
+page_reclaims: 9448
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 48
 
 Network Stats
 -------------
@@ -411,6 +411,7 @@ Writeback_Ack [873 ] 873
 Writeback_Nack [0 ] 0
 Unblock [0 ] 0
 Exclusive_Unblock [926 ] 926
+DmaAck [0 ] 0
 L2_Replacement [874 ] 874
 
  - Transitions -
@@ -1160,6 +1161,76 @@ ILSI  All_Acks [0 ] 0
 ILSI  Writeback_Ack [0 ] 0
 ILSI  L2_Replacement [0 ] 0
 
+ILOSD  L1_GETS [0 ] 0
+ILOSD  L1_GETX [0 ] 0
+ILOSD  L1_PUTO [0 ] 0
+ILOSD  L1_PUTX [0 ] 0
+ILOSD  L1_PUTS_only [0 ] 0
+ILOSD  L1_PUTS [0 ] 0
+ILOSD  Fwd_GETX [0 ] 0
+ILOSD  Fwd_GETS [0 ] 0
+ILOSD  Fwd_DMA [0 ] 0
+ILOSD  Own_GETX [0 ] 0
+ILOSD  Inv [0 ] 0
+ILOSD  DmaAck [0 ] 0
+ILOSD  L2_Replacement [0 ] 0
+
+ILOSXD  L1_GETS [0 ] 0
+ILOSXD  L1_GETX [0 ] 0
+ILOSXD  L1_PUTO [0 ] 0
+ILOSXD  L1_PUTX [0 ] 0
+ILOSXD  L1_PUTS_only [0 ] 0
+ILOSXD  L1_PUTS [0 ] 0
+ILOSXD  Fwd_GETX [0 ] 0
+ILOSXD  Fwd_GETS [0 ] 0
+ILOSXD  Fwd_DMA [0 ] 0
+ILOSXD  Own_GETX [0 ] 0
+ILOSXD  Inv [0 ] 0
+ILOSXD  DmaAck [0 ] 0
+ILOSXD  L2_Replacement [0 ] 0
+
+ILOD  L1_GETS [0 ] 0
+ILOD  L1_GETX [0 ] 0
+ILOD  L1_PUTO [0 ] 0
+ILOD  L1_PUTX [0 ] 0
+ILOD  L1_PUTS_only [0 ] 0
+ILOD  L1_PUTS [0 ] 0
+ILOD  Fwd_GETX [0 ] 0
+ILOD  Fwd_GETS [0 ] 0
+ILOD  Fwd_DMA [0 ] 0
+ILOD  Own_GETX [0 ] 0
+ILOD  Inv [0 ] 0
+ILOD  DmaAck [0 ] 0
+ILOD  L2_Replacement [0 ] 0
+
+ILXD  L1_GETS [0 ] 0
+ILXD  L1_GETX [0 ] 0
+ILXD  L1_PUTO [0 ] 0
+ILXD  L1_PUTX [0 ] 0
+ILXD  L1_PUTS_only [0 ] 0
+ILXD  L1_PUTS [0 ] 0
+ILXD  Fwd_GETX [0 ] 0
+ILXD  Fwd_GETS [0 ] 0
+ILXD  Fwd_DMA [0 ] 0
+ILXD  Own_GETX [0 ] 0
+ILXD  Inv [0 ] 0
+ILXD  DmaAck [0 ] 0
+ILXD  L2_Replacement [0 ] 0
+
+ILOXD  L1_GETS [0 ] 0
+ILOXD  L1_GETX [0 ] 0
+ILOXD  L1_PUTO [0 ] 0
+ILOXD  L1_PUTX [0 ] 0
+ILOXD  L1_PUTS_only [0 ] 0
+ILOXD  L1_PUTS [0 ] 0
+ILOXD  Fwd_GETX [0 ] 0
+ILOXD  Fwd_GETS [0 ] 0
+ILOXD  Fwd_DMA [0 ] 0
+ILOXD  Own_GETX [0 ] 0
+ILOXD  Inv [0 ] 0
+ILOXD  DmaAck [0 ] 0
+ILOXD  L2_Replacement [0 ] 0
+
 Memory controller: system.dir_cntrl0.memBuffer:
   memory_total_requests: 1676
   memory_reads: 882
@@ -1196,6 +1267,7 @@ Memory_Data [882 ] 882
 Memory_Ack [793 ] 793
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
+DMA_ACK [0 ] 0
 Data [0 ] 0
 
  - Transitions -
@@ -1376,4 +1448,22 @@ OI_D  PUTO [0 ] 0
 OI_D  PUTO_SHARERS [0 ] 0
 OI_D  DMA_READ [0 ] 0
 OI_D  DMA_WRITE [0 ] 0
-OI_D  Data
\ No newline at end of file
+OI_D  Data [0 ] 0
+
+OD  GETX [0 ] 0
+OD  GETS [0 ] 0
+OD  PUTX [0 ] 0
+OD  PUTO [0 ] 0
+OD  PUTO_SHARERS [0 ] 0
+OD  DMA_READ [0 ] 0
+OD  DMA_WRITE [0 ] 0
+OD  DMA_ACK [0 ] 0
+
+MD  GETX [0 ] 0
+MD  GETS [0 ] 0
+MD  PUTX [0 ] 0
+MD  PUTO [0 ] 0
+MD  PUTO_SHARERS [0 ] 0
+MD  DMA_READ [0 ] 0
+MD  DMA_WRITE [0 ] 0
+MD  DMA_ACK
\ No newline at end of file
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
index 835c245b9..02f8ee2da 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 17:41:34
-M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
-M5 started Feb  8 2011 17:41:42
-M5 executing on SC2B0617
+M5 compiled Apr 19 2011 12:14:48
+M5 started Apr 19 2011 12:14:52
+M5 executing on maize
 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
index e7af0eda4..575c0cf2d 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 213148                       # Number of bytes of host memory used
-host_seconds                                     0.50                       # Real time elapsed on the host
-host_tick_rate                                 746373                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211096                       # Number of bytes of host memory used
+host_seconds                                     0.28                       # Real time elapsed on the host
+host_tick_rate                                1336063                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000372                       # Number of seconds simulated
 sim_ticks                                      372291                       # Number of ticks simulated
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
index d76954012..49751acb6 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
@@ -238,6 +238,7 @@ warmup_length=100000
 
 [system.tester]
 type=RubyTester
+check_flush=false
 checks_to_complete=100
 deadlock_threshold=50000
 wakeup_frequency=10
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
index eaf785d6e..11981e7c4 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Mar/26/2011 22:00:44
+Real time: Apr/19/2011 12:17:16
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.23
-Virtual_time_in_minutes: 0.00383333
-Virtual_time_in_hours:   6.38889e-05
-Virtual_time_in_days:    2.66204e-06
+Virtual_time_in_seconds: 0.19
+Virtual_time_in_minutes: 0.00316667
+Virtual_time_in_hours:   5.27778e-05
+Virtual_time_in_days:    2.19907e-06
 
 Ruby_current_time: 268001
 Ruby_start_time: 0
 Ruby_cycles: 268001
 
-mbytes_resident: 34.8828
-mbytes_total: 197.086
-resident_ratio: 0.177013
+mbytes_resident: 35.6602
+mbytes_total: 205.984
+resident_ratio: 0.17314
 
 ruby_cycles_executed: [ 268002 ]
 
@@ -127,7 +127,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9226
+page_reclaims: 9422
 page_faults: 0
 swaps: 0
 block_inputs: 0
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
index 59a570da3..aa7783380 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Mar 26 2011 14:06:20
-M5 started Mar 26 2011 22:00:43
-M5 executing on phenom
+M5 compiled Apr 19 2011 12:17:10
+M5 started Apr 19 2011 12:17:16
+M5 executing on maize
 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
index 4b63b6519..e0dc8816d 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 201820                       # Number of bytes of host memory used
-host_seconds                                     0.29                       # Real time elapsed on the host
-host_tick_rate                                 910825                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210932                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
+host_tick_rate                                3091502                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000268                       # Number of seconds simulated
 sim_ticks                                      268001                       # Number of ticks simulated
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
index dda1ea910..5fea2b164 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
@@ -128,6 +128,7 @@ deadlock_threshold=500000
 icache=system.ruby.cpu_ruby_ports.icache
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=true
 version=0
 physMemPort=system.physmem.port[0]
@@ -213,6 +214,7 @@ warmup_length=100000
 
 [system.tester]
 type=RubyTester
+check_flush=false
 checks_to_complete=100
 deadlock_threshold=50000
 wakeup_frequency=10
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
index d1706cac4..a78bc431b 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/08/2011 17:57:03
+Real time: Apr/19/2011 12:09:50
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.4
-Virtual_time_in_minutes: 0.00666667
-Virtual_time_in_hours:   0.000111111
-Virtual_time_in_days:    4.62963e-06
+Virtual_time_in_seconds: 0.17
+Virtual_time_in_minutes: 0.00283333
+Virtual_time_in_hours:   4.72222e-05
+Virtual_time_in_days:    1.96759e-06
 
 Ruby_current_time: 210961
 Ruby_start_time: 0
 Ruby_cycles: 210961
 
-mbytes_resident: 33.4023
-mbytes_total: 207.566
-resident_ratio: 0.160961
+mbytes_resident: 35.4336
+mbytes_total: 205.836
+resident_ratio: 0.172164
 
 ruby_cycles_executed: [ 210962 ]
 
@@ -70,9 +70,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 16 count: 978 average: 15.8016
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 64 max: 8993 count: 963 average: 3469.42 | standard deviation: 1599.67 | 72 11 5 3 10 7 13 12 7 12 1 8 4 1 1 2 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 2 3 2 0 5 2 2 5 6 10 12 7 16 18 17 32 34 24 31 26 29 36 35 35 28 41 44 32 34 21 30 17 25 22 20 20 10 10 6 8 9 7 5 2 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 8 max: 1126 count: 52 average: 473.327 | standard deviation: 221.338 | 0 2 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD: [binsize: 32 max: 5235 count: 48 average: 3979.79 | standard deviation: 1306.56 | 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 1 0 1 0 0 1 0 1 0 1 0 2 3 2 2 1 4 0 1 0 1 1 2 0 0 1 0 2 1 1 0 0 0 0 0 0 1 0 1 0 3 0 2 0 0 0 3 0 1 ]
 miss_latency_ST: [binsize: 64 max: 8993 count: 863 average: 3621.56 | standard deviation: 1476.69 | 66 9 4 1 5 2 6 6 3 6 0 0 2 1 1 2 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 2 3 2 0 5 2 2 5 5 10 11 7 16 18 17 32 31 23 31 25 28 35 30 31 23 40 43 29 34 20 27 16 25 22 19 19 7 8 6 5 8 7 5 2 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 8 max: 1126 count: 52 average: 473.327 | standard deviation: 221.338 | 0 2 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_L1Cache: [binsize: 1 max: 117 count: 71 average: 13.3803 | standard deviation: 32.5601 | 0 10 15 23 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 0 1 1 ]
 miss_latency_L2Cache: [binsize: 64 max: 8993 count: 33 average: 2589.88 | standard deviation: 2554.56 | 8 4 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 4 2 2 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
 miss_latency_Directory: [binsize: 32 max: 6151 count: 859 average: 3788.87 | standard deviation: 1226.92 | 0 0 0 0 0 5 1 1 8 2 2 5 13 0 0 12 6 0 4 8 1 0 7 1 1 3 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 1 2 0 0 0 5 0 1 1 2 0 2 3 3 3 6 3 4 7 4 3 6 10 11 6 4 12 14 14 15 17 13 9 17 13 7 19 18 10 17 19 20 15 17 17 8 20 25 16 22 22 14 18 15 19 10 10 19 11 9 8 14 11 15 7 12 8 9 11 5 5 4 6 3 3 3 5 4 5 2 5 2 3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ]
@@ -86,13 +86,13 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 imcomplete_dir_Times: 859
-miss_latency_IFETCH_L2Cache: [binsize: 1 max: 117 count: 4 average: 62.25 | standard deviation: 62.0725 | 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ]
-miss_latency_IFETCH_Directory: [binsize: 8 max: 1126 count: 48 average: 507.583 | standard deviation: 193.22 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 4 average:     2 | standard deviation: 0.816497 | 0 1 2 1 ]
 miss_latency_LD_Directory: [binsize: 32 max: 5235 count: 44 average: 4341.41 | standard deviation: 510.099 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 1 0 1 0 0 1 0 1 0 1 0 2 3 2 2 1 4 0 1 0 1 1 2 0 0 1 0 2 1 1 0 0 0 0 0 0 1 0 1 0 3 0 2 0 0 0 3 0 1 ]
 miss_latency_ST_L1Cache: [binsize: 1 max: 117 count: 67 average: 14.0597 | standard deviation: 33.4075 | 0 9 13 22 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 0 1 1 ]
 miss_latency_ST_L2Cache: [binsize: 64 max: 8993 count: 29 average: 2938.52 | standard deviation: 2533.58 | 6 2 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 4 2 2 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
 miss_latency_ST_Directory: [binsize: 32 max: 6151 count: 767 average: 3962.52 | standard deviation: 973.04 | 0 0 0 0 0 4 0 0 4 1 0 2 6 0 0 6 2 0 1 5 0 0 0 0 0 2 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 1 2 0 0 0 5 0 1 1 2 0 2 3 3 2 6 3 4 6 4 3 6 10 11 6 4 12 14 14 13 16 13 8 17 13 6 19 17 10 16 19 18 12 15 15 7 16 25 15 22 21 13 16 15 19 9 10 17 10 8 8 14 11 15 7 12 7 9 10 5 2 4 4 3 3 3 2 4 4 2 5 2 3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ]
+miss_latency_IFETCH_L2Cache: [binsize: 1 max: 117 count: 4 average: 62.25 | standard deviation: 62.0725 | 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ]
+miss_latency_IFETCH_Directory: [binsize: 8 max: 1126 count: 48 average: 507.583 | standard deviation: 193.22 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -124,11 +124,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9722
+page_reclaims: 9364
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 56
 
 Network Stats
 -------------
@@ -188,7 +188,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.icache
 
   system.ruby.cpu_ruby_ports.icache_request_type_IFETCH:   100%
 
-  system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode:   52    100%
+  system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor:   52    100%
 
 Cache Stats: system.ruby.cpu_ruby_ports.dcache
   system.ruby.cpu_ruby_ports.dcache_total_misses: 852
@@ -200,7 +200,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache
   system.ruby.cpu_ruby_ports.dcache_request_type_LD:   5.28169%
   system.ruby.cpu_ruby_ports.dcache_request_type_ST:   94.7183%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   852    100%
+  system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor:   852    100%
 
 Cache Stats: system.l1_cntrl0.L2cacheMemory
   system.l1_cntrl0.L2cacheMemory_total_misses: 904
@@ -213,7 +213,7 @@ Cache Stats: system.l1_cntrl0.L2cacheMemory
   system.l1_cntrl0.L2cacheMemory_request_type_ST:   89.2699%
   system.l1_cntrl0.L2cacheMemory_request_type_IFETCH:   5.75221%
 
-  system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   904    100%
+  system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   904    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -240,6 +240,8 @@ Writeback_Ack [852 ] 852
 Writeback_Nack [0 ] 0
 All_acks [0 ] 0
 All_acks_no_sharers [859 ] 859
+Flush_line [0 ] 0
+Block_Ack [0 ] 0
 
  - Transitions -
 I  Load [44 ] 44
@@ -254,6 +256,7 @@ I  Other_GETS [0 ] 0
 I  Other_GETS_No_Mig [0 ] 0
 I  NC_DMA_GETS [0 ] 0
 I  Invalidate [0 ] 0
+I  Flush_line [0 ] 0
 
 S  Load [0 ] 0
 S  Ifetch [0 ] 0
@@ -267,6 +270,7 @@ S  Other_GETS [0 ] 0
 S  Other_GETS_No_Mig [0 ] 0
 S  NC_DMA_GETS [0 ] 0
 S  Invalidate [0 ] 0
+S  Flush_line [0 ] 0
 
 O  Load [0 ] 0
 O  Ifetch [0 ] 0
@@ -281,6 +285,7 @@ O  Merged_GETS [0 ] 0
 O  Other_GETS_No_Mig [0 ] 0
 O  NC_DMA_GETS [0 ] 0
 O  Invalidate [0 ] 0
+O  Flush_line [0 ] 0
 
 M  Load [0 ] 0
 M  Ifetch [0 ] 0
@@ -295,6 +300,7 @@ M  Merged_GETS [0 ] 0
 M  Other_GETS_No_Mig [0 ] 0
 M  NC_DMA_GETS [0 ] 0
 M  Invalidate [0 ] 0
+M  Flush_line [0 ] 0
 
 MM  Load [4 ] 4
 MM  Ifetch [4 ] 4
@@ -309,6 +315,7 @@ MM  Merged_GETS [0 ] 0
 MM  Other_GETS_No_Mig [0 ] 0
 MM  NC_DMA_GETS [0 ] 0
 MM  Invalidate [0 ] 0
+MM  Flush_line [0 ] 0
 
 IM  Load [0 ] 0
 IM  Ifetch [0 ] 0
@@ -323,6 +330,7 @@ IM  Invalidate [0 ] 0
 IM  Ack [0 ] 0
 IM  Data [0 ] 0
 IM  Exclusive_Data [767 ] 767
+IM  Flush_line [0 ] 0
 
 SM  Load [0 ] 0
 SM  Ifetch [0 ] 0
@@ -337,6 +345,7 @@ SM  Invalidate [0 ] 0
 SM  Ack [0 ] 0
 SM  Data [0 ] 0
 SM  Exclusive_Data [0 ] 0
+SM  Flush_line [0 ] 0
 
 OM  Load [0 ] 0
 OM  Ifetch [0 ] 0
@@ -352,6 +361,7 @@ OM  Invalidate [0 ] 0
 OM  Ack [0 ] 0
 OM  All_acks [0 ] 0
 OM  All_acks_no_sharers [0 ] 0
+OM  Flush_line [0 ] 0
 
 ISM  Load [0 ] 0
 ISM  Ifetch [0 ] 0
@@ -360,6 +370,7 @@ ISM  L2_Replacement [0 ] 0
 ISM  L1_to_L2 [0 ] 0
 ISM  Ack [0 ] 0
 ISM  All_acks_no_sharers [0 ] 0
+ISM  Flush_line [0 ] 0
 
 M_W  Load [0 ] 0
 M_W  Ifetch [0 ] 0
@@ -368,6 +379,7 @@ M_W  L2_Replacement [0 ] 0
 M_W  L1_to_L2 [310 ] 310
 M_W  Ack [0 ] 0
 M_W  All_acks_no_sharers [91 ] 91
+M_W  Flush_line [0 ] 0
 
 MM_W  Load [0 ] 0
 MM_W  Ifetch [0 ] 0
@@ -376,6 +388,7 @@ MM_W  L2_Replacement [0 ] 0
 MM_W  L1_to_L2 [4284 ] 4284
 MM_W  Ack [0 ] 0
 MM_W  All_acks_no_sharers [768 ] 768
+MM_W  Flush_line [0 ] 0
 
 IS  Load [0 ] 0
 IS  Ifetch [0 ] 0
@@ -392,6 +405,7 @@ IS  Shared_Ack [0 ] 0
 IS  Data [0 ] 0
 IS  Shared_Data [0 ] 0
 IS  Exclusive_Data [92 ] 92
+IS  Flush_line [0 ] 0
 
 SS  Load [0 ] 0
 SS  Ifetch [0 ] 0
@@ -402,6 +416,7 @@ SS  Ack [0 ] 0
 SS  Shared_Ack [0 ] 0
 SS  All_acks [0 ] 0
 SS  All_acks_no_sharers [0 ] 0
+SS  Flush_line [0 ] 0
 
 OI  Load [0 ] 0
 OI  Ifetch [0 ] 0
@@ -415,6 +430,7 @@ OI  Other_GETS_No_Mig [0 ] 0
 OI  NC_DMA_GETS [0 ] 0
 OI  Invalidate [0 ] 0
 OI  Writeback_Ack [0 ] 0
+OI  Flush_line [0 ] 0
 
 MI  Load [0 ] 0
 MI  Ifetch [1 ] 1
@@ -428,6 +444,7 @@ MI  Other_GETS_No_Mig [0 ] 0
 MI  NC_DMA_GETS [0 ] 0
 MI  Invalidate [0 ] 0
 MI  Writeback_Ack [852 ] 852
+MI  Flush_line [0 ] 0
 
 II  Load [0 ] 0
 II  Ifetch [0 ] 0
@@ -441,6 +458,7 @@ II  NC_DMA_GETS [0 ] 0
 II  Invalidate [0 ] 0
 II  Writeback_Ack [0 ] 0
 II  Writeback_Nack [0 ] 0
+II  Flush_line [0 ] 0
 
 IT  Load [0 ] 0
 IT  Ifetch [0 ] 0
@@ -454,6 +472,7 @@ IT  Merged_GETS [0 ] 0
 IT  Other_GETS_No_Mig [0 ] 0
 IT  NC_DMA_GETS [0 ] 0
 IT  Invalidate [0 ] 0
+IT  Flush_line [0 ] 0
 
 ST  Load [0 ] 0
 ST  Ifetch [0 ] 0
@@ -467,6 +486,7 @@ ST  Merged_GETS [0 ] 0
 ST  Other_GETS_No_Mig [0 ] 0
 ST  NC_DMA_GETS [0 ] 0
 ST  Invalidate [0 ] 0
+ST  Flush_line [0 ] 0
 
 OT  Load [0 ] 0
 OT  Ifetch [0 ] 0
@@ -480,6 +500,7 @@ OT  Merged_GETS [0 ] 0
 OT  Other_GETS_No_Mig [0 ] 0
 OT  NC_DMA_GETS [0 ] 0
 OT  Invalidate [0 ] 0
+OT  Flush_line [0 ] 0
 
 MT  Load [0 ] 0
 MT  Ifetch [0 ] 0
@@ -493,6 +514,7 @@ MT  Merged_GETS [0 ] 0
 MT  Other_GETS_No_Mig [0 ] 0
 MT  NC_DMA_GETS [0 ] 0
 MT  Invalidate [0 ] 0
+MT  Flush_line [0 ] 0
 
 MMT  Load [0 ] 0
 MMT  Ifetch [0 ] 0
@@ -506,6 +528,94 @@ MMT  Merged_GETS [0 ] 0
 MMT  Other_GETS_No_Mig [0 ] 0
 MMT  NC_DMA_GETS [0 ] 0
 MMT  Invalidate [0 ] 0
+MMT  Flush_line [0 ] 0
+
+MI_F  Load [0 ] 0
+MI_F  Ifetch [0 ] 0
+MI_F  Store [0 ] 0
+MI_F  L1_to_L2 [0 ] 0
+MI_F  Writeback_Ack [0 ] 0
+MI_F  Flush_line [0 ] 0
+
+MM_F  Load [0 ] 0
+MM_F  Ifetch [0 ] 0
+MM_F  Store [0 ] 0
+MM_F  L1_to_L2 [0 ] 0
+MM_F  Other_GETX [0 ] 0
+MM_F  Other_GETS [0 ] 0
+MM_F  Merged_GETS [0 ] 0
+MM_F  Other_GETS_No_Mig [0 ] 0
+MM_F  NC_DMA_GETS [0 ] 0
+MM_F  Invalidate [0 ] 0
+MM_F  Ack [0 ] 0
+MM_F  All_acks [0 ] 0
+MM_F  All_acks_no_sharers [0 ] 0
+MM_F  Flush_line [0 ] 0
+MM_F  Block_Ack [0 ] 0
+
+IM_F  Load [0 ] 0
+IM_F  Ifetch [0 ] 0
+IM_F  Store [0 ] 0
+IM_F  L2_Replacement [0 ] 0
+IM_F  L1_to_L2 [0 ] 0
+IM_F  Other_GETX [0 ] 0
+IM_F  Other_GETS [0 ] 0
+IM_F  Other_GETS_No_Mig [0 ] 0
+IM_F  NC_DMA_GETS [0 ] 0
+IM_F  Invalidate [0 ] 0
+IM_F  Ack [0 ] 0
+IM_F  Data [0 ] 0
+IM_F  Exclusive_Data [0 ] 0
+IM_F  Flush_line [0 ] 0
+
+ISM_F  Load [0 ] 0
+ISM_F  Ifetch [0 ] 0
+ISM_F  Store [0 ] 0
+ISM_F  L2_Replacement [0 ] 0
+ISM_F  L1_to_L2 [0 ] 0
+ISM_F  Ack [0 ] 0
+ISM_F  All_acks_no_sharers [0 ] 0
+ISM_F  Flush_line [0 ] 0
+
+SM_F  Load [0 ] 0
+SM_F  Ifetch [0 ] 0
+SM_F  Store [0 ] 0
+SM_F  L2_Replacement [0 ] 0
+SM_F  L1_to_L2 [0 ] 0
+SM_F  Other_GETX [0 ] 0
+SM_F  Other_GETS [0 ] 0
+SM_F  Other_GETS_No_Mig [0 ] 0
+SM_F  NC_DMA_GETS [0 ] 0
+SM_F  Invalidate [0 ] 0
+SM_F  Ack [0 ] 0
+SM_F  Data [0 ] 0
+SM_F  Exclusive_Data [0 ] 0
+SM_F  Flush_line [0 ] 0
+
+OM_F  Load [0 ] 0
+OM_F  Ifetch [0 ] 0
+OM_F  Store [0 ] 0
+OM_F  L2_Replacement [0 ] 0
+OM_F  L1_to_L2 [0 ] 0
+OM_F  Other_GETX [0 ] 0
+OM_F  Other_GETS [0 ] 0
+OM_F  Merged_GETS [0 ] 0
+OM_F  Other_GETS_No_Mig [0 ] 0
+OM_F  NC_DMA_GETS [0 ] 0
+OM_F  Invalidate [0 ] 0
+OM_F  Ack [0 ] 0
+OM_F  All_acks [0 ] 0
+OM_F  All_acks_no_sharers [0 ] 0
+OM_F  Flush_line [0 ] 0
+
+MM_WF  Load [0 ] 0
+MM_WF  Ifetch [0 ] 0
+MM_WF  Store [0 ] 0
+MM_WF  L2_Replacement [0 ] 0
+MM_WF  L1_to_L2 [0 ] 0
+MM_WF  Ack [0 ] 0
+MM_WF  All_acks_no_sharers [0 ] 0
+MM_WF  Flush_line [0 ] 0
 
 Cache Stats: system.dir_cntrl0.probeFilter
   system.dir_cntrl0.probeFilter_total_misses: 0
@@ -561,6 +671,8 @@ All_acks_and_shared_data [0 ] 0
 All_acks_and_owner_data [0 ] 0
 All_acks_and_data_no_sharers [0 ] 0
 All_Unblocks [0 ] 0
+GETF [0 ] 0
+PUTF [0 ] 0
 
  - Transitions -
 NX  GETX [0 ] 0
@@ -569,6 +681,7 @@ NX  PUT [0 ] 0
 NX  Pf_Replacement [0 ] 0
 NX  DMA_READ [0 ] 0
 NX  DMA_WRITE [0 ] 0
+NX  GETF [0 ] 0
 
 NO  GETX [0 ] 0
 NO  GETS [0 ] 0
@@ -576,6 +689,7 @@ NO  PUT [852 ] 852
 NO  Pf_Replacement [0 ] 0
 NO  DMA_READ [0 ] 0
 NO  DMA_WRITE [0 ] 0
+NO  GETF [0 ] 0
 
 S  GETX [0 ] 0
 S  GETS [0 ] 0
@@ -583,6 +697,7 @@ S  PUT [0 ] 0
 S  Pf_Replacement [0 ] 0
 S  DMA_READ [0 ] 0
 S  DMA_WRITE [0 ] 0
+S  GETF [0 ] 0
 
 O  GETX [0 ] 0
 O  GETS [0 ] 0
@@ -590,12 +705,14 @@ O  PUT [0 ] 0
 O  Pf_Replacement [0 ] 0
 O  DMA_READ [0 ] 0
 O  DMA_WRITE [0 ] 0
+O  GETF [0 ] 0
 
 E  GETX [767 ] 767
 E  GETS [92 ] 92
 E  PUT [0 ] 0
 E  DMA_READ [0 ] 0
 E  DMA_WRITE [0 ] 0
+E  GETF [0 ] 0
 
 O_R  GETX [0 ] 0
 O_R  GETS [0 ] 0
@@ -605,6 +722,7 @@ O_R  DMA_READ [0 ] 0
 O_R  DMA_WRITE [0 ] 0
 O_R  Ack [0 ] 0
 O_R  All_acks_and_data_no_sharers [0 ] 0
+O_R  GETF [0 ] 0
 
 S_R  GETX [0 ] 0
 S_R  GETS [0 ] 0
@@ -615,6 +733,7 @@ S_R  DMA_WRITE [0 ] 0
 S_R  Ack [0 ] 0
 S_R  Data [0 ] 0
 S_R  All_acks_and_data_no_sharers [0 ] 0
+S_R  GETF [0 ] 0
 
 NO_R  GETX [0 ] 0
 NO_R  GETS [0 ] 0
@@ -626,6 +745,7 @@ NO_R  Ack [0 ] 0
 NO_R  Data [0 ] 0
 NO_R  Exclusive_Data [0 ] 0
 NO_R  All_acks_and_data_no_sharers [0 ] 0
+NO_R  GETF [0 ] 0
 
 NO_B  GETX [0 ] 0
 NO_B  GETS [0 ] 0
@@ -635,6 +755,7 @@ NO_B  UnblockM [856 ] 856
 NO_B  Pf_Replacement [0 ] 0
 NO_B  DMA_READ [0 ] 0
 NO_B  DMA_WRITE [0 ] 0
+NO_B  GETF [0 ] 0
 
 NO_B_X  GETX [0 ] 0
 NO_B_X  GETS [0 ] 0
@@ -644,6 +765,7 @@ NO_B_X  UnblockM [0 ] 0
 NO_B_X  Pf_Replacement [0 ] 0
 NO_B_X  DMA_READ [0 ] 0
 NO_B_X  DMA_WRITE [0 ] 0
+NO_B_X  GETF [0 ] 0
 
 NO_B_S  GETX [0 ] 0
 NO_B_S  GETS [0 ] 0
@@ -653,6 +775,7 @@ NO_B_S  UnblockM [0 ] 0
 NO_B_S  Pf_Replacement [0 ] 0
 NO_B_S  DMA_READ [0 ] 0
 NO_B_S  DMA_WRITE [0 ] 0
+NO_B_S  GETF [0 ] 0
 
 NO_B_S_W  GETX [0 ] 0
 NO_B_S_W  GETS [0 ] 0
@@ -662,6 +785,7 @@ NO_B_S_W  Pf_Replacement [0 ] 0
 NO_B_S_W  DMA_READ [0 ] 0
 NO_B_S_W  DMA_WRITE [0 ] 0
 NO_B_S_W  All_Unblocks [0 ] 0
+NO_B_S_W  GETF [0 ] 0
 
 O_B  GETX [0 ] 0
 O_B  GETS [0 ] 0
@@ -671,6 +795,7 @@ O_B  UnblockM [0 ] 0
 O_B  Pf_Replacement [0 ] 0
 O_B  DMA_READ [0 ] 0
 O_B  DMA_WRITE [0 ] 0
+O_B  GETF [0 ] 0
 
 NO_B_W  GETX [0 ] 0
 NO_B_W  GETS [0 ] 0
@@ -681,6 +806,7 @@ NO_B_W  Pf_Replacement [0 ] 0
 NO_B_W  DMA_READ [0 ] 0
 NO_B_W  DMA_WRITE [0 ] 0
 NO_B_W  Memory_Data [859 ] 859
+NO_B_W  GETF [0 ] 0
 
 O_B_W  GETX [0 ] 0
 O_B_W  GETS [0 ] 0
@@ -690,6 +816,7 @@ O_B_W  Pf_Replacement [0 ] 0
 O_B_W  DMA_READ [0 ] 0
 O_B_W  DMA_WRITE [0 ] 0
 O_B_W  Memory_Data [0 ] 0
+O_B_W  GETF [0 ] 0
 
 NO_W  GETX [0 ] 0
 NO_W  GETS [0 ] 0
@@ -698,6 +825,7 @@ NO_W  Pf_Replacement [0 ] 0
 NO_W  DMA_READ [0 ] 0
 NO_W  DMA_WRITE [0 ] 0
 NO_W  Memory_Data [0 ] 0
+NO_W  GETF [0 ] 0
 
 O_W  GETX [0 ] 0
 O_W  GETS [0 ] 0
@@ -706,6 +834,7 @@ O_W  Pf_Replacement [0 ] 0
 O_W  DMA_READ [0 ] 0
 O_W  DMA_WRITE [0 ] 0
 O_W  Memory_Data [0 ] 0
+O_W  GETF [0 ] 0
 
 NO_DW_B_W  GETX [0 ] 0
 NO_DW_B_W  GETS [0 ] 0
@@ -717,6 +846,7 @@ NO_DW_B_W  Ack [0 ] 0
 NO_DW_B_W  Data [0 ] 0
 NO_DW_B_W  Exclusive_Data [0 ] 0
 NO_DW_B_W  All_acks_and_data_no_sharers [0 ] 0
+NO_DW_B_W  GETF [0 ] 0
 
 NO_DR_B_W  GETX [0 ] 0
 NO_DR_B_W  GETS [0 ] 0
@@ -730,6 +860,7 @@ NO_DR_B_W  Shared_Ack [0 ] 0
 NO_DR_B_W  Shared_Data [0 ] 0
 NO_DR_B_W  Data [0 ] 0
 NO_DR_B_W  Exclusive_Data [0 ] 0
+NO_DR_B_W  GETF [0 ] 0
 
 NO_DR_B_D  GETX [0 ] 0
 NO_DR_B_D  GETS [0 ] 0
@@ -745,6 +876,7 @@ NO_DR_B_D  Exclusive_Data [0 ] 0
 NO_DR_B_D  All_acks_and_shared_data [0 ] 0
 NO_DR_B_D  All_acks_and_owner_data [0 ] 0
 NO_DR_B_D  All_acks_and_data_no_sharers [0 ] 0
+NO_DR_B_D  GETF [0 ] 0
 
 NO_DR_B  GETX [0 ] 0
 NO_DR_B  GETS [0 ] 0
@@ -760,6 +892,7 @@ NO_DR_B  Exclusive_Data [0 ] 0
 NO_DR_B  All_acks_and_shared_data [0 ] 0
 NO_DR_B  All_acks_and_owner_data [0 ] 0
 NO_DR_B  All_acks_and_data_no_sharers [0 ] 0
+NO_DR_B  GETF [0 ] 0
 
 NO_DW_W  GETX [0 ] 0
 NO_DW_W  GETS [0 ] 0
@@ -768,6 +901,7 @@ NO_DW_W  Pf_Replacement [0 ] 0
 NO_DW_W  DMA_READ [0 ] 0
 NO_DW_W  DMA_WRITE [0 ] 0
 NO_DW_W  Memory_Ack [0 ] 0
+NO_DW_W  GETF [0 ] 0
 
 O_DR_B_W  GETX [0 ] 0
 O_DR_B_W  GETS [0 ] 0
@@ -778,6 +912,7 @@ O_DR_B_W  DMA_WRITE [0 ] 0
 O_DR_B_W  Memory_Data [0 ] 0
 O_DR_B_W  Ack [0 ] 0
 O_DR_B_W  Shared_Ack [0 ] 0
+O_DR_B_W  GETF [0 ] 0
 
 O_DR_B  GETX [0 ] 0
 O_DR_B  GETS [0 ] 0
@@ -789,6 +924,7 @@ O_DR_B  Ack [0 ] 0
 O_DR_B  Shared_Ack [0 ] 0
 O_DR_B  All_acks_and_owner_data [0 ] 0
 O_DR_B  All_acks_and_data_no_sharers [0 ] 0
+O_DR_B  GETF [0 ] 0
 
 WB  GETX [0 ] 0
 WB  GETS [0 ] 0
@@ -801,6 +937,7 @@ WB  Writeback_Exclusive_Dirty [767 ] 767
 WB  Pf_Replacement [0 ] 0
 WB  DMA_READ [0 ] 0
 WB  DMA_WRITE [0 ] 0
+WB  GETF [0 ] 0
 
 WB_O_W  GETX [0 ] 0
 WB_O_W  GETS [0 ] 0
@@ -809,6 +946,7 @@ WB_O_W  Pf_Replacement [0 ] 0
 WB_O_W  DMA_READ [0 ] 0
 WB_O_W  DMA_WRITE [0 ] 0
 WB_O_W  Memory_Ack [0 ] 0
+WB_O_W  GETF [0 ] 0
 
 WB_E_W  GETX [0 ] 0
 WB_E_W  GETS [1 ] 1
@@ -816,4 +954,22 @@ WB_E_W  PUT [0 ] 0
 WB_E_W  Pf_Replacement [0 ] 0
 WB_E_W  DMA_READ [0 ] 0
 WB_E_W  DMA_WRITE [0 ] 0
-WB_E_W  Memory_Ack
\ No newline at end of file
+WB_E_W  Memory_Ack [767 ] 767
+WB_E_W  GETF [0 ] 0
+
+NO_F  GETX [0 ] 0
+NO_F  GETS [0 ] 0
+NO_F  PUT [0 ] 0
+NO_F  UnblockM [0 ] 0
+NO_F  Pf_Replacement [0 ] 0
+NO_F  GETF [0 ] 0
+NO_F  PUTF [0 ] 0
+
+NO_F_W  GETX [0 ] 0
+NO_F_W  GETS [0 ] 0
+NO_F_W  PUT [0 ] 0
+NO_F_W  Pf_Replacement [0 ] 0
+NO_F_W  DMA_READ [0 ] 0
+NO_F_W  DMA_WRITE [0 ] 0
+NO_F_W  Memory_Data [0 ] 0
+NO_F_W  GETF
\ No newline at end of file
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
index 1073821b9..05640872e 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 17:56:59
-M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
-M5 started Feb  8 2011 17:57:03
-M5 executing on SC2B0617
+M5 compiled Apr 19 2011 12:09:47
+M5 started Apr 19 2011 12:09:50
+M5 executing on maize
 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
index a2b6d6c54..a66b45470 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 212552                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
-host_tick_rate                                1803209                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210780                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                                3205678                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000211                       # Number of seconds simulated
 sim_ticks                                      210961                       # Number of ticks simulated
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
index 247e64cce..25ba63d62 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
@@ -104,6 +104,7 @@ deadlock_threshold=500000
 icache=system.ruby.cpu_ruby_ports.dcache
 max_outstanding_requests=16
 physmem=system.physmem
+using_network_tester=false
 using_ruby_tester=true
 version=0
 physMemPort=system.physmem.port[0]
@@ -181,6 +182,7 @@ warmup_length=100000
 
 [system.tester]
 type=RubyTester
+check_flush=false
 checks_to_complete=100
 deadlock_threshold=50000
 wakeup_frequency=10
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
index ce11e4002..6fae82526 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/07/2011 01:47:37
+Real time: Apr/19/2011 11:58:24
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.3
-Virtual_time_in_minutes: 0.005
-Virtual_time_in_hours:   8.33333e-05
-Virtual_time_in_days:    3.47222e-06
+Virtual_time_in_seconds: 0.16
+Virtual_time_in_minutes: 0.00266667
+Virtual_time_in_hours:   4.44444e-05
+Virtual_time_in_days:    1.85185e-06
 
 Ruby_current_time: 281031
 Ruby_start_time: 0
 Ruby_cycles: 281031
 
-mbytes_resident: 34.3867
-mbytes_total: 225.355
-resident_ratio: 0.152606
+mbytes_resident: 35.2539
+mbytes_total: 205.707
+resident_ratio: 0.171398
 
 ruby_cycles_executed: [ 281032 ]
 
@@ -70,9 +70,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1014 average: 15.7801
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 32 max: 6068 count: 999 average: 4453.7 | standard deviation: 529.325 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 5 6 4 7 8 11 10 20 9 19 17 13 22 23 30 23 21 22 25 31 27 31 39 35 22 20 39 25 30 27 25 23 23 19 22 10 24 20 22 19 19 12 21 14 12 11 5 8 6 0 3 2 0 2 0 2 0 1 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 32 max: 5702 count: 52 average: 4674.27 | standard deviation: 454.241 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 2 0 0 1 3 4 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 2 2 0 3 2 0 3 0 3 1 3 3 1 1 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
 miss_latency_LD: [binsize: 32 max: 5245 count: 48 average: 4523.02 | standard deviation: 319.516 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 2 1 1 2 3 1 2 1 1 0 4 1 0 2 1 2 4 2 0 1 1 0 1 1 2 4 1 1 0 0 0 0 0 1 0 1 ]
 miss_latency_ST: [binsize: 32 max: 6068 count: 899 average: 4437.24 | standard deviation: 539.424 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 4 6 4 7 7 11 9 18 9 16 16 12 19 19 25 21 18 21 23 29 26 30 34 33 22 18 37 23 25 25 23 20 22 16 19 9 19 16 18 17 16 9 20 13 9 8 4 7 6 0 3 2 0 1 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 32 max: 5702 count: 52 average: 4674.27 | standard deviation: 454.241 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 2 0 0 1 3 4 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 2 2 0 3 2 0 3 0 3 1 3 3 1 1 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
 miss_latency_L1Cache: [binsize: 32 max: 4572 count: 43 average: 3768.3 | standard deviation: 359.401 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 2 2 0 3 1 0 2 2 1 1 3 1 2 1 1 0 4 1 3 0 2 0 0 1 0 0 0 0 0 0 0 2 0 0 0 2 ]
 miss_latency_Directory: [binsize: 32 max: 6068 count: 956 average: 4484.53 | standard deviation: 514.797 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 1 0 2 4 1 5 4 3 3 5 7 10 10 16 8 16 17 11 22 23 29 23 21 22 25 31 27 31 37 35 22 20 37 25 30 27 25 23 23 19 22 10 24 20 22 19 19 12 21 14 12 11 5 8 6 0 3 2 0 2 0 2 0 1 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -85,12 +85,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 imcomplete_dir_Times: 956
-miss_latency_IFETCH_L1Cache: [binsize: 32 max: 4022 count: 1 average:  4022 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_IFETCH_Directory: [binsize: 32 max: 5702 count: 51 average: 4687.06 | standard deviation: 449.206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 0 0 1 3 4 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 2 2 0 3 2 0 3 0 3 1 3 3 1 1 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
 miss_latency_LD_L1Cache: [binsize: 32 max: 3964 count: 1 average:  3964 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_LD_Directory: [binsize: 32 max: 5245 count: 47 average: 4534.91 | standard deviation: 312.044 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 1 1 2 3 1 2 1 1 0 4 1 0 2 1 2 4 2 0 1 1 0 1 1 2 4 1 1 0 0 0 0 0 1 0 1 ]
 miss_latency_ST_L1Cache: [binsize: 32 max: 4572 count: 41 average: 3757.34 | standard deviation: 364.607 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 2 2 0 3 1 0 2 2 1 1 3 1 2 1 1 0 3 1 2 0 2 0 0 1 0 0 0 0 0 0 0 2 0 0 0 2 ]
 miss_latency_ST_Directory: [binsize: 32 max: 6068 count: 858 average: 4469.73 | standard deviation: 524.902 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 1 0 2 4 1 5 3 3 3 5 6 10 9 15 8 14 16 10 19 19 24 21 18 21 23 29 26 30 32 33 22 18 35 23 25 25 23 20 22 16 19 9 19 16 18 17 16 9 20 13 9 8 4 7 6 0 3 2 0 1 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
+miss_latency_IFETCH_L1Cache: [binsize: 32 max: 4022 count: 1 average:  4022 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_IFETCH_Directory: [binsize: 32 max: 5702 count: 51 average: 4687.06 | standard deviation: 449.206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 0 0 1 3 4 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 2 2 0 3 2 0 3 0 3 1 3 3 1 1 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -122,7 +122,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9878
+page_reclaims: 9324
 page_faults: 0
 swaps: 0
 block_inputs: 0
@@ -181,7 +181,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache
   system.ruby.cpu_ruby_ports.dcache_request_type_ST:   89.7597%
   system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   5.32915%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   957    100%
+  system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor:   957    100%
 
  --- L1Cache ---
  - Event Counts -
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
index e67c01bd9..4ccb7bef5 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:47:37
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:24
+M5 executing on maize
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index e1f5ad3f1..5b0c0bebb 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 230768                       # Number of bytes of host memory used
-host_seconds                                     0.30                       # Real time elapsed on the host
-host_tick_rate                                 934733                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210648                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
+host_tick_rate                                5633491                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000281                       # Number of seconds simulated
 sim_ticks                                      281031                       # Number of ticks simulated
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index 540e1709f..ea57eb23e 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -10,7 +10,7 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=drivesys.physmem
-readfile=/home/gblack/m5/repos/m5.x86fs/configs/boot/netperf-server.rcS
+readfile=/n/blue/z/binkert/work/m5/work/configs/boot/netperf-server.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -731,7 +731,7 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=testsys.physmem
-readfile=/home/gblack/m5/repos/m5.x86fs/configs/boot/netperf-stream-client.rcS
+readfile=/n/blue/z/binkert/work/m5/work/configs/boot/netperf-stream-client.rcS
 symbolfile=
 system_rev=1024
 system_type=34
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
index 62b569073..cd96bb2d7 100755
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:46:17
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:46:32
-M5 executing on burrito
+M5 compiled Apr 19 2011 12:17:36
+M5 started Apr 19 2011 12:17:43
+M5 executing on maize
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index a776ca423..a57983503 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
@@ -172,10 +172,10 @@ drivesys.tsunami.ethernet.txPPS                    25                       # Pa
 drivesys.tsunami.ethernet.txPackets                 5                       # Number of Packets Transmitted
 drivesys.tsunami.ethernet.txTcpChecksums            2                       # Number of tx TCP Checksums done by device
 drivesys.tsunami.ethernet.txUdpChecksums            0                       # Number of tx UDP Checksums done by device
-host_inst_rate                               71982907                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 498216                       # Number of bytes of host memory used
-host_seconds                                     3.80                       # Real time elapsed on the host
-host_tick_rate                            52659325700                       # Simulator tick rate (ticks/s)
+host_inst_rate                              269342091                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 478340                       # Number of bytes of host memory used
+host_seconds                                     1.02                       # Real time elapsed on the host
+host_tick_rate                           197020377111                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   273374833                       # Number of instructions simulated
 sim_seconds                                  0.200001                       # Number of seconds simulated
@@ -479,10 +479,10 @@ drivesys.tsunami.ethernet.totalSwi                  0                       # to
 drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
 drivesys.tsunami.ethernet.totalTxIdle               0                       # total number of TxIdle written to ISR
 drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
-host_inst_rate                            86035621838                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 498216                       # Number of bytes of host memory used
+host_inst_rate                           178043202572                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 478340                       # Number of bytes of host memory used
 host_seconds                                     0.00                       # Real time elapsed on the host
-host_tick_rate                              235143018                       # Simulator tick rate (ticks/s)
+host_tick_rate                              482553899                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   273374833                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
-- 
2.30.2