From 8c1c451a9088a8a62cac447bcbadd049ee428079 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 1 May 2018 14:34:19 -0400 Subject: [PATCH] ac/surface/gfx6: don't overallocate mipmapped HTILE MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Tested-by: Dieter Nützel Reviewed-by: Nicolai Hähnle --- src/amd/common/ac_surface.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index b50157cdb9a..6600ff6b7ef 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -934,8 +934,17 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, /* Make sure HTILE covers the whole miptree, because the shader reads * TC-compatible HTILE even for levels where it's disabled by DB. */ - if (surf->htile_size && config->info.levels > 1) - surf->htile_size *= 2; + if (surf->htile_size && config->info.levels > 1 && + surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) { + /* MSAA can't occur with levels > 1, so ignore the sample count. */ + const unsigned total_pixels = surf->surf_size / surf->bpe; + const unsigned htile_block_size = 8 * 8; + const unsigned htile_element_size = 4; + + surf->htile_size = (total_pixels / htile_block_size) * + htile_element_size; + surf->htile_size = align(surf->htile_size, surf->htile_alignment); + } surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED; surf->is_displayable = surf->is_linear || -- 2.30.2