From 8c1e619359c76295dd98b3ed1faecf41e7cb5c4e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 20 May 2020 15:23:42 +0100 Subject: [PATCH] whitespace, rename ilang to alu_main_stage.il --- src/soc/fu/alu/formal/proof_main_stage.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/fu/alu/formal/proof_main_stage.py b/src/soc/fu/alu/formal/proof_main_stage.py index c139cccb..3bc06e6f 100644 --- a/src/soc/fu/alu/formal/proof_main_stage.py +++ b/src/soc/fu/alu/formal/proof_main_stage.py @@ -70,7 +70,7 @@ class Driver(Elaboratable): # main assertion of arithmetic operations with m.Switch(rec.insn_type): with m.Case(InternalOp.OP_ADD): - + comb += Assert(Cat(o, carry_out) == (a + b + carry_in)) # CA32 @@ -104,7 +104,7 @@ class ALUTestCase(FHDLTestCase): def test_ilang(self): dut = Driver() vl = rtlil.convert(dut, ports=[]) - with open("main_stage.il", "w") as f: + with open("alu_main_stage.il", "w") as f: f.write(vl) -- 2.30.2