From 8c2ef0c0b88be360b5e0a782ec0056cc12ac8908 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 13 Jun 2018 15:09:52 +0100 Subject: [PATCH] cross-reference issues under consideration --- simple_v_extension.mdwn | 2 +- simple_v_extension/simple_v_chennai_2018.tex | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index 803bdba02..4cf0937ed 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -1059,7 +1059,7 @@ Similar rules apply to the destination register. * Throw an exception. Whether that actually results in spawning threads as part of the trap-handling remains to be seen. -# Under consideration +# Under consideration From the Chennai 2018 slides the following issues were raised. Efforts to analyse and answer these questions are below. diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index 417c0f3d9..82d9b1d36 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -715,6 +715,7 @@ loop: \item 8/16-bit ops is it worthwhile adding a "start offset"? \\ (a bit like misaligned addressing... for registers)\\ or just use predication to skip start? + \item http://libre-riscv.org/simple\_v\_extension/\#issues \end{itemize} } -- 2.30.2