From 8c3cabfc353df86b59052c41b3582534fc867a2f Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 25 May 2022 15:45:15 +0100 Subject: [PATCH] --- openpower/sv/cr_int_predication.mdwn | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index 9da87f9a5..c30776ef3 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -70,6 +70,8 @@ Useful side-effects: or destination GPR, in ways that are not possible with other SVP64 instructions because normal SVP64 is bit-per-element. On these weird instructions the element in effect *is* a bit. +* `mfcrweird` mitigates a need to add `conflictd`, part of + [[sv/vector_ops]], as well as allowing more complex comparisons. # Bit ordering. -- 2.30.2