From 8c49977463b9ebbf1a233be1efe3d5629009cc6e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 10 Oct 2018 06:14:22 +0100 Subject: [PATCH] add microarchitecture comment --- 3d_gpu/microarchitecture.mdwn | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn index 7b095bd95..ca99e1441 100644 --- a/3d_gpu/microarchitecture.mdwn +++ b/3d_gpu/microarchitecture.mdwn @@ -16,3 +16,14 @@ using the extended registers (similar to how Intel processors use a lower clock rate when AVX512 is in use) so that scalar code is not slowed down too much. +> > Using a 4xFMA with a banked register file where the bank is selected by +> the +> > lower order register number means we could probably get away with 1Rx1W +> > SRAM as the backing memory for the register file, similarly to Hwacha. +> +> okaaay.... sooo... we make an assumption that the top higher "banks" +> are pretty much always going to be "vectorised", such that, actually, +> they genuinely don't need to be 6R-4W (or whatever). +> +Yeah pretty much, though I had meant the bank number comes from the +least-significant bits of the 7-bit register number. -- 2.30.2