From 8c4a38ff15fb8f58238fbd7caf0ffa8f66fc3fd6 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 30 Dec 2020 19:34:50 +0000 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 1c3702016..9db2e1969 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -285,6 +285,8 @@ this may be considered to be elements 0b00 to 0b01 inclusive. # MASK/MASK_SRC & MASK_KIND Encoding +TODO: rename MASK_KIND to MASKMODE + One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two types may not be mixed. @@ -295,10 +297,10 @@ mask, which is equivalent to "not having any predication at all" and consequently, in combination with all other default zeros, fully disables SV. -| Value | Description | -|-------|------------------------------------------------------| -| 0 | MASK/MASK_SRC are encoded using Integer Predication | -| 1 | MASK/MASK_SRC are encoded using CR-based Predication | +| MASK\_KIND Value | Description | +|-----------|------------------------------------------------------| +| 0 | MASK/MASK_SRC are encoded using Integer Predication | +| 1 | MASK/MASK_SRC are encoded using CR-based Predication | Integer Twin predication has a second set of 3 bits that uses the same encoding thus allowing either the same register (r3 or r10) to be used -- 2.30.2