From 8c4c4285cf6210dc75c58600a275822451caee11 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 21 May 2020 11:14:52 +0100 Subject: [PATCH] use branch-specific data structures, add "regspecs" to branch pspec --- src/soc/fu/branch/pipe_data.py | 14 +++++++++++++- src/soc/fu/branch/test/test_pipe_caller.py | 6 +++--- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py index 05d3a931..e75f9e96 100644 --- a/src/soc/fu/branch/pipe_data.py +++ b/src/soc/fu/branch/pipe_data.py @@ -27,7 +27,8 @@ from nmigen import Signal, Const from ieee754.fpcommon.getop import FPPipeContext from soc.decoder.power_decoder2 import Data from soc.fu.alu.pipe_data import IntegerData - +from nmutil.dynamicpipe import SimpleHandshakeRedir +from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace class BranchInputData(IntegerData): regspec = [('SPR', 'spr1', '0:63'), @@ -86,3 +87,14 @@ class BranchOutputData(IntegerData): lst = super().eq(i) return lst + [self.spr1.eq(i.spr1), self.spr2.eq(i.spr2), self.nia.eq(i.nia)] + + +# TODO: replace CompALUOpSubset with CompBranchOpSubset +class BranchPipeSpec: + regspec = (BranchInputData.regspec, BranchOutputData.regspec) + def __init__(self, id_wid, op_wid): + self.id_wid = id_wid + self.op_wid = op_wid + self.opkls = lambda _: CompALUOpSubset(name="op") + self.stage = None + self.pipekls = SimpleHandshakeRedir diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index 8666a416..53758b1d 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -14,7 +14,7 @@ from soc.decoder.isa.all import ISA from soc.fu.branch.pipeline import BranchBasePipe from soc.fu.branch.br_input_record import CompBROpSubset -from soc.fu.alu.pipe_data import ALUPipeSpec +from soc.fu.branch.pipe_data import BranchPipeSpec import random @@ -101,7 +101,7 @@ class BranchTestCase(FHDLTestCase): def test_ilang(self): rec = CompBROpSubset() - pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) + pspec = BranchPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) alu = BranchBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("branch_pipeline.il", "w") as f: @@ -124,7 +124,7 @@ class TestRunner(FHDLTestCase): rec = CompBROpSubset() - pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) + pspec = BranchPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) m.submodules.branch = branch = BranchBasePipe(pspec) comb += branch.p.data_i.ctx.op.eq_from_execute1(pdecode2.e) -- 2.30.2