From 8c849de8bc8f637f7fa1b8ef4f55dd6bd32c7733 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 23 Jun 2021 17:21:05 +0100 Subject: [PATCH] add ASCII art example to int predicated SVP64 --- src/openpower/decoder/isa/test_caller_svp64_predication.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/openpower/decoder/isa/test_caller_svp64_predication.py b/src/openpower/decoder/isa/test_caller_svp64_predication.py index 839b8a99..d96ed2cd 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_predication.py +++ b/src/openpower/decoder/isa/test_caller_svp64_predication.py @@ -120,6 +120,13 @@ class DecoderTestCase(FHDLTestCase): # adds, integer predicated mask r3=0b10 # 1 = 5 + 9 => not to be touched (skipped) # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 + # reg num 0 1 2 3 4 5 6 7 8 9 10 11 + # src r3=0b10 N Y N Y + # | | | | + # +-------+ | add + | + # | +-------+ add --+ + # | | + # dest r3=0b10 N Y isa = SVP64Asm(['sv.add/m=r3 1.v, 5.v, 9.v' ]) lst = list(isa) -- 2.30.2