From 8c93e40094e465e85f9239dffdf62fb91d679647 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 27 Sep 2019 05:27:48 +0100 Subject: [PATCH] update nlnet standards proposal --- nlnet_2019_standards.mdwn | 67 +++++++++++++++++++++++++++++---------- nlnet_proposals.mdwn | 1 + 2 files changed, 51 insertions(+), 17 deletions(-) diff --git a/nlnet_2019_standards.mdwn b/nlnet_2019_standards.mdwn index 676049d73..af0b52b6a 100644 --- a/nlnet_2019_standards.mdwn +++ b/nlnet_2019_standards.mdwn @@ -19,11 +19,18 @@ if you need any HTML to make your point please include this as attachment. ## Abstract: Can you explain the whole project and its expected outcome(s). -The Libre RISC-V SoC is a hybrid CPU, VPU and GPU which is being designed to be libre to the bedrock. When the hardware is transparently auditable, it can be trusted to not secretly compromise the software running on it. +The Libre RISC-V SoC is a hybrid CPU, VPU and GPU which is being designed +to be libre to the bedrock. When the hardware is transparently auditable, +it can be trusted to not secretly compromise the software running on it. -With RISC-V being in its early infancy, however, Standards for Video Acceleration and 3D Graphics Acceleration do not yet exist. These need to be written, proposed, formally ratified and Conformance Test Suites written and likewise ratified. +With RISC-V being in its early infancy, however, Standards for Video +Acceleration and 3D Graphics Acceleration do not yet exist. These need +to be written, proposed, formally ratified and Conformance Test Suites +written and likewise ratified. -This takes a huge amount of time and coordinated collaboration, and is a necessary co-dependent task alongside the actual development of the processor itself. +This takes a huge amount of time and coordinated collaboration, and is +a necessary co-dependent task alongside the actual development of the +processor itself. # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions? @@ -39,37 +46,63 @@ EUR 50,000. # Explain what the requested budget will be used for? -The improvements and additions to RISC-V Standards (known as Extensions) need to be written, reviewed thoroughly, justification for the features given, and then proposed. +The improvements and additions to RISC-V Standards (known as Extensions) +need to be written, reviewed thoroughly, justification for the features +given, and then proposed. -There are several (see links at end) already in draft form. The primary one is the Vectorisation Standard. Additional Vector Operations is another. Ttranscendental operations (SIN, COS, LOG) another. +There are several (see links at end) already in draft form. The primary +one is the Vectorisation Standard. Additional Vector Operations is +another. Ttranscendental operations (SIN, COS, LOG) another. -Once drafts have been agreed, a simulator can be developed. Next is some unit tests, and after that, some formal Compliance Tests. +Once drafts have been agreed, a simulator can be developed. Next is some +unit tests, and after that, some formal Compliance Tests. -Finally this can be submitted to the RISC-V Foundation for formal adoption. +Finally this can be submitted to the RISC-V Foundation for formal +adoption. -Traveling expenses for presenting the standards to the RISC-V -community at Libre Conferences as well as RISC-V Workshops. +Traveling expenses for presenting the standards to the RISC-V community +at Libre Conferences as well as RISC-V Workshops are needed. -Writing up of papers on the core technology and discoveries behind the standards, for presentation at IEEE and other Computing Conferences. +Writing up of papers on the core technology and discoveries behind the +standards, for presentation at IEEE and other Computing Conferences. +This to aid in understanding of the need for the Standards and to +make adoption easier. # Does the project have other funding sources, both past and present? -The initial proposal in November 2018 was for implementation of the actual processor, as well as writing a simulator and developing Kazan, the 3D Vulkan Driver. Purism began also sponsoring the overall project in mid 2019. +The initial proposal in November 2018 was for implementation of the +actual processor, as well as writing a simulator and developing Kazan, +the 3D Vulkan Driver. Purism began also sponsoring the overall project +in mid 2019. -It was discovered only in September 2019 on an offchance comment from someone inside the (closed participation) RISC-V Foundation that RISC-V Standards require a full Conformance Compliance Test Suite as part of formal acceptance. This easily doubles the workload of Standards Development and is in no way coverable by the initial 2018 proposal. +It was discovered only in September 2019 on an offchance comment from +someone inside the (closed participation) RISC-V Foundation that RISC-V +Standards require a full Conformance Compliance Test Suite as part +of formal acceptance. This easily doubles the workload of Standards +Development and is in no way coverable by the initial 2018 proposal. # Compare your own project with existing or historical efforts. -RISC-V is in its early infancy and has neither Extensions for 3D nor Video. Most off the shelf commercial SoCs will use a special custom block for Video, and a separate GPU for 3D. Each of these, bring proprietary, is an attack vector for privacy subversion. - -In this project, the CPU *is* the VPU and the GPU, so there is nothing to compare it against. The full transparency of the Standards Development Process is a necessary prerequisite for being able to trust the end result. +RISC-V is in its early infancy and has neither Extensions for 3D nor +Video. Most off the shelf commercial SoCs will use a special custom block +for Video, and a separate GPU for 3D. Each of these, bring proprietary, +is an attack vector for privacy subversion. +In this project, the CPU *is* the VPU and the GPU, so there is nothing to +compare it against. The full transparency of the Standards Development +Process is a necessary prerequisite for being able to trust the end +result. ## What are significant technical challenges you expect to solve during the project, if any? -The key challenge will not be technical, it is a communications issue. The RISC-V Foundation operates as a closed ITU Style Standards Organisation, requiring effectively an NDA for participation, with negligeable transparency and zero accountability. +The key challenge will not be technical, it is a communications issue. The +RISC-V Foundation operates as a closed ITU Style Standards Organisation, +requiring effectively an NDA for participation, with negligeable +transparency and zero accountability. -A two year protracted and persistent request for open participation and recognition of the value of the same is finally starting to get action taken. +A two year protracted and persistent request for open participation +and recognition of the value of the same is finally starting to get +action taken. ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes diff --git a/nlnet_proposals.mdwn b/nlnet_proposals.mdwn index ca665d436..cf584ace3 100644 --- a/nlnet_proposals.mdwn +++ b/nlnet_proposals.mdwn @@ -9,6 +9,7 @@ added RADV, re-submitted 2019sep26 * [[nlnet_2019_gcc]] - submitted 2019sep23 * [[nlnet_2019_wishbone_streaming]] - submitted 2019sep26 +* [[nlnet_2019_standards]] - submitted 2019sep27 # MESA RADV Discussion links -- 2.30.2