From 8c9d630dfb14609b9787c5124129d48410ed1bb8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 23 Oct 2022 10:52:15 +0100 Subject: [PATCH] use svshape2 instead of svindex for the 4th shape (cycling through modulo4 shifts) as there is no change of order, svindex wastes a regfile lookup chacha20 --- src/openpower/decoder/isa/test_caller_svp64_chacha20.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_chacha20.py b/src/openpower/decoder/isa/test_caller_svp64_chacha20.py index 747d4f03..7e11fb4b 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_chacha20.py +++ b/src/openpower/decoder/isa/test_caller_svp64_chacha20.py @@ -115,7 +115,7 @@ class SVSTATETestCase(FHDLTestCase): 'svindex 11, 0, 1, 3, 0, 1, 0', # SVSHAPE0, a 'svindex 15, 1, 1, 3, 0, 1, 0', # SVSHAPE1, b 'svindex 19, 2, 1, 3, 0, 1, 0', # SVSHAPE2, c - 'svindex 21, 3, 4, 3, 0, 1, 0', # SVSHAPE3, shift amount, mod 4 + 'svshape2 0, 0, 3, 4, 0, 1', # SVSHAPE3, shift amount, mod 4 # establish CTR for outer round count 'addi 16, 0, %d' % nrounds, # set number of rounds 'mtspr 9, 16', # set CTR to number of rounds @@ -150,11 +150,10 @@ class SVSTATETestCase(FHDLTestCase): # offsets for d (modulo 4 shift amount) shifts = [16, 12, 8, 7] # chacha20 shifts - idxs2 = [0, 1, 2, 3] # cycle order (for fun) for i in range(4): - set_masked_reg(initial_regs, 42, i, ew_bits=8, value=idxs2[i]) set_masked_reg(initial_regs, 18, i, ew_bits=32, value=shifts[i]) + # set up input test vector then pack it into regs x = [0] * 16 for i in range(16): x[i] = i << 1 -- 2.30.2