From 8cbe83445b2ec78fab1f303918c79268713500b5 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 24 Sep 2019 16:56:21 -0400 Subject: [PATCH] ac: add radeon_info::tcc_harvested Cc: 19.2 Reviewed-by: Bas Nieuwenhuizen --- src/amd/common/ac_gpu_info.c | 4 ++++ src/amd/common/ac_gpu_info.h | 1 + 2 files changed, 5 insertions(+) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 41713b5348e..b5e0b8415d2 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -470,6 +470,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, } if (info->chip_class >= GFX10) { info->tcc_cache_line_size = 128; + /* This is a hack, but it's all we can do without a kernel upgrade. */ + info->tcc_harvested = + (info->vram_size / info->num_tcc_blocks) != 512*1024*1024; } else { info->tcc_cache_line_size = 64; } @@ -694,6 +697,7 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" num_sdma_rings = %i\n", info->num_sdma_rings); printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq); printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size); + printf(" tcc_harvested = %u\n", info->tcc_harvested); printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned); printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index a21bd51e29d..a2adab88ec4 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -58,6 +58,7 @@ struct radeon_info { uint32_t num_sdma_rings; uint32_t clock_crystal_freq; uint32_t tcc_cache_line_size; + bool tcc_harvested; bool has_clear_state; bool has_distributed_tess; bool has_dcc_constant_encode; -- 2.30.2