From 8cc6a5f85d290294febd9b8705c1ac8d79cbf24e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 23 Sep 2022 17:12:56 +0100 Subject: [PATCH] add expected results for sv.maddld in openpower/test/mul_cases.py --- src/openpower/test/mul/mul_cases.py | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/openpower/test/mul/mul_cases.py b/src/openpower/test/mul/mul_cases.py index bd456a5a..903579a6 100644 --- a/src/openpower/test/mul/mul_cases.py +++ b/src/openpower/test/mul/mul_cases.py @@ -4,6 +4,7 @@ from openpower.test.common import TestAccumulatorBase, skip_case from openpower.test.state import ExpectedState from openpower.sv.trans.svp64 import SVP64Asm from openpower.decoder.isa.caller import SVP64State +from copy import deepcopy import random @@ -162,6 +163,7 @@ class SVP64MAdd(TestAccumulatorBase): # needs to be implemented) # "maddhd","maddhdu","maddld" def case_sv_maddld(self): + # muladdlo RT = RA * RB + RC lst = list(SVP64Asm(["sv.maddld *4, *8, *12, 16"])) initial_regs = [0] * 32 initial_regs[8:16] = range(1, 17) @@ -169,5 +171,13 @@ class SVP64MAdd(TestAccumulatorBase): svstate = SVP64State() svstate.vl = 4 svstate.maxvl = 4 + expected_regs = deepcopy(initial_regs) + r16 = initial_regs[16] + for i in range(4): + # mul-and-add-lo is: RT = RA*RB+RC. RC (16) is scalar, RA/RB vector + res = initial_regs[8+i] * initial_regs[12+i] + r16 + expected_regs[4+i] = res & 0xffff_ffff_ffff_ffff + e = ExpectedState(expected_regs, 8) self.add_case(Program(lst, bigendian), initial_regs, - initial_svstate=svstate) + initial_svstate=svstate, + expected=e) -- 2.30.2