From 8ce8a230f458d09f1847ba87a3073cf4c07579d3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 16 Jan 2015 17:51:17 +0100 Subject: [PATCH] Bugfix in dff2dffe --- passes/techmap/dff2dffe.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc index 339007156..17549bd06 100644 --- a/passes/techmap/dff2dffe.cc +++ b/passes/techmap/dff2dffe.cc @@ -173,7 +173,7 @@ struct Dff2dffeWorker return or_input; RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = module->addReduceOr(NEW_ID, or_input, y); + RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y); if (make_gates) { simplemap(module, c); -- 2.30.2