From 8cfae3b4c2f3f274040619f0cffc5b0ff087103c Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 18 Sep 2022 12:47:48 +0100
Subject: [PATCH]

---
 openpower/sv/rfc/ls001.mdwn | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 4a3c055db..2076a9529 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -353,7 +353,6 @@ multiplied by the element index and *substituted* for "D" when
 the immediate, D, is zero.  Modifications to support this
 "cheat" on top of pre-existing Scalar HDL (and Simulators)
 have both turned out to be minimal.[^mul]
-
 Also added was the option to perform signed or unsigned Effective
 Address calculation, which comes into play only on LD/ST Indexed,
 when elwidth overrides are used.  Another quirk: `RA` is never
@@ -394,12 +393,16 @@ or as Register-based.
 *All of the above modes are covered by Twin-Predication*
 
 In particular, a special predicate mode `1<<r3` uses the register `r3`
-*binary* value effectively as a single (Scalar) Index offset into
-what would otherwise be a Vector operation. Combined with the
+*binary* value, converted to single-bit unary mask,
+effectively as a single (Scalar) Index *runtime*-dynamic offset into
+a Vector.[^r3] Combined with the
 (mis-named) "mapreduce" mode when used as a source predicate
-a `VSPLAT` is performed.  When used as a destination predicate `1<<r3`
+a `VSPLAT` (broadcast) is performed.  When used as a destination
+predicate `1<<r3`
 provides `VINSERT` behaviour.
 
+[^r3]: Effectively: `GPR(RA+r3)`
+
 Also worth an explicit mention is that Twin Predication when using
 different source from destination predicate masks effectively combines
 back-to-back `VCOMPRESS` and `VEXPAND` (in a single instruction), and,
-- 
2.30.2