From 8d157f96538cb927156e184cfc94ae3580e43426 Mon Sep 17 00:00:00 2001
From: Doug Evans <dje@google.com>
Date: Fri, 20 Feb 1998 00:57:03 +0000
Subject: [PATCH] 	* m32r-opc.[ch]: Regenerate.

---
 opcodes/ChangeLog  |   4 +
 opcodes/m32r-opc.c | 757 +++++++++++++++++++++++----------------------
 opcodes/m32r-opc.h |   7 +-
 3 files changed, 395 insertions(+), 373 deletions(-)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3ad8bc111d1..7b329cc0a61 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+Thu Feb 19 16:51:13 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* m32r-opc.[ch]: Regenerate.
+
 start-sanitize-sky
 Thu Feb 19 02:11:39 1998  Doug Evans  <devans@charmed.cygnus.com>
 
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c
index 01645fb23eb..b69de02ee78 100644
--- a/opcodes/m32r-opc.c
+++ b/opcodes/m32r-opc.c
@@ -306,12 +306,14 @@ static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
   { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
   { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
   { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
+  { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
   { 0 }
 };
 
 /* The operand table.  */
 
-#define OP_ENT(op) m32r_cgen_operand_table[CONCAT2 (M32R_OPERAND_,op)]
+#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
+#define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
 {
 /* pc: program counter */
@@ -472,12 +474,14 @@ static const CGEN_OPERAND_INSTANCE fmt_7_addx_ops[] = {
 static const CGEN_OPERAND_INSTANCE fmt_8_bc8_ops[] = {
   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
+  { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_10_bc24_ops[] = {
   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
+  { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
   { 0 }
 };
 
@@ -485,18 +489,21 @@ static const CGEN_OPERAND_INSTANCE fmt_12_beq_ops[] = {
   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+  { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_13_beqz_ops[] = {
   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+  { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_14_bl8_ops[] = {
   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+  { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
   { 0 }
 };
@@ -504,6 +511,7 @@ static const CGEN_OPERAND_INSTANCE fmt_14_bl8_ops[] = {
 static const CGEN_OPERAND_INSTANCE fmt_15_bl24_ops[] = {
   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+  { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
   { 0 }
 };
@@ -512,6 +520,7 @@ static const CGEN_OPERAND_INSTANCE fmt_16_bcl8_ops[] = {
   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+  { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
   { 0 }
 };
@@ -520,17 +529,20 @@ static const CGEN_OPERAND_INSTANCE fmt_17_bcl24_ops[] = {
   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+  { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_18_bra8_ops[] = {
   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
+  { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_19_bra24_ops[] = {
   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
+  { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
   { 0 }
 };
 
@@ -571,18 +583,21 @@ static const CGEN_OPERAND_INSTANCE fmt_24_div_ops[] = {
 static const CGEN_OPERAND_INSTANCE fmt_25_jc_ops[] = {
   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+  { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_26_jl_ops[] = {
   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+  { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
   { 0 }
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_27_jmp_ops[] = {
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+  { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
   { 0 }
 };
 
@@ -658,8 +673,10 @@ static const CGEN_OPERAND_INSTANCE fmt_39_ldi16_ops[] = {
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_40_lock_ops[] = {
-  { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+  { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+  { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+  { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
   { 0 }
 };
 
@@ -743,18 +760,6 @@ static const CGEN_OPERAND_INSTANCE fmt_53_rac_ops[] = {
   { 0 }
 };
 
-static const CGEN_OPERAND_INSTANCE fmt_54_rac_d_ops[] = {
-  { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
-  { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
-  { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_55_rac_ds_ops[] = {
-  { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
-  { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
-  { 0 }
-};
-
 static const CGEN_OPERAND_INSTANCE fmt_56_rac_dsi_ops[] = {
   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
@@ -848,37 +853,45 @@ static const CGEN_OPERAND_INSTANCE fmt_69_st_plus_ops[] = {
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_70_trap_ops[] = {
+  { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+  { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 },
   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0 },
+  { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+  { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 },
+  { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 6 },
   { 0 }
 };
 
-static const CGEN_OPERAND_INSTANCE fmt_71_unlock_ops[] = {
+static const CGEN_OPERAND_INSTANCE fmt_72_unlock_ops[] = {
+  { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+  { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+  { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
   { 0 }
 };
 
-static const CGEN_OPERAND_INSTANCE fmt_74_satb_ops[] = {
+static const CGEN_OPERAND_INSTANCE fmt_75_satb_ops[] = {
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
   { 0 }
 };
 
-static const CGEN_OPERAND_INSTANCE fmt_75_sat_ops[] = {
+static const CGEN_OPERAND_INSTANCE fmt_76_sat_ops[] = {
   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
   { 0 }
 };
 
-static const CGEN_OPERAND_INSTANCE fmt_76_sadd_ops[] = {
+static const CGEN_OPERAND_INSTANCE fmt_77_sadd_ops[] = {
   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
   { 0 }
 };
 
-static const CGEN_OPERAND_INSTANCE fmt_77_macwu1_ops[] = {
+static const CGEN_OPERAND_INSTANCE fmt_78_macwu1_ops[] = {
   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
@@ -886,14 +899,14 @@ static const CGEN_OPERAND_INSTANCE fmt_77_macwu1_ops[] = {
   { 0 }
 };
 
-static const CGEN_OPERAND_INSTANCE fmt_78_mulwu1_ops[] = {
+static const CGEN_OPERAND_INSTANCE fmt_79_mulwu1_ops[] = {
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
   { 0 }
 };
 
-static const CGEN_OPERAND_INSTANCE fmt_79_sc_ops[] = {
+static const CGEN_OPERAND_INSTANCE fmt_80_sc_ops[] = {
   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
   { OUTPUT, & HW_ENT (HW_H_ABORT), CGEN_MODE_UBI, 0, 0 },
   { 0 }
@@ -902,118 +915,120 @@ static const CGEN_OPERAND_INSTANCE fmt_79_sc_ops[] = {
 #undef INPUT
 #undef OUTPUT
 
-#define OP 1 /* syntax value for mnemonic */
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 
 static const CGEN_SYNTAX syntax_table[] =
 {
-/* <op> $dr,$sr */
-/*   0 */  { OP, ' ', 130, ',', 129, 0 },
-/* <op> $dr,$sr,#$slo16 */
-/*   1 */  { OP, ' ', 130, ',', 129, ',', '#', 145, 0 },
-/* <op> $dr,$sr,$slo16 */
-/*   2 */  { OP, ' ', 130, ',', 129, ',', 145, 0 },
-/* <op> $dr,$sr,#$uimm16 */
-/*   3 */  { OP, ' ', 130, ',', 129, ',', '#', 139, 0 },
-/* <op> $dr,$sr,$uimm16 */
-/*   4 */  { OP, ' ', 130, ',', 129, ',', 139, 0 },
-/* <op> $dr,$sr,#$ulo16 */
-/*   5 */  { OP, ' ', 130, ',', 129, ',', '#', 146, 0 },
-/* <op> $dr,$sr,$ulo16 */
-/*   6 */  { OP, ' ', 130, ',', 129, ',', 146, 0 },
-/* <op> $dr,#$simm8 */
-/*   7 */  { OP, ' ', 130, ',', '#', 135, 0 },
-/* <op> $dr,$simm8 */
-/*   8 */  { OP, ' ', 130, ',', 135, 0 },
-/* <op> $dr,$sr,#$simm16 */
-/*   9 */  { OP, ' ', 130, ',', 129, ',', '#', 136, 0 },
-/* <op> $dr,$sr,$simm16 */
-/*  10 */  { OP, ' ', 130, ',', 129, ',', 136, 0 },
-/* <op> $disp8 */
-/*  11 */  { OP, ' ', 148, 0 },
-/* <op> $disp24 */
-/*  12 */  { OP, ' ', 150, 0 },
-/* <op> $src1,$src2,$disp16 */
-/*  13 */  { OP, ' ', 131, ',', 132, ',', 149, 0 },
-/* <op> $src2,$disp16 */
-/*  14 */  { OP, ' ', 132, ',', 149, 0 },
-/* <op> $src1,$src2 */
-/*  15 */  { OP, ' ', 131, ',', 132, 0 },
-/* <op> $src2,#$simm16 */
-/*  16 */  { OP, ' ', 132, ',', '#', 136, 0 },
-/* <op> $src2,$simm16 */
-/*  17 */  { OP, ' ', 132, ',', 136, 0 },
-/* <op> $src2,#$uimm16 */
-/*  18 */  { OP, ' ', 132, ',', '#', 139, 0 },
-/* <op> $src2,$uimm16 */
-/*  19 */  { OP, ' ', 132, ',', 139, 0 },
-/* <op> $src2 */
-/*  20 */  { OP, ' ', 132, 0 },
-/* <op> $sr */
-/*  21 */  { OP, ' ', 129, 0 },
-/* <op> $dr,@$sr */
-/*  22 */  { OP, ' ', 130, ',', '@', 129, 0 },
-/* <op> $dr,@($sr) */
-/*  23 */  { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
-/* <op> $dr,@($slo16,$sr) */
-/*  24 */  { OP, ' ', 130, ',', '@', '(', 145, ',', 129, ')', 0 },
-/* <op> $dr,@($sr,$slo16) */
-/*  25 */  { OP, ' ', 130, ',', '@', '(', 129, ',', 145, ')', 0 },
-/* <op> $dr,@$sr+ */
-/*  26 */  { OP, ' ', 130, ',', '@', 129, '+', 0 },
-/* <op> $dr,#$uimm24 */
-/*  27 */  { OP, ' ', 130, ',', '#', 147, 0 },
-/* <op> $dr,$uimm24 */
-/*  28 */  { OP, ' ', 130, ',', 147, 0 },
-/* <op> $dr,$slo16 */
-/*  29 */  { OP, ' ', 130, ',', 145, 0 },
-/* <op> $src1,$src2,$acc */
-/*  30 */  { OP, ' ', 131, ',', 132, ',', 143, 0 },
-/* <op> $dr */
-/*  31 */  { OP, ' ', 130, 0 },
-/* <op> $dr,$accs */
-/*  32 */  { OP, ' ', 130, ',', 142, 0 },
-/* <op> $dr,$scr */
-/*  33 */  { OP, ' ', 130, ',', 133, 0 },
-/* <op> $src1 */
-/*  34 */  { OP, ' ', 131, 0 },
-/* <op> $src1,$accs */
-/*  35 */  { OP, ' ', 131, ',', 142, 0 },
-/* <op> $sr,$dcr */
-/*  36 */  { OP, ' ', 129, ',', 134, 0 },
-/* <op> */
-/*  37 */  { OP, 0 },
-/* <op> $accd */
-/*  38 */  { OP, ' ', 141, 0 },
-/* <op> $accd,$accs */
-/*  39 */  { OP, ' ', 141, ',', 142, 0 },
-/* <op> $accd,$accs,#$imm1 */
-/*  40 */  { OP, ' ', 141, ',', 142, ',', '#', 140, 0 },
-/* <op> $dr,#$hi16 */
-/*  41 */  { OP, ' ', 130, ',', '#', 144, 0 },
-/* <op> $dr,$hi16 */
-/*  42 */  { OP, ' ', 130, ',', 144, 0 },
-/* <op> $dr,#$uimm5 */
-/*  43 */  { OP, ' ', 130, ',', '#', 138, 0 },
-/* <op> $dr,$uimm5 */
-/*  44 */  { OP, ' ', 130, ',', 138, 0 },
-/* <op> $src1,@$src2 */
-/*  45 */  { OP, ' ', 131, ',', '@', 132, 0 },
-/* <op> $src1,@($src2) */
-/*  46 */  { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
-/* <op> $src1,@($slo16,$src2) */
-/*  47 */  { OP, ' ', 131, ',', '@', '(', 145, ',', 132, ')', 0 },
-/* <op> $src1,@($src2,$slo16) */
-/*  48 */  { OP, ' ', 131, ',', '@', '(', 132, ',', 145, ')', 0 },
-/* <op> $src1,@+$src2 */
-/*  49 */  { OP, ' ', 131, ',', '@', '+', 132, 0 },
-/* <op> $src1,@-$src2 */
-/*  50 */  { OP, ' ', 131, ',', '@', '-', 132, 0 },
-/* <op> #$uimm4 */
-/*  51 */  { OP, ' ', '#', 137, 0 },
-/* <op> $uimm4 */
-/*  52 */  { OP, ' ', 137, 0 },
-};
-
+/* <mnem> $dr,$sr */
+/*   0 */  { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+/* <mnem> $dr,$sr,#$slo16 */
+/*   1 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SLO16), 0 },
+/* <mnem> $dr,$sr,$slo16 */
+/*   2 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SLO16), 0 },
+/* <mnem> $dr,$sr,#$uimm16 */
+/*   3 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (UIMM16), 0 },
+/* <mnem> $dr,$sr,$uimm16 */
+/*   4 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
+/* <mnem> $dr,$sr,#$ulo16 */
+/*   5 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (ULO16), 0 },
+/* <mnem> $dr,$sr,$ulo16 */
+/*   6 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (ULO16), 0 },
+/* <mnem> $dr,#$simm8 */
+/*   7 */  { MNEM, ' ', OP (DR), ',', '#', OP (SIMM8), 0 },
+/* <mnem> $dr,$simm8 */
+/*   8 */  { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
+/* <mnem> $dr,$sr,#$simm16 */
+/*   9 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SIMM16), 0 },
+/* <mnem> $dr,$sr,$simm16 */
+/*  10 */  { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
+/* <mnem> $disp8 */
+/*  11 */  { MNEM, ' ', OP (DISP8), 0 },
+/* <mnem> $disp24 */
+/*  12 */  { MNEM, ' ', OP (DISP24), 0 },
+/* <mnem> $src1,$src2,$disp16 */
+/*  13 */  { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
+/* <mnem> $src2,$disp16 */
+/*  14 */  { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
+/* <mnem> $src1,$src2 */
+/*  15 */  { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+/* <mnem> $src2,#$simm16 */
+/*  16 */  { MNEM, ' ', OP (SRC2), ',', '#', OP (SIMM16), 0 },
+/* <mnem> $src2,$simm16 */
+/*  17 */  { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
+/* <mnem> $src2,#$uimm16 */
+/*  18 */  { MNEM, ' ', OP (SRC2), ',', '#', OP (UIMM16), 0 },
+/* <mnem> $src2,$uimm16 */
+/*  19 */  { MNEM, ' ', OP (SRC2), ',', OP (UIMM16), 0 },
+/* <mnem> $src2 */
+/*  20 */  { MNEM, ' ', OP (SRC2), 0 },
+/* <mnem> $sr */
+/*  21 */  { MNEM, ' ', OP (SR), 0 },
+/* <mnem> $dr,@$sr */
+/*  22 */  { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
+/* <mnem> $dr,@($sr) */
+/*  23 */  { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
+/* <mnem> $dr,@($slo16,$sr) */
+/*  24 */  { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
+/* <mnem> $dr,@($sr,$slo16) */
+/*  25 */  { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
+/* <mnem> $dr,@$sr+ */
+/*  26 */  { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 },
+/* <mnem> $dr,#$uimm24 */
+/*  27 */  { MNEM, ' ', OP (DR), ',', '#', OP (UIMM24), 0 },
+/* <mnem> $dr,$uimm24 */
+/*  28 */  { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 },
+/* <mnem> $dr,$slo16 */
+/*  29 */  { MNEM, ' ', OP (DR), ',', OP (SLO16), 0 },
+/* <mnem> $src1,$src2,$acc */
+/*  30 */  { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
+/* <mnem> $dr */
+/*  31 */  { MNEM, ' ', OP (DR), 0 },
+/* <mnem> $dr,$accs */
+/*  32 */  { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
+/* <mnem> $dr,$scr */
+/*  33 */  { MNEM, ' ', OP (DR), ',', OP (SCR), 0 },
+/* <mnem> $src1 */
+/*  34 */  { MNEM, ' ', OP (SRC1), 0 },
+/* <mnem> $src1,$accs */
+/*  35 */  { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
+/* <mnem> $sr,$dcr */
+/*  36 */  { MNEM, ' ', OP (SR), ',', OP (DCR), 0 },
+/* <mnem> */
+/*  37 */  { MNEM, 0 },
+/* <mnem> $accd */
+/*  38 */  { MNEM, ' ', OP (ACCD), 0 },
+/* <mnem> $accd,$accs */
+/*  39 */  { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
+/* <mnem> $accd,$accs,#$imm1 */
+/*  40 */  { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', '#', OP (IMM1), 0 },
+/* <mnem> $dr,#$hi16 */
+/*  41 */  { MNEM, ' ', OP (DR), ',', '#', OP (HI16), 0 },
+/* <mnem> $dr,$hi16 */
+/*  42 */  { MNEM, ' ', OP (DR), ',', OP (HI16), 0 },
+/* <mnem> $dr,#$uimm5 */
+/*  43 */  { MNEM, ' ', OP (DR), ',', '#', OP (UIMM5), 0 },
+/* <mnem> $dr,$uimm5 */
+/*  44 */  { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
+/* <mnem> $src1,@$src2 */
+/*  45 */  { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
+/* <mnem> $src1,@($src2) */
+/*  46 */  { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
+/* <mnem> $src1,@($slo16,$src2) */
+/*  47 */  { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
+/* <mnem> $src1,@($src2,$slo16) */
+/*  48 */  { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
+/* <mnem> $src1,@+$src2 */
+/*  49 */  { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 },
+/* <mnem> $src1,@-$src2 */
+/*  50 */  { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 },
+/* <mnem> #$uimm4 */
+/*  51 */  { MNEM, ' ', '#', OP (UIMM4), 0 },
+/* <mnem> $uimm4 */
+/*  52 */  { MNEM, ' ', OP (UIMM4), 0 },
+};
+
+#undef MNEM
 #undef OP
 
 static const CGEN_FORMAT format_table[] = 
@@ -1034,29 +1049,29 @@ static const CGEN_FORMAT format_table[] =
 /*   6 */  { 32, 32, 0xf0f00000 },
 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(condbit UBI)(dr SI)(sr SI)(condbit UBI)(dr SI) */
 /*   7 */  { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM) */
+/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM)(pc USI) */
 /*   8 */  { 16, 16, 0xff00 },
 /* (f-op1 #)(f-r1 #)(f-disp8 disp8) */
 /*   9 */  { 16, 16, 0xff00 },
-/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM) */
+/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM)(pc USI) */
 /*  10 */  { 32, 32, 0xff000000 },
 /* (f-op1 #)(f-r1 #)(f-disp24 disp24) */
 /*  11 */  { 32, 32, 0xff000000 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src1 SI)(src2 SI) */
+/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src1 SI)(src2 SI)(pc USI) */
 /*  12 */  { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src2 SI) */
+/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src2 SI)(pc USI) */
 /*  13 */  { 32, 32, 0xfff00000 },
-/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM)(pc USI)(h-gr-14 SI) */
+/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM)(pc USI)(pc USI)(h-gr-14 SI) */
 /*  14 */  { 16, 16, 0xff00 },
-/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM)(pc USI)(h-gr-14 SI) */
+/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM)(pc USI)(pc USI)(h-gr-14 SI) */
 /*  15 */  { 32, 32, 0xff000000 },
-/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM)(pc USI)(h-gr-14 SI) */
+/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM)(pc USI)(pc USI)(h-gr-14 SI) */
 /*  16 */  { 16, 16, 0xff00 },
-/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM)(pc USI)(h-gr-14 SI) */
+/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM)(pc USI)(pc USI)(h-gr-14 SI) */
 /*  17 */  { 32, 32, 0xff000000 },
-/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM) */
+/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM)(pc USI) */
 /*  18 */  { 16, 16, 0xff00 },
-/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM) */
+/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM)(pc USI) */
 /*  19 */  { 32, 32, 0xff000000 },
 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(condbit UBI) */
 /*  20 */  { 16, 16, 0xf0f0 },
@@ -1068,11 +1083,11 @@ static const CGEN_FORMAT format_table[] =
 /*  23 */  { 16, 16, 0xfff0 },
 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 #)(dr SI)(sr SI)(dr SI) */
 /*  24 */  { 32, 32, 0xf0f0ffff },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(condbit UBI)(sr SI) */
+/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(condbit UBI)(sr SI)(pc USI) */
 /*  25 */  { 16, 16, 0xfff0 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(pc USI)(sr SI)(h-gr-14 SI) */
+/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(pc USI)(sr SI)(pc USI)(h-gr-14 SI) */
 /*  26 */  { 16, 16, 0xfff0 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(sr SI) */
+/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(sr SI)(pc USI) */
 /*  27 */  { 16, 16, 0xfff0 },
 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI) */
 /*  28 */  { 16, 16, 0xf0f0 },
@@ -1098,7 +1113,7 @@ static const CGEN_FORMAT format_table[] =
 /*  38 */  { 16, 16, 0xf000 },
 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-simm16 slo16)(slo16 HI)(dr SI) */
 /*  39 */  { 32, 32, 0xf0ff0000 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI) */
+/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI)(h-lock-0 UBI) */
 /*  40 */  { 16, 16, 0xf0f0 },
 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(accum DI)(src1 SI)(src2 SI)(accum DI) */
 /*  41 */  { 16, 16, 0xf0f0 },
@@ -1126,9 +1141,9 @@ static const CGEN_FORMAT format_table[] =
 /*  52 */  { 16, 16, 0xffff },
 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(accum DI)(accum DI) */
 /*  53 */  { 16, 16, 0xffff },
-/* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs #)(f-bit14 #)(f-imm1 #)(accum DI)(accd DI) */
+/* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs #)(f-bit14 #)(f-imm1 #) */
 /*  54 */  { 16, 16, 0xf3ff },
-/* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 #)(accs DI)(accd DI) */
+/* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 #) */
 /*  55 */  { 16, 16, 0xf3f3 },
 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 imm1)(accs DI)(imm1 USI)(accd DI) */
 /*  56 */  { 16, 16, 0xf3f2 },
@@ -1158,26 +1173,28 @@ static const CGEN_FORMAT format_table[] =
 /*  68 */  { 32, 32, 0xf0f00000 },
 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI)(src2 SI) */
 /*  69 */  { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-uimm4 uimm4)(uimm4 USI) */
+/* (f-op1 #)(f-r1 #)(f-op2 #)(f-uimm4 uimm4)(pc USI)(h-cr-0 SI)(uimm4 USI)(pc USI)(h-cr-0 SI)(h-cr-6 SI) */
 /*  70 */  { 16, 16, 0xfff0 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI) */
-/*  71 */  { 16, 16, 0xf0f0 },
+/* (f-op1 #)(f-r1 #)(f-op2 #)(f-uimm4 uimm4) */
+/*  71 */  { 16, 16, 0xfff0 },
+/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(h-lock-0 UBI)(src1 SI)(src2 SI)(h-memory-src2 SI)(h-lock-0 UBI) */
+/*  72 */  { 16, 16, 0xf0f0 },
 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #) */
-/*  72 */  { 16, 16, 0xf0ff },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #) */
 /*  73 */  { 16, 16, 0xf0ff },
+/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #) */
+/*  74 */  { 16, 16, 0xf0ff },
 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 #)(sr SI)(dr SI) */
-/*  74 */  { 32, 32, 0xf0f0ffff },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 #)(condbit UBI)(sr SI)(dr SI) */
 /*  75 */  { 32, 32, 0xf0f0ffff },
+/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 #)(condbit UBI)(sr SI)(dr SI) */
+/*  76 */  { 32, 32, 0xf0f0ffff },
 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-accums-0 DI)(h-accums-1 DI)(h-accums-0 DI) */
-/*  76 */  { 16, 16, 0xffff },
+/*  77 */  { 16, 16, 0xffff },
 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(h-accums-1 DI)(src1 SI)(src2 SI)(h-accums-1 DI) */
-/*  77 */  { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-accums-1 DI) */
 /*  78 */  { 16, 16, 0xf0f0 },
+/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-accums-1 DI) */
+/*  79 */  { 16, 16, 0xf0f0 },
 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(condbit UBI)(abort-parallel-execution UBI) */
-/*  79 */  { 16, 16, 0xffff },
+/*  80 */  { 16, 16, 0xffff },
 };
 
 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
@@ -1195,231 +1212,231 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "add", "add", SYN (0), FMT (0), 0xa0,
     & fmt_0_add_ops[0],
-    { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* add3 $dr,$sr,#$slo16 */
   {
     { 1, 1, 1, 1 },
     "add3", "add3", SYN (1), FMT (1), 0x80a00000,
     & fmt_1_add3_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* add3 $dr,$sr,$slo16 */
   {
     { 1, 1, 1, 1 },
     "add3.a", "add3", SYN (2), FMT (1), 0x80a00000,
     & fmt_1_add3_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* and $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "and", "and", SYN (0), FMT (0), 0xc0,
     & fmt_0_add_ops[0],
-    { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* and3 $dr,$sr,#$uimm16 */
   {
     { 1, 1, 1, 1 },
     "and3", "and3", SYN (3), FMT (2), 0x80c00000,
     & fmt_2_and3_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* and3 $dr,$sr,$uimm16 */
   {
     { 1, 1, 1, 1 },
     "and3.a", "and3", SYN (4), FMT (2), 0x80c00000,
     & fmt_2_and3_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* or $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "or", "or", SYN (0), FMT (0), 0xe0,
     & fmt_0_add_ops[0],
-    { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* or3 $dr,$sr,#$ulo16 */
   {
     { 1, 1, 1, 1 },
     "or3", "or3", SYN (5), FMT (3), 0x80e00000,
     & fmt_3_or3_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* or3 $dr,$sr,$ulo16 */
   {
     { 1, 1, 1, 1 },
     "or3.a", "or3", SYN (6), FMT (3), 0x80e00000,
     & fmt_3_or3_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* xor $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "xor", "xor", SYN (0), FMT (0), 0xd0,
     & fmt_0_add_ops[0],
-    { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* xor3 $dr,$sr,#$uimm16 */
   {
     { 1, 1, 1, 1 },
     "xor3", "xor3", SYN (3), FMT (2), 0x80d00000,
     & fmt_2_and3_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* xor3 $dr,$sr,$uimm16 */
   {
     { 1, 1, 1, 1 },
     "xor3.a", "xor3", SYN (4), FMT (2), 0x80d00000,
     & fmt_2_and3_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* addi $dr,#$simm8 */
   {
     { 1, 1, 1, 1 },
     "addi", "addi", SYN (7), FMT (4), 0x4000,
     & fmt_4_addi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* addi $dr,$simm8 */
   {
     { 1, 1, 1, 1 },
     "addi.a", "addi", SYN (8), FMT (4), 0x4000,
     & fmt_4_addi_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* addv $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "addv", "addv", SYN (0), FMT (5), 0x80,
     & fmt_5_addv_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* addv3 $dr,$sr,#$simm16 */
   {
     { 1, 1, 1, 1 },
     "addv3", "addv3", SYN (9), FMT (6), 0x80800000,
     & fmt_6_addv3_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* addv3 $dr,$sr,$simm16 */
   {
     { 1, 1, 1, 1 },
     "addv3.a", "addv3", SYN (10), FMT (6), 0x80800000,
     & fmt_6_addv3_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* addx $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "addx", "addx", SYN (0), FMT (7), 0x90,
     & fmt_7_addx_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* bc $disp8 */
   {
     { 1, 1, 1, 1 },
     "bc8", "bc", SYN (11), FMT (8), 0x7c00,
     & fmt_8_bc8_ops[0],
-    { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bc.s $disp8 */
   {
     { 1, 1, 1, 1 },
     "bc8.s", "bc.s", SYN (11), FMT (9), 0x7c00,
     0,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bc $disp24 */
   {
     { 1, 1, 1, 1 },
     "bc24", "bc", SYN (12), FMT (10), 0xfc000000,
     & fmt_10_bc24_ops[0],
-    { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bc.l $disp24 */
   {
     { 1, 1, 1, 1 },
     "bc24.l", "bc.l", SYN (12), FMT (11), 0xfc000000,
     0,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* beq $src1,$src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "beq", "beq", SYN (13), FMT (12), 0xb0000000,
     & fmt_12_beq_ops[0],
-    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* beqz $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "beqz", "beqz", SYN (14), FMT (13), 0xb0800000,
     & fmt_13_beqz_ops[0],
-    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bgez $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bgez", "bgez", SYN (14), FMT (13), 0xb0b00000,
     & fmt_13_beqz_ops[0],
-    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bgtz $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bgtz", "bgtz", SYN (14), FMT (13), 0xb0d00000,
     & fmt_13_beqz_ops[0],
-    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* blez $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "blez", "blez", SYN (14), FMT (13), 0xb0c00000,
     & fmt_13_beqz_ops[0],
-    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bltz $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bltz", "bltz", SYN (14), FMT (13), 0xb0a00000,
     & fmt_13_beqz_ops[0],
-    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bnez $src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bnez", "bnez", SYN (14), FMT (13), 0xb0900000,
     & fmt_13_beqz_ops[0],
-    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bl $disp8 */
   {
     { 1, 1, 1, 1 },
     "bl8", "bl", SYN (11), FMT (14), 0x7e00,
     & fmt_14_bl8_ops[0],
-    { 2, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bl.s $disp8 */
   {
     { 1, 1, 1, 1 },
     "bl8.s", "bl.s", SYN (11), FMT (9), 0x7e00,
     0,
-    { 2, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bl $disp24 */
   {
     { 1, 1, 1, 1 },
     "bl24", "bl", SYN (12), FMT (15), 0xfe000000,
     & fmt_15_bl24_ops[0],
-    { 2, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bl.l $disp24 */
   {
     { 1, 1, 1, 1 },
     "bl24.l", "bl.l", SYN (12), FMT (11), 0xfe000000,
     0,
-    { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* start-sanitize-m32rx */
 /* bcl $disp8 */
@@ -1427,7 +1444,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bcl8", "bcl", SYN (11), FMT (16), 0x7800,
     & fmt_16_bcl8_ops[0],
-    { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1436,7 +1453,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bcl8.s", "bcl.s", SYN (11), FMT (9), 0x7800,
     0,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1445,7 +1462,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bcl24", "bcl", SYN (12), FMT (17), 0xf8000000,
     & fmt_17_bcl24_ops[0],
-    { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1454,7 +1471,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bcl24.l", "bcl.l", SYN (12), FMT (11), 0xf8000000,
     0,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* bnc $disp8 */
@@ -1462,63 +1479,63 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bnc8", "bnc", SYN (11), FMT (8), 0x7d00,
     & fmt_8_bc8_ops[0],
-    { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bnc.s $disp8 */
   {
     { 1, 1, 1, 1 },
     "bnc8.s", "bnc.s", SYN (11), FMT (9), 0x7d00,
     0,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bnc $disp24 */
   {
     { 1, 1, 1, 1 },
     "bnc24", "bnc", SYN (12), FMT (10), 0xfd000000,
     & fmt_10_bc24_ops[0],
-    { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bnc.l $disp24 */
   {
     { 1, 1, 1, 1 },
     "bnc24.l", "bnc.l", SYN (12), FMT (11), 0xfd000000,
     0,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bne $src1,$src2,$disp16 */
   {
     { 1, 1, 1, 1 },
     "bne", "bne", SYN (13), FMT (12), 0xb0100000,
     & fmt_12_beq_ops[0],
-    { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bra $disp8 */
   {
     { 1, 1, 1, 1 },
     "bra8", "bra", SYN (11), FMT (18), 0x7f00,
     & fmt_18_bra8_ops[0],
-    { 2, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bra.s $disp8 */
   {
     { 1, 1, 1, 1 },
     "bra8.s", "bra.s", SYN (11), FMT (9), 0x7f00,
     0,
-    { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* bra $disp24 */
   {
     { 1, 1, 1, 1 },
     "bra24", "bra", SYN (12), FMT (19), 0xff000000,
     & fmt_19_bra24_ops[0],
-    { 2, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* bra.l $disp24 */
   {
     { 1, 1, 1, 1 },
     "bra24.l", "bra.l", SYN (12), FMT (11), 0xff000000,
     0,
-    { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* start-sanitize-m32rx */
 /* bncl $disp8 */
@@ -1526,7 +1543,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bncl8", "bncl", SYN (11), FMT (16), 0x7900,
     & fmt_16_bcl8_ops[0],
-    { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1535,7 +1552,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bncl8.s", "bncl.s", SYN (11), FMT (9), 0x7900,
     0,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1544,7 +1561,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bncl24", "bncl", SYN (12), FMT (17), 0xf9000000,
     & fmt_17_bcl24_ops[0],
-    { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1553,7 +1570,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "bncl24.l", "bncl.l", SYN (12), FMT (11), 0xf9000000,
     0,
-    { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* cmp $src1,$src2 */
@@ -1561,42 +1578,42 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "cmp", "cmp", SYN (15), FMT (20), 0x40,
     & fmt_20_cmp_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* cmpi $src2,#$simm16 */
   {
     { 1, 1, 1, 1 },
     "cmpi", "cmpi", SYN (16), FMT (21), 0x80400000,
     & fmt_21_cmpi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* cmpi $src2,$simm16 */
   {
     { 1, 1, 1, 1 },
     "cmpi.a", "cmpi", SYN (17), FMT (21), 0x80400000,
     & fmt_21_cmpi_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* cmpu $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "cmpu", "cmpu", SYN (15), FMT (20), 0x50,
     & fmt_20_cmp_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* cmpui $src2,#$uimm16 */
   {
     { 1, 1, 1, 1 },
     "cmpui", "cmpui", SYN (18), FMT (22), 0x80500000,
     & fmt_22_cmpui_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* cmpui $src2,$uimm16 */
   {
     { 1, 1, 1, 1 },
     "cmpui.a", "cmpui", SYN (19), FMT (22), 0x80500000,
     & fmt_22_cmpui_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* start-sanitize-m32rx */
 /* cmpeq $src1,$src2 */
@@ -1604,7 +1621,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "cmpeq", "cmpeq", SYN (15), FMT (20), 0x60,
     & fmt_20_cmp_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1613,7 +1630,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "cmpz", "cmpz", SYN (20), FMT (23), 0x70,
     & fmt_23_cmpz_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
   },
 /* end-sanitize-m32rx */
 /* div $dr,$sr */
@@ -1621,28 +1638,28 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "div", "div", SYN (0), FMT (24), 0x90000000,
     & fmt_24_div_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* divu $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "divu", "divu", SYN (0), FMT (24), 0x90100000,
     & fmt_24_div_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* rem $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "rem", "rem", SYN (0), FMT (24), 0x90200000,
     & fmt_24_div_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* remu $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "remu", "remu", SYN (0), FMT (24), 0x90300000,
     & fmt_24_div_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* start-sanitize-m32rx */
 /* divh $dr,$sr */
@@ -1650,7 +1667,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "divh", "divh", SYN (0), FMT (24), 0x90000010,
     & fmt_24_div_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1659,7 +1676,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "jc", "jc", SYN (21), FMT (25), 0x1cc0,
     & fmt_25_jc_ops[0],
-    { 2, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -1668,7 +1685,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "jnc", "jnc", SYN (21), FMT (25), 0x1dc0,
     & fmt_25_jc_ops[0],
-    { 2, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 /* jl $sr */
@@ -1676,231 +1693,231 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "jl", "jl", SYN (21), FMT (26), 0x1ec0,
     & fmt_26_jl_ops[0],
-    { 2, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* jmp $sr */
   {
     { 1, 1, 1, 1 },
     "jmp", "jmp", SYN (21), FMT (27), 0x1fc0,
     & fmt_27_jmp_ops[0],
-    { 2, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* ld $dr,@$sr */
   {
     { 1, 1, 1, 1 },
     "ld", "ld", SYN (22), FMT (28), 0x20c0,
     & fmt_28_ld_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* ld $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
     "ld-2", "ld", SYN (23), FMT (29), 0x20c0,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* ld $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
     "ld-d", "ld", SYN (24), FMT (30), 0xa0c00000,
     & fmt_30_ld_d_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ld $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
     "ld-d2", "ld", SYN (25), FMT (31), 0xa0c00000,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldb $dr,@$sr */
   {
     { 1, 1, 1, 1 },
     "ldb", "ldb", SYN (22), FMT (32), 0x2080,
     & fmt_32_ldb_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* ldb $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
     "ldb-2", "ldb", SYN (23), FMT (29), 0x2080,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* ldb $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
     "ldb-d", "ldb", SYN (24), FMT (33), 0xa0800000,
     & fmt_33_ldb_d_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldb $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
     "ldb-d2", "ldb", SYN (25), FMT (31), 0xa0800000,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldh $dr,@$sr */
   {
     { 1, 1, 1, 1 },
     "ldh", "ldh", SYN (22), FMT (34), 0x20a0,
     & fmt_34_ldh_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* ldh $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
     "ldh-2", "ldh", SYN (23), FMT (29), 0x20a0,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* ldh $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
     "ldh-d", "ldh", SYN (24), FMT (35), 0xa0a00000,
     & fmt_35_ldh_d_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldh $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
     "ldh-d2", "ldh", SYN (25), FMT (31), 0xa0a00000,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldub $dr,@$sr */
   {
     { 1, 1, 1, 1 },
     "ldub", "ldub", SYN (22), FMT (32), 0x2090,
     & fmt_32_ldb_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* ldub $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
     "ldub-2", "ldub", SYN (23), FMT (29), 0x2090,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* ldub $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
     "ldub-d", "ldub", SYN (24), FMT (33), 0xa0900000,
     & fmt_33_ldb_d_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldub $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
     "ldub-d2", "ldub", SYN (25), FMT (31), 0xa0900000,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* lduh $dr,@$sr */
   {
     { 1, 1, 1, 1 },
     "lduh", "lduh", SYN (22), FMT (34), 0x20b0,
     & fmt_34_ldh_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* lduh $dr,@($sr) */
   {
     { 1, 1, 1, 1 },
     "lduh-2", "lduh", SYN (23), FMT (29), 0x20b0,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* lduh $dr,@($slo16,$sr) */
   {
     { 1, 1, 1, 1 },
     "lduh-d", "lduh", SYN (24), FMT (35), 0xa0b00000,
     & fmt_35_ldh_d_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* lduh $dr,@($sr,$slo16) */
   {
     { 1, 1, 1, 1 },
     "lduh-d2", "lduh", SYN (25), FMT (31), 0xa0b00000,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ld $dr,@$sr+ */
   {
     { 1, 1, 1, 1 },
     "ld-plus", "ld", SYN (26), FMT (36), 0x20e0,
     & fmt_36_ld_plus_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* ld24 $dr,#$uimm24 */
   {
     { 1, 1, 1, 1 },
     "ld24", "ld24", SYN (27), FMT (37), 0xe0000000,
     & fmt_37_ld24_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ld24 $dr,$uimm24 */
   {
     { 1, 1, 1, 1 },
     "ld24.a", "ld24", SYN (28), FMT (37), 0xe0000000,
     & fmt_37_ld24_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldi $dr,#$simm8 */
   {
     { 1, 1, 1, 1 },
     "ldi8", "ldi", SYN (7), FMT (38), 0x6000,
     & fmt_38_ldi8_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* ldi $dr,$simm8 */
   {
     { 1, 1, 1, 1 },
     "ldi8.a", "ldi", SYN (8), FMT (38), 0x6000,
     & fmt_38_ldi8_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* ldi8 $dr,#$simm8 */
   {
     { 1, 1, 1, 1 },
     "ldi8a", "ldi8", SYN (7), FMT (38), 0x6000,
     & fmt_38_ldi8_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* ldi8 $dr,$simm8 */
   {
     { 1, 1, 1, 1 },
     "ldi8a.a", "ldi8", SYN (8), FMT (38), 0x6000,
     & fmt_38_ldi8_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
   },
 /* ldi $dr,$slo16 */
   {
     { 1, 1, 1, 1 },
     "ldi16", "ldi", SYN (29), FMT (39), 0x90f00000,
     & fmt_39_ldi16_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* ldi16 $dr,$slo16 */
   {
     { 1, 1, 1, 1 },
     "ldi16a", "ldi16", SYN (29), FMT (39), 0x90f00000,
     & fmt_39_ldi16_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* lock $dr,@$sr */
   {
     { 1, 1, 1, 1 },
     "lock", "lock", SYN (22), FMT (40), 0x20d0,
     & fmt_40_lock_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* machi $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "machi", "machi", SYN (15), FMT (41), 0x3040,
     & fmt_41_machi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* machi $src1,$src2,$acc */
@@ -1908,7 +1925,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "machi-a", "machi", SYN (30), FMT (42), 0x3040,
     & fmt_42_machi_a_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* maclo $src1,$src2 */
@@ -1916,7 +1933,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "maclo", "maclo", SYN (15), FMT (41), 0x3050,
     & fmt_41_machi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* maclo $src1,$src2,$acc */
@@ -1924,7 +1941,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "maclo-a", "maclo", SYN (30), FMT (42), 0x3050,
     & fmt_42_machi_a_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* macwhi $src1,$src2 */
@@ -1932,28 +1949,28 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "macwhi", "macwhi", SYN (15), FMT (41), 0x3060,
     & fmt_41_machi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* macwlo $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "macwlo", "macwlo", SYN (15), FMT (41), 0x3070,
     & fmt_41_machi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* mul $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "mul", "mul", SYN (0), FMT (0), 0x1060,
     & fmt_0_add_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* mulhi $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "mulhi", "mulhi", SYN (15), FMT (43), 0x3000,
     & fmt_43_mulhi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* mulhi $src1,$src2,$acc */
@@ -1961,7 +1978,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mulhi-a", "mulhi", SYN (30), FMT (44), 0x3000,
     & fmt_44_mulhi_a_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* mullo $src1,$src2 */
@@ -1969,7 +1986,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mullo", "mullo", SYN (15), FMT (43), 0x3010,
     & fmt_43_mulhi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* mullo $src1,$src2,$acc */
@@ -1977,7 +1994,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mullo-a", "mullo", SYN (30), FMT (44), 0x3010,
     & fmt_44_mulhi_a_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* mulwhi $src1,$src2 */
@@ -1985,28 +2002,28 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mulwhi", "mulwhi", SYN (15), FMT (43), 0x3020,
     & fmt_43_mulhi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* mulwlo $src1,$src2 */
   {
     { 1, 1, 1, 1 },
     "mulwlo", "mulwlo", SYN (15), FMT (43), 0x3030,
     & fmt_43_mulhi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* mv $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "mv", "mv", SYN (0), FMT (45), 0x1080,
     & fmt_45_mv_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* mvfachi $dr */
   {
     { 1, 1, 1, 1 },
     "mvfachi", "mvfachi", SYN (31), FMT (46), 0x50f0,
     & fmt_46_mvfachi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* mvfachi $dr,$accs */
@@ -2014,7 +2031,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvfachi-a", "mvfachi", SYN (32), FMT (47), 0x50f0,
     & fmt_47_mvfachi_a_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* mvfaclo $dr */
@@ -2022,7 +2039,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvfaclo", "mvfaclo", SYN (31), FMT (46), 0x50f1,
     & fmt_46_mvfachi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* mvfaclo $dr,$accs */
@@ -2030,7 +2047,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvfaclo-a", "mvfaclo", SYN (32), FMT (47), 0x50f1,
     & fmt_47_mvfachi_a_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* mvfacmi $dr */
@@ -2038,7 +2055,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvfacmi", "mvfacmi", SYN (31), FMT (46), 0x50f2,
     & fmt_46_mvfachi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* mvfacmi $dr,$accs */
@@ -2046,7 +2063,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvfacmi-a", "mvfacmi", SYN (32), FMT (47), 0x50f2,
     & fmt_47_mvfachi_a_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* mvfc $dr,$scr */
@@ -2054,14 +2071,14 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvfc", "mvfc", SYN (33), FMT (48), 0x1090,
     & fmt_48_mvfc_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* mvtachi $src1 */
   {
     { 1, 1, 1, 1 },
     "mvtachi", "mvtachi", SYN (34), FMT (49), 0x5070,
     & fmt_49_mvtachi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* mvtachi $src1,$accs */
@@ -2069,7 +2086,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvtachi-a", "mvtachi", SYN (35), FMT (50), 0x5070,
     & fmt_50_mvtachi_a_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* mvtaclo $src1 */
@@ -2077,7 +2094,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvtaclo", "mvtaclo", SYN (34), FMT (49), 0x5071,
     & fmt_49_mvtachi_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* mvtaclo $src1,$accs */
@@ -2085,7 +2102,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvtaclo-a", "mvtaclo", SYN (35), FMT (50), 0x5071,
     & fmt_50_mvtachi_a_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* mvtc $sr,$dcr */
@@ -2093,43 +2110,43 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "mvtc", "mvtc", SYN (36), FMT (51), 0x10a0,
     & fmt_51_mvtc_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* neg $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "neg", "neg", SYN (0), FMT (45), 0x30,
     & fmt_45_mv_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* nop */
   {
     { 1, 1, 1, 1 },
     "nop", "nop", SYN (37), FMT (52), 0x7000,
     0,
-    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* not $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "not", "not", SYN (0), FMT (45), 0xb0,
     & fmt_45_mv_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* rac */
   {
     { 1, 1, 1, 1 },
     "rac", "rac", SYN (37), FMT (53), 0x5090,
     & fmt_53_rac_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* rac $accd */
   {
     { 1, 1, 1, 1 },
     "rac-d", "rac", SYN (38), FMT (54), 0x5090,
-    & fmt_54_rac_d_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    0,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2137,8 +2154,8 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     "rac-ds", "rac", SYN (39), FMT (55), 0x5090,
-    & fmt_55_rac_ds_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    0,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2147,7 +2164,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "rac-dsi", "rac", SYN (40), FMT (56), 0x5090,
     & fmt_56_rac_dsi_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* rach */
@@ -2155,15 +2172,15 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "rach", "rach", SYN (37), FMT (53), 0x5080,
     & fmt_53_rac_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
   },
 /* start-sanitize-m32rx */
 /* rach $accd */
   {
     { 1, 1, 1, 1 },
     "rach-d", "rach", SYN (38), FMT (54), 0x5080,
-    & fmt_54_rac_d_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    0,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2171,8 +2188,8 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
   {
     { 1, 1, 1, 1 },
     "rach-ds", "rach", SYN (39), FMT (55), 0x5080,
-    & fmt_55_rac_ds_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    0,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2181,7 +2198,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "rach-dsi", "rach", SYN (40), FMT (56), 0x5080,
     & fmt_56_rac_dsi_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* rte */
@@ -2189,306 +2206,306 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "rte", "rte", SYN (37), FMT (57), 0x10d6,
     & fmt_57_rte_ops[0],
-    { 2, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* seth $dr,#$hi16 */
   {
     { 1, 1, 1, 1 },
     "seth", "seth", SYN (41), FMT (58), 0xd0c00000,
     & fmt_58_seth_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* seth $dr,$hi16 */
   {
     { 1, 1, 1, 1 },
     "seth.a", "seth", SYN (42), FMT (58), 0xd0c00000,
     & fmt_58_seth_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* sll $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "sll", "sll", SYN (0), FMT (0), 0x1040,
     & fmt_0_add_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* sll3 $dr,$sr,#$simm16 */
   {
     { 1, 1, 1, 1 },
     "sll3", "sll3", SYN (9), FMT (59), 0x90c00000,
     & fmt_59_sll3_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* sll3 $dr,$sr,$simm16 */
   {
     { 1, 1, 1, 1 },
     "sll3.a", "sll3", SYN (10), FMT (59), 0x90c00000,
     & fmt_59_sll3_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* slli $dr,#$uimm5 */
   {
     { 1, 1, 1, 1 },
     "slli", "slli", SYN (43), FMT (60), 0x5040,
     & fmt_60_slli_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* slli $dr,$uimm5 */
   {
     { 1, 1, 1, 1 },
     "slli.a", "slli", SYN (44), FMT (60), 0x5040,
     & fmt_60_slli_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* sra $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "sra", "sra", SYN (0), FMT (0), 0x1020,
     & fmt_0_add_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* sra3 $dr,$sr,#$simm16 */
   {
     { 1, 1, 1, 1 },
     "sra3", "sra3", SYN (9), FMT (59), 0x90a00000,
     & fmt_59_sll3_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* sra3 $dr,$sr,$simm16 */
   {
     { 1, 1, 1, 1 },
     "sra3.a", "sra3", SYN (10), FMT (59), 0x90a00000,
     & fmt_59_sll3_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* srai $dr,#$uimm5 */
   {
     { 1, 1, 1, 1 },
     "srai", "srai", SYN (43), FMT (60), 0x5020,
     & fmt_60_slli_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* srai $dr,$uimm5 */
   {
     { 1, 1, 1, 1 },
     "srai.a", "srai", SYN (44), FMT (60), 0x5020,
     & fmt_60_slli_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* srl $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "srl", "srl", SYN (0), FMT (0), 0x1000,
     & fmt_0_add_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* srl3 $dr,$sr,#$simm16 */
   {
     { 1, 1, 1, 1 },
     "srl3", "srl3", SYN (9), FMT (59), 0x90800000,
     & fmt_59_sll3_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* srl3 $dr,$sr,$simm16 */
   {
     { 1, 1, 1, 1 },
     "srl3.a", "srl3", SYN (10), FMT (59), 0x90800000,
     & fmt_59_sll3_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* srli $dr,#$uimm5 */
   {
     { 1, 1, 1, 1 },
     "srli", "srli", SYN (43), FMT (60), 0x5000,
     & fmt_60_slli_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* srli $dr,$uimm5 */
   {
     { 1, 1, 1, 1 },
     "srli.a", "srli", SYN (44), FMT (60), 0x5000,
     & fmt_60_slli_ops[0],
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* st $src1,@$src2 */
   {
     { 1, 1, 1, 1 },
     "st", "st", SYN (45), FMT (61), 0x2040,
     & fmt_61_st_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* st $src1,@($src2) */
   {
     { 1, 1, 1, 1 },
     "st-2", "st", SYN (46), FMT (62), 0x2040,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* st $src1,@($slo16,$src2) */
   {
     { 1, 1, 1, 1 },
     "st-d", "st", SYN (47), FMT (63), 0xa0400000,
     & fmt_63_st_d_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* st $src1,@($src2,$slo16) */
   {
     { 1, 1, 1, 1 },
     "st-d2", "st", SYN (48), FMT (64), 0xa0400000,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* stb $src1,@$src2 */
   {
     { 1, 1, 1, 1 },
     "stb", "stb", SYN (45), FMT (65), 0x2000,
     & fmt_65_stb_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* stb $src1,@($src2) */
   {
     { 1, 1, 1, 1 },
     "stb-2", "stb", SYN (46), FMT (62), 0x2000,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* stb $src1,@($slo16,$src2) */
   {
     { 1, 1, 1, 1 },
     "stb-d", "stb", SYN (47), FMT (66), 0xa0000000,
     & fmt_66_stb_d_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* stb $src1,@($src2,$slo16) */
   {
     { 1, 1, 1, 1 },
     "stb-d2", "stb", SYN (48), FMT (64), 0xa0000000,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* sth $src1,@$src2 */
   {
     { 1, 1, 1, 1 },
     "sth", "sth", SYN (45), FMT (67), 0x2020,
     & fmt_67_sth_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* sth $src1,@($src2) */
   {
     { 1, 1, 1, 1 },
     "sth-2", "sth", SYN (46), FMT (62), 0x2020,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
   },
 /* sth $src1,@($slo16,$src2) */
   {
     { 1, 1, 1, 1 },
     "sth-d", "sth", SYN (47), FMT (68), 0xa0200000,
     & fmt_68_sth_d_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* sth $src1,@($src2,$slo16) */
   {
     { 1, 1, 1, 1 },
     "sth-d2", "sth", SYN (48), FMT (64), 0xa0200000,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* st $src1,@+$src2 */
   {
     { 1, 1, 1, 1 },
     "st-plus", "st", SYN (49), FMT (69), 0x2060,
     & fmt_69_st_plus_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* st $src1,@-$src2 */
   {
     { 1, 1, 1, 1 },
     "st-minus", "st", SYN (50), FMT (69), 0x2070,
     & fmt_69_st_plus_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* sub $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "sub", "sub", SYN (0), FMT (0), 0x20,
     & fmt_0_add_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* subv $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "subv", "subv", SYN (0), FMT (5), 0x0,
     & fmt_5_addv_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* subx $dr,$sr */
   {
     { 1, 1, 1, 1 },
     "subx", "subx", SYN (0), FMT (7), 0x10,
     & fmt_7_addx_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
   },
 /* trap #$uimm4 */
   {
     { 1, 1, 1, 1 },
     "trap", "trap", SYN (51), FMT (70), 0x10f0,
     & fmt_70_trap_ops[0],
-    { 2, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* trap $uimm4 */
   {
     { 1, 1, 1, 1 },
-    "trap.a", "trap", SYN (52), FMT (70), 0x10f0,
-    & fmt_70_trap_ops[0],
-    { 2, 0|A(ALIAS)|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
+    "trap.a", "trap", SYN (52), FMT (71), 0x10f0,
+    0,
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
   },
 /* unlock $src1,@$src2 */
   {
     { 1, 1, 1, 1 },
-    "unlock", "unlock", SYN (45), FMT (71), 0x2050,
-    & fmt_71_unlock_ops[0],
-    { 2, 0, { (1<<MACH_M32R), PIPE_O } }
+    "unlock", "unlock", SYN (45), FMT (72), 0x2050,
+    & fmt_72_unlock_ops[0],
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
   },
 /* push $src1 */
   {
     { 1, 1, 1, 1 },
-    "push", "push", SYN (34), FMT (72), 0x207f,
+    "push", "push", SYN (34), FMT (73), 0x207f,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* pop $dr */
   {
     { 1, 1, 1, 1 },
-    "pop", "pop", SYN (31), FMT (73), 0x20ef,
+    "pop", "pop", SYN (31), FMT (74), 0x20ef,
     0,
-    { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
   },
 /* start-sanitize-m32rx */
 /* satb $dr,$sr */
   {
     { 1, 1, 1, 1 },
-    "satb", "satb", SYN (0), FMT (74), 0x80000100,
-    & fmt_74_satb_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
+    "satb", "satb", SYN (0), FMT (75), 0x80000100,
+    & fmt_75_satb_ops[0],
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
 /* sath $dr,$sr */
   {
     { 1, 1, 1, 1 },
-    "sath", "sath", SYN (0), FMT (74), 0x80000200,
-    & fmt_74_satb_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
+    "sath", "sath", SYN (0), FMT (75), 0x80000200,
+    & fmt_75_satb_ops[0],
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
 /* sat $dr,$sr */
   {
     { 1, 1, 1, 1 },
-    "sat", "sat", SYN (0), FMT (75), 0x80000000,
-    & fmt_75_sat_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
+    "sat", "sat", SYN (0), FMT (76), 0x80000000,
+    & fmt_76_sat_ops[0],
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2497,25 +2514,25 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "pcmpbz", "pcmpbz", SYN (20), FMT (23), 0x370,
     & fmt_23_cmpz_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
 /* sadd */
   {
     { 1, 1, 1, 1 },
-    "sadd", "sadd", SYN (37), FMT (76), 0x50e4,
-    & fmt_76_sadd_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    "sadd", "sadd", SYN (37), FMT (77), 0x50e4,
+    & fmt_77_sadd_ops[0],
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
 /* macwu1 $src1,$src2 */
   {
     { 1, 1, 1, 1 },
-    "macwu1", "macwu1", SYN (15), FMT (77), 0x50b0,
-    & fmt_77_macwu1_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    "macwu1", "macwu1", SYN (15), FMT (78), 0x50b0,
+    & fmt_78_macwu1_ops[0],
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
@@ -2524,43 +2541,43 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     "msblo", "msblo", SYN (15), FMT (41), 0x50d0,
     & fmt_41_machi_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
 /* mulwu1 $src1,$src2 */
   {
     { 1, 1, 1, 1 },
-    "mulwu1", "mulwu1", SYN (15), FMT (78), 0x50a0,
-    & fmt_78_mulwu1_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    "mulwu1", "mulwu1", SYN (15), FMT (79), 0x50a0,
+    & fmt_79_mulwu1_ops[0],
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
 /* maclh1 $src1,$src2 */
   {
     { 1, 1, 1, 1 },
-    "maclh1", "maclh1", SYN (15), FMT (77), 0x50c0,
-    & fmt_77_macwu1_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
+    "maclh1", "maclh1", SYN (15), FMT (78), 0x50c0,
+    & fmt_78_macwu1_ops[0],
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
 /* sc */
   {
     { 1, 1, 1, 1 },
-    "sc", "sc", SYN (37), FMT (79), 0x7401,
-    & fmt_79_sc_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_O } }
+    "sc", "sc", SYN (37), FMT (80), 0x7401,
+    & fmt_80_sc_ops[0],
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 /* start-sanitize-m32rx */
 /* snc */
   {
     { 1, 1, 1, 1 },
-    "snc", "snc", SYN (37), FMT (79), 0x7501,
-    & fmt_79_sc_ops[0],
-    { 2, 0, { (1<<MACH_M32RX), PIPE_O } }
+    "snc", "snc", SYN (37), FMT (80), 0x7501,
+    & fmt_80_sc_ops[0],
+    { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
   },
 /* end-sanitize-m32rx */
 };
diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h
index 8adf49e755a..09ad058cf07 100644
--- a/opcodes/m32r-opc.h
+++ b/opcodes/m32r-opc.h
@@ -133,7 +133,7 @@ typedef enum cgen_operand_attr {
 } CGEN_OPERAND_ATTR;
 
 /* Number of non-boolean elements in cgen_operand.  */
-#define CGEN_OPERAND_MAX_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
+#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
 
 /* Enum declaration for cgen_insn attrs.  */
 typedef enum cgen_insn_attr {
@@ -146,7 +146,7 @@ typedef enum cgen_insn_attr {
 } CGEN_INSN_ATTR;
 
 /* Number of non-boolean elements in cgen_insn.  */
-#define CGEN_INSN_MAX_ATTRS ((int) CGEN_INSN_ALIAS)
+#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
 
 /* Insn types are used by the simulator.  */
 /* Enum declaration for m32r instruction types.  */
@@ -387,7 +387,8 @@ typedef enum hw_type {
  , HW_H_ABORT
 /* end-sanitize-m32rx */
  , HW_H_COND, HW_H_SM, HW_H_BSM, HW_H_IE
- , HW_H_BIE, HW_H_BCOND, HW_H_BPC, HW_MAX
+ , HW_H_BIE, HW_H_BCOND, HW_H_BPC, HW_H_LOCK
+ , HW_MAX
 } HW_TYPE;
 
 #define MAX_HW ((int) HW_MAX)
-- 
2.30.2