From 8d2423d2003180faf7beeb7d9216ea58f21e822b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 27 Feb 2022 13:40:40 +0000 Subject: [PATCH] add PLL reset stability time option (defaults to 18 bits) to fpga/top-generic.vhdl --- fpga/top-generic.vhdl | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl index 66c65cc..3aabe93 100644 --- a/fpga/top-generic.vhdl +++ b/fpga/top-generic.vhdl @@ -10,6 +10,7 @@ entity toplevel is MEMORY_SIZE : positive := (384*1024); RAM_INIT_FILE : string := "firmware.hex"; RESET_LOW : boolean := true; + PLL_RESET_BITS : positive := 18; EXTERNAL_CORE : boolean := false; SIM_MAIN_BRAM : boolean := false; SIM_BRAM_CHAINBOOT : positive := 0; @@ -62,7 +63,8 @@ begin reset_controller: entity work.soc_reset generic map( - RESET_LOW => RESET_LOW + RESET_LOW => RESET_LOW, + PLL_RESET_BITS => PLL_RESET_BITS ) port map( ext_clk => ext_clk, -- 2.30.2