From 8d245016cc36ce7b43f95f6d4a14a72c91a829bb Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 9 Jun 2021 14:46:29 +0100
Subject: [PATCH] try setting actual clk to pllclk_o

---
 ls180soc.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/ls180soc.py b/ls180soc.py
index a240839..5f91d69 100755
--- a/ls180soc.py
+++ b/ls180soc.py
@@ -433,7 +433,8 @@ class LibreSoCSim(SoCCore):
             self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
             self.comb += pll_test_o.eq(self.cpu.pll_test_o) # "test" from PLL
             self.comb += pll_vco_o.eq(self.cpu.pll_vco_o) # PLL lock flag
-            self.comb += self.cpu.clk.eq(self.cpu.pllclk_o) # PLL out into cpu
+            clk = ClockSignal()
+            self.comb += clk.eq(self.cpu.pllclk_o) # PLL out into cpu
 
         #ram_init = []
 
-- 
2.30.2