From 8d287c2dfc6ab3e364c988f6ee2d5b65fb2ca82a Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sat, 29 Feb 2020 16:07:47 -0500 Subject: [PATCH] Add decoder/test for minor_19 field --- src/decoder/.gitignore | 1 + ...ower_major_decoder.py => power_decoder.py} | 47 +++++++------------ src/decoder/power_enums.py | 18 +++++++ ...major_decoder.py => test_power_decoder.py} | 30 +++++++----- 4 files changed, 55 insertions(+), 41 deletions(-) create mode 100644 src/decoder/.gitignore rename src/decoder/{power_major_decoder.py => power_decoder.py} (67%) rename src/decoder/test/{test_power_major_decoder.py => test_power_decoder.py} (78%) diff --git a/src/decoder/.gitignore b/src/decoder/.gitignore new file mode 100644 index 00000000..afed0735 --- /dev/null +++ b/src/decoder/.gitignore @@ -0,0 +1 @@ +*.csv diff --git a/src/decoder/power_major_decoder.py b/src/decoder/power_decoder.py similarity index 67% rename from src/decoder/power_major_decoder.py rename to src/decoder/power_decoder.py index d7cd6c8b..275c85a7 100644 --- a/src/decoder/power_major_decoder.py +++ b/src/decoder/power_decoder.py @@ -1,26 +1,13 @@ from nmigen import Module, Elaboratable, Signal from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel, - OutSel, RC, LdstLen, CryIn, get_csv) + OutSel, RC, LdstLen, CryIn, get_csv, single_bit_flags, + get_signal_name) -# names of the fields in major.csv that don't correspond to an enum -single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out', - 'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b', - 'sgn', 'lk', 'sgl pipe'] - - -def get_signal_name(name): - return name.lower().replace(' ', '_') - - - - -major_opcodes = get_csv("major.csv") - - -class PowerMajorDecoder(Elaboratable): - def __init__(self): - self.opcode_in = Signal(6, reset_less=True) +class PowerDecoder(Elaboratable): + def __init__(self, width, csvname): + self.opcodes = get_csv(csvname) + self.opcode_in = Signal(width, reset_less=True) self.function_unit = Signal(Function, reset_less=True) self.internal_op = Signal(InternalOp, reset_less=True) @@ -41,8 +28,8 @@ class PowerMajorDecoder(Elaboratable): comb = m.d.comb with m.Switch(self.opcode_in): - for row in major_opcodes: - opcode = int(row['opcode']) + for row in self.opcodes: + opcode = int(row['opcode'], 0) with m.Case(opcode): comb += self.function_unit.eq(Function[row['unit']]) comb += self.internal_op.eq(InternalOp[row['internal op']]) @@ -59,15 +46,15 @@ class PowerMajorDecoder(Elaboratable): return m def ports(self): - regular =[self.opcode_in, - self.function_unit, - self.in1_sel, - self.in2_sel, - self.in3_sel, - self.out_sel, - self.ldst_len, - self.rc_sel, - self.internal_op] + regular = [self.opcode_in, + self.function_unit, + self.in1_sel, + self.in2_sel, + self.in3_sel, + self.out_sel, + self.ldst_len, + self.rc_sel, + self.internal_op] single_bit_ports = [getattr(self, get_signal_name(x)) for x in single_bit_flags] return regular + single_bit_ports diff --git a/src/decoder/power_enums.py b/src/decoder/power_enums.py index 66c2029d..fc187dd8 100644 --- a/src/decoder/power_enums.py +++ b/src/decoder/power_enums.py @@ -3,6 +3,7 @@ import csv import os import requests + def get_csv(name): file_dir = os.path.dirname(os.path.realpath(__file__)) file_path = os.path.join(file_dir, name) @@ -15,6 +16,17 @@ def get_csv(name): reader = csv.DictReader(csvfile) return list(reader) + +# names of the fields in the tables that don't correspond to an enum +single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out', + 'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b', + 'sgn', 'lk', 'sgl pipe'] + + +def get_signal_name(name): + return name.lower().replace(' ', '_') + + @unique class Function(Enum): ALU = 0 @@ -35,6 +47,10 @@ class InternalOp(Enum): OP_STORE = 9 OP_TDI = 10 OP_XOR = 11 + OP_MCRF = 12 + OP_BCREG = 13 + OP_ISYNC = 14 + OP_ILLEGAL = 15 @unique @@ -55,6 +71,8 @@ class In2Sel(Enum): CONST_BD = 5 CONST_SH32 = 6 RB = 7 + NONE = 8 + SPR = 9 @unique diff --git a/src/decoder/test/test_power_major_decoder.py b/src/decoder/test/test_power_decoder.py similarity index 78% rename from src/decoder/test/test_power_major_decoder.py rename to src/decoder/test/test_power_decoder.py index 0cc46173..5f3f3e2e 100644 --- a/src/decoder/test/test_power_major_decoder.py +++ b/src/decoder/test/test_power_decoder.py @@ -3,19 +3,20 @@ from nmigen.back.pysim import Simulator, Delay from nmigen.test.utils import FHDLTestCase from nmigen.cli import rtlil import sys +import os import unittest sys.path.append("../") -from power_major_decoder import (PowerMajorDecoder, single_bit_flags, - get_signal_name, major_opcodes) +from power_decoder import (PowerDecoder) from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel, - OutSel, RC, LdstLen, CryIn) + OutSel, RC, LdstLen, CryIn, single_bit_flags, + get_signal_name) class DecoderTestCase(FHDLTestCase): - def test_function_unit(self): + def run_test(self, width, csvname): m = Module() comb = m.d.comb - opcode = Signal(6) + opcode = Signal(width) function_unit = Signal(Function) internal_op = Signal(InternalOp) in1_sel = Signal(In1Sel) @@ -26,7 +27,7 @@ class DecoderTestCase(FHDLTestCase): ldst_len = Signal(LdstLen) cry_in = Signal(CryIn) - m.submodules.dut = dut = PowerMajorDecoder() + m.submodules.dut = dut = PowerDecoder(width, csvname) comb += [dut.opcode_in.eq(opcode), function_unit.eq(dut.function_unit), in1_sel.eq(dut.in1_sel), @@ -41,8 +42,8 @@ class DecoderTestCase(FHDLTestCase): sim = Simulator(m) def process(): - for row in major_opcodes: - yield opcode.eq(int(row['opcode'])) + for row in dut.opcodes: + yield opcode.eq(int(row['opcode'], 0)) yield Delay(1e-6) signals = [(function_unit, Function, 'unit'), (internal_op, InternalOp, 'internal op'), @@ -70,12 +71,19 @@ class DecoderTestCase(FHDLTestCase): in1_sel, in2_sel]): sim.run() - def test_ilang(self): - dut = PowerMajorDecoder() + def generate_ilang(self, width, csvname): + prefix = os.path.splitext(csvname)[0] + dut = PowerDecoder(width, csvname) vl = rtlil.convert(dut, ports=dut.ports()) - with open("power_major_decoder.il", "w") as f: + with open("%s_decoder.il" % prefix, "w") as f: f.write(vl) + def test_major(self): + self.run_test(6, "major.csv") + + def test_minor_19(self): + self.run_test(3, "minor_19.csv") + if __name__ == "__main__": unittest.main() -- 2.30.2