From 8d3d61ba9840ddbf6424a368aaab86e678404078 Mon Sep 17 00:00:00 2001
From: Robert Jordens <jordens@gmail.com>
Date: Tue, 3 Dec 2013 14:12:40 -0700
Subject: [PATCH] fhdl.size: rename to bitcontainer

---
 doc/api.rst                             | 4 ++--
 migen/fhdl/{size.py => bitcontainer.py} | 0
 migen/fhdl/specials.py                  | 2 +-
 migen/fhdl/std.py                       | 2 +-
 migen/fhdl/structure.py                 | 4 ++--
 migen/fhdl/tools.py                     | 2 +-
 migen/fhdl/verilog.py                   | 2 +-
 migen/genlib/cdc.py                     | 2 +-
 8 files changed, 9 insertions(+), 9 deletions(-)
 rename migen/fhdl/{size.py => bitcontainer.py} (100%)

diff --git a/doc/api.rst b/doc/api.rst
index d49b9b70..1181773c 100644
--- a/doc/api.rst
+++ b/doc/api.rst
@@ -8,10 +8,10 @@ migen API Documentation
         :members:
         :show-inheritance:
 
-:mod:`fhdl.size` Module
+:mod:`fhdl.bitcontainer` Module
 ------------------------------
 
-.. automodule:: migen.fhdl.size
+.. automodule:: migen.fhdl.bitcontainer
         :members:
         :show-inheritance:
 
diff --git a/migen/fhdl/size.py b/migen/fhdl/bitcontainer.py
similarity index 100%
rename from migen/fhdl/size.py
rename to migen/fhdl/bitcontainer.py
diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
index ad11f578..ae0a2e63 100644
--- a/migen/fhdl/specials.py
+++ b/migen/fhdl/specials.py
@@ -1,7 +1,7 @@
 from operator import itemgetter
 
 from migen.fhdl.structure import *
-from migen.fhdl.size import bits_for, value_bits_sign
+from migen.fhdl.bitcontainer import bits_for, value_bits_sign
 from migen.fhdl.tools import *
 from migen.fhdl.tracer import get_obj_var_name
 from migen.fhdl.verilog import _printexpr as verilog_printexpr
diff --git a/migen/fhdl/std.py b/migen/fhdl/std.py
index b9ec729f..2007ff3f 100644
--- a/migen/fhdl/std.py
+++ b/migen/fhdl/std.py
@@ -1,5 +1,5 @@
 from migen.fhdl.structure import *
 from migen.fhdl.module import Module
 from migen.fhdl.specials import TSTriple, Instance, Memory
-from migen.fhdl.size import log2_int, bits_for, flen, fiter, fslice, freversed
+from migen.fhdl.bitcontainer import log2_int, bits_for, flen, fiter, fslice, freversed
 from migen.fhdl.decorators import DecorateModule, InsertCE, InsertReset, RenameClockDomains
diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index aba747b3..9b31e696 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -79,7 +79,7 @@ class Value(HUID):
 	
 	
 	def __getitem__(self, key):
-		from migen.fhdl.size import flen
+		from migen.fhdl.bitcontainer import flen
 
 		if isinstance(key, int):
 			if key < 0:
@@ -242,7 +242,7 @@ class Signal(Value):
 	related : Signal or None
 	"""
 	def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None, related=None):
-		from migen.fhdl.size import bits_for
+		from migen.fhdl.bitcontainer import bits_for
 
 		Value.__init__(self)
 		
diff --git a/migen/fhdl/tools.py b/migen/fhdl/tools.py
index b25280ba..00c9932f 100644
--- a/migen/fhdl/tools.py
+++ b/migen/fhdl/tools.py
@@ -1,7 +1,7 @@
 from migen.fhdl.structure import *
 from migen.fhdl.structure import _Slice, _Assign
 from migen.fhdl.visit import NodeVisitor, NodeTransformer
-from migen.fhdl.size import value_bits_sign
+from migen.fhdl.bitcontainer import value_bits_sign
 from migen.util.misc import flat_iteration
 
 class _SignalLister(NodeVisitor):
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 10bd7e37..fc56f784 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -4,7 +4,7 @@ from operator import itemgetter
 from migen.fhdl.structure import *
 from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
 from migen.fhdl.tools import *
-from migen.fhdl.size import bits_for, flen
+from migen.fhdl.bitcontainer import bits_for, flen
 from migen.fhdl.namer import Namespace, build_namespace
 
 def _printsig(ns, s):
diff --git a/migen/genlib/cdc.py b/migen/genlib/cdc.py
index 773c7b2c..9cdca4ab 100644
--- a/migen/genlib/cdc.py
+++ b/migen/genlib/cdc.py
@@ -1,5 +1,5 @@
 from migen.fhdl.std import *
-from migen.fhdl.size import value_bits_sign
+from migen.fhdl.bitcontainer import value_bits_sign
 from migen.fhdl.specials import Special
 from migen.fhdl.tools import list_signals
 
-- 
2.30.2