From 8d4a42887ecd5319de1553d9ad6077d2d97ee6ef Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 24 Feb 2012 15:44:51 +0100 Subject: [PATCH] ddrphy: working on hardware, simulation a bit messed up --- software/bios/ddrinit.c | 2 -- tb/s6ddrphy/tb_s6ddrphy.v | 6 ++--- verilog/s6ddrphy/s6ddrphy.v | 45 ++++++++++++++++++++++++------------- 3 files changed, 31 insertions(+), 22 deletions(-) diff --git a/software/bios/ddrinit.c b/software/bios/ddrinit.c index 7b199147..563221a1 100644 --- a/software/bios/ddrinit.c +++ b/software/bios/ddrinit.c @@ -61,7 +61,6 @@ static void init_sequence(void) /* Load Mode Register */ setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */ - //setaddr(0x0162); /* Reset DLL, CL=2.5, BL=4 */ CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS; cdelay(200); @@ -78,7 +77,6 @@ static void init_sequence(void) /* Load Mode Register */ setaddr(0x0032); /* CL=3, BL=4 */ - //setaddr(0x0062); /* CL=2.5, BL=4 */ CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS; cdelay(200); } diff --git a/tb/s6ddrphy/tb_s6ddrphy.v b/tb/s6ddrphy/tb_s6ddrphy.v index d3203e32..13c41e79 100644 --- a/tb/s6ddrphy/tb_s6ddrphy.v +++ b/tb/s6ddrphy/tb_s6ddrphy.v @@ -123,14 +123,13 @@ initial begin `ifdef TEST_WRITE #13; dfi_address_p1 <= 13'h0dbe; - #12; - dfi_address_p1 <= 0; dfi_wrdata_en_p1 <= 1; dfi_wrdata_mask_p0 <= 8'h12; dfi_wrdata_mask_p1 <= 8'h34; dfi_wrdata_p0 <= 64'hcafebabeabadface; dfi_wrdata_p1 <= 64'h0123456789abcdef; #12; + dfi_address_p1 <= 0; dfi_wrdata_en_p1 <= 0; dfi_wrdata_mask_p0 <= 0; dfi_wrdata_mask_p1 <= 0; @@ -142,10 +141,9 @@ initial begin `ifdef TEST_READ #13; dfi_address_p0 <= 13'h1234; - #12; - dfi_address_p0 <= 0; dfi_rddata_en_p0 <= 1; #12; + dfi_address_p0 <= 0; dfi_rddata_en_p0 <= 0; #15.5; dq_tb <= 32'h12345678; diff --git a/verilog/s6ddrphy/s6ddrphy.v b/verilog/s6ddrphy/s6ddrphy.v index a20bc650..d9a46399 100644 --- a/verilog/s6ddrphy/s6ddrphy.v +++ b/verilog/s6ddrphy/s6ddrphy.v @@ -218,7 +218,19 @@ endgenerate always @(posedge clk2x_270) postamble <= drive_dqs; +reg [NUM_D-1:0] d_dfi_wrdata_p0; +reg [NUM_D-1:0] d_dfi_wrdata_p1; +reg [NUM_D/8-1:0] d_dfi_wrdata_mask_p0; +reg [NUM_D/8-1:0] d_dfi_wrdata_mask_p1; +always @(posedge sys_clk) begin + d_dfi_wrdata_p0 <= dfi_wrdata_p0; + d_dfi_wrdata_p1 <= dfi_wrdata_p1; + d_dfi_wrdata_mask_p0 <= dfi_wrdata_mask_p0; + d_dfi_wrdata_mask_p1 <= dfi_wrdata_mask_p1; +end + wire drive_dq; +wire d_drive_dq; wire [NUM_D/2-1:0] dq_i; wire [NUM_D/2-1:0] dq_o; wire [NUM_D/2-1:0] dq_t; @@ -239,14 +251,14 @@ generate .IOCE(clk4x_wr_strb), .RST(1'b0), .CLKDIV(sys_clk), - .D1(dfi_wrdata_p0[i+NUM_D/2]), - .D2(dfi_wrdata_p0[i]), - .D3(dfi_wrdata_p1[i+NUM_D/2]), - .D4(dfi_wrdata_p1[i]), + .D1(d_dfi_wrdata_p0[i]), + .D2(d_dfi_wrdata_p1[i+NUM_D/2]), + .D3(d_dfi_wrdata_p1[i]), + .D4(dfi_wrdata_p0[i+NUM_D/2]), .TQ(dq_t[i]), - .T1(~drive_dq), - .T2(~drive_dq), - .T3(~drive_dq), + .T1(~d_drive_dq), + .T2(~d_drive_dq), + .T3(~d_drive_dq), .T4(~drive_dq), .TRAIN(1'b0), .TCE(1'b1), @@ -313,10 +325,10 @@ generate .IOCE(clk4x_wr_strb), .RST(1'b0), .CLKDIV(sys_clk), - .D1(dfi_wrdata_mask_p0[i+NUM_D/16]), - .D2(dfi_wrdata_mask_p0[i]), - .D3(dfi_wrdata_mask_p1[i+NUM_D/16]), - .D4(dfi_wrdata_mask_p1[i]), + .D1(d_dfi_wrdata_mask_p0[i]), + .D2(d_dfi_wrdata_mask_p1[i+NUM_D/16]), + .D3(d_dfi_wrdata_mask_p1[i]), + .D4(dfi_wrdata_mask_p0[i+NUM_D/16]), .TQ(), .T1(), .T2(), @@ -344,16 +356,17 @@ reg d_dfi_wrdata_en_p1; always @(posedge sys_clk) d_dfi_wrdata_en_p1 <= dfi_wrdata_en_p1; +assign drive_dq = dfi_wrdata_en_p1; +assign d_drive_dq = d_dfi_wrdata_en_p1; + reg r_dfi_wrdata_en; -always @(posedge clk2x_270) - r_dfi_wrdata_en <= d_dfi_wrdata_en_p1; - reg r2_dfi_wrdata_en; -always @(posedge clk2x_270) +always @(posedge clk2x_270) begin + r_dfi_wrdata_en <= d_dfi_wrdata_en_p1; r2_dfi_wrdata_en <= r_dfi_wrdata_en; +end assign drive_dqs = r2_dfi_wrdata_en; -assign drive_dq = d_dfi_wrdata_en_p1; wire rddata_valid; reg [4:0] rddata_sr; -- 2.30.2