From 8d4f237b9fb6e4313a2f87d876027cddc1eb3972 Mon Sep 17 00:00:00 2001 From: Julia Koval Date: Wed, 29 Nov 2017 19:19:34 +0100 Subject: [PATCH] Enable VBMI2 support [6/7] gcc/ * config/i386/avx512vbmi2intrin.h (_mm512_shrdv_epi16, _mm512_mask_shrdv_epi16, _mm512_maskz_shrdv_epi16, _mm512_shrdv_epi32, _mm512_mask_shrdv_epi32, _mm512_maskz_shrdv_epi32, _mm512_shrdv_epi64, _mm512_mask_shrdv_epi64, _mm512_maskz_shrdv_epi64): New intrinsics. * config/i386/avx512vbmi2vlintrin.h (_mm256_shrdv_epi16, _mm256_mask_shrdv_epi16, _mm256_maskz_shrdv_epi16, _mm256_shrdv_epi32, _mm256_mask_shrdv_epi32, _mm256_maskz_shrdv_epi32, _mm256_shrdv_epi64, _mm256_mask_shrdv_epi64, _mm256_maskz_shrdv_epi64, _mm_shrdv_epi16, _mm_mask_shrdv_epi16, _mm_maskz_shrdv_epi16, _mm_shrdv_epi32, _mm_mask_shrdv_epi32, _mm_maskz_shrdv_epi32, _mm_shrdv_epi64, _mm_mask_shrdv_epi64, _mm_maskz_shrdv_epi64): Ditto. * config/i386/i386-builtin-types.def (V32HI_FTYPE_V32HI_V32HI_V32HI, V32HI_FTYPE_V32HI_V32HI_V32HI_INT, V16HI_FTYPE_V16HI_V16HI_V16HI_INT, V8HI_FTYPE_V8HI_V8HI_V8HI_INT, V8SI_FTYPE_V8SI_V8SI_V8SI_INT, V4SI_FTYPE_V4SI_V4SI_V4SI_INT, V8DI_FTYPE_V8DI_V8DI_V8DI, V8DI_FTYPE_V8DI_V8DI_V8DI_INT, V4DI_FTYPE_V4DI_V4DI_V4DI_INT, V16SI_FTYPE_V16SI_V16SI_V16SI, V16SI_FTYPE_V16SI_V16SI_V16SI_INT, V2DI_FTYPE_V2DI_V2DI_V2DI_INT): New types. * config/i386/i386.c (ix86_expand_args_builtin): Handle new types. * config/i386/sse.md (vpshrdv_, vpshrdv__mask, vpshrdv__maskz, vpshrdv__maskz_1): New pattern. gcc/testsuite/ * gcc.target/i386/avx512f-vpshrdv-1.c: New test. * gcc.target/i386/avx512f-vpshrdvd-2.c: Ditto. * gcc.target/i386/avx512f-vpshrdvq-2.c: Ditto. * gcc.target/i386/avx512f-vpshrdvw-2.c: Ditto. * gcc.target/i386/avx512f-vpshrdw-2.c: Ditto. * gcc.target/i386/avx512vl-vpshrdv-1.c: Ditto. * gcc.target/i386/avx512vl-vpshrdvd-2.c: Ditto. * gcc.target/i386/avx512vl-vpshrdvq-2.c: Ditto. * gcc.target/i386/avx512vl-vpshrdvw-2.c: Ditto. * gcc.target/i386/avx512vl-vpshrdw-2.c: Ditto. From-SVN: r255249 --- gcc/ChangeLog | 24 +++ gcc/config/i386/avx512vbmi2intrin.h | 73 +++++++++ gcc/config/i386/avx512vbmi2vlintrin.h | 146 ++++++++++++++++++ gcc/config/i386/i386-builtin-types.def | 12 ++ gcc/config/i386/i386-builtin.def | 28 ++++ gcc/config/i386/i386.c | 16 ++ gcc/config/i386/sse.md | 57 +++++++ gcc/testsuite/ChangeLog | 13 ++ .../gcc.target/i386/avx512f-vpshrdv-1.c | 36 +++++ .../gcc.target/i386/avx512f-vpshrdvd-2.c | 62 ++++++++ .../gcc.target/i386/avx512f-vpshrdvq-2.c | 62 ++++++++ .../gcc.target/i386/avx512f-vpshrdvw-2.c | 62 ++++++++ .../gcc.target/i386/avx512f-vpshrdw-2.c | 62 ++++++++ .../gcc.target/i386/avx512vl-vpshrdv-1.c | 54 +++++++ .../gcc.target/i386/avx512vl-vpshrdvd-2.c | 16 ++ .../gcc.target/i386/avx512vl-vpshrdvq-2.c | 16 ++ .../gcc.target/i386/avx512vl-vpshrdvw-2.c | 16 ++ .../gcc.target/i386/avx512vl-vpshrdw-2.c | 16 ++ 18 files changed, 771 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vpshrdv-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vpshrdvd-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vpshrdvq-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vpshrdvw-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vpshrdw-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpshrdv-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpshrdvd-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpshrdvq-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpshrdvw-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpshrdw-2.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 19099451ed1..f421b64fd62 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,27 @@ +2017-11-29 Julia Koval + + * config/i386/avx512vbmi2intrin.h (_mm512_shrdv_epi16, + _mm512_mask_shrdv_epi16, _mm512_maskz_shrdv_epi16, _mm512_shrdv_epi32, + _mm512_mask_shrdv_epi32, _mm512_maskz_shrdv_epi32, _mm512_shrdv_epi64, + _mm512_mask_shrdv_epi64, _mm512_maskz_shrdv_epi64): New intrinsics. + * config/i386/avx512vbmi2vlintrin.h (_mm256_shrdv_epi16, + _mm256_mask_shrdv_epi16, _mm256_maskz_shrdv_epi16, _mm256_shrdv_epi32, + _mm256_mask_shrdv_epi32, _mm256_maskz_shrdv_epi32, _mm256_shrdv_epi64, + _mm256_mask_shrdv_epi64, _mm256_maskz_shrdv_epi64, _mm_shrdv_epi16, + _mm_mask_shrdv_epi16, _mm_maskz_shrdv_epi16, _mm_shrdv_epi32, + _mm_mask_shrdv_epi32, _mm_maskz_shrdv_epi32, _mm_shrdv_epi64, + _mm_mask_shrdv_epi64, _mm_maskz_shrdv_epi64): Ditto. + * config/i386/i386-builtin-types.def (V32HI_FTYPE_V32HI_V32HI_V32HI, + V32HI_FTYPE_V32HI_V32HI_V32HI_INT, V16HI_FTYPE_V16HI_V16HI_V16HI_INT, + V8HI_FTYPE_V8HI_V8HI_V8HI_INT, V8SI_FTYPE_V8SI_V8SI_V8SI_INT, + V4SI_FTYPE_V4SI_V4SI_V4SI_INT, V8DI_FTYPE_V8DI_V8DI_V8DI, + V8DI_FTYPE_V8DI_V8DI_V8DI_INT, V4DI_FTYPE_V4DI_V4DI_V4DI_INT, + V16SI_FTYPE_V16SI_V16SI_V16SI, V16SI_FTYPE_V16SI_V16SI_V16SI_INT, + V2DI_FTYPE_V2DI_V2DI_V2DI_INT): New types. + * config/i386/i386.c (ix86_expand_args_builtin): Handle new types. + * config/i386/sse.md (vpshrdv_, vpshrdv__mask, + vpshrdv__maskz, vpshrdv__maskz_1): New pattern. + 2017-11-29 Daniel Cederman * config/sparc/sparc.c (sparc_do_work_around_errata): Treat the diff --git a/gcc/config/i386/avx512vbmi2intrin.h b/gcc/config/i386/avx512vbmi2intrin.h index 0a7c2b9c412..1fed406db40 100644 --- a/gcc/config/i386/avx512vbmi2intrin.h +++ b/gcc/config/i386/avx512vbmi2intrin.h @@ -361,6 +361,79 @@ _mm512_maskz_shldi_epi64 (__mmask8 __A, __m512i __B, __m512i __C, int __D) (__v8di)(__m512i)_mm512_setzero_si512 (), (__mmask8)(A)) #endif +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_shrdv_epi16 (__m512i __A, __m512i __B, __m512i __C) +{ + return (__m512i) __builtin_ia32_vpshrdv_v32hi ((__v32hi)__A, (__v32hi) __B, + (__v32hi) __C); +} + +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_shrdv_epi16 (__m512i __A, __mmask32 __B, __m512i __C, __m512i __D) +{ + return (__m512i)__builtin_ia32_vpshrdv_v32hi_mask ((__v32hi)__A, + (__v32hi) __C, (__v32hi) __D, (__mmask32)__B); +} + +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_shrdv_epi16 (__mmask32 __A, __m512i __B, __m512i __C, __m512i __D) +{ + return (__m512i)__builtin_ia32_vpshrdv_v32hi_maskz ((__v32hi)__B, + (__v32hi) __C, (__v32hi) __D, (__mmask32)__A); +} + +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_shrdv_epi32 (__m512i __A, __m512i __B, __m512i __C) +{ + return (__m512i) __builtin_ia32_vpshrdv_v16si ((__v16si)__A, (__v16si) __B, + (__v16si) __C); +} + +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_shrdv_epi32 (__m512i __A, __mmask16 __B, __m512i __C, __m512i __D) +{ + return (__m512i)__builtin_ia32_vpshrdv_v16si_mask ((__v16si)__A, + (__v16si) __C, (__v16si) __D, (__mmask16)__B); +} + +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_shrdv_epi32 (__mmask16 __A, __m512i __B, __m512i __C, __m512i __D) +{ + return (__m512i)__builtin_ia32_vpshrdv_v16si_maskz ((__v16si)__B, + (__v16si) __C, (__v16si) __D, (__mmask16)__A); +} + +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_shrdv_epi64 (__m512i __A, __m512i __B, __m512i __C) +{ + return (__m512i) __builtin_ia32_vpshrdv_v8di ((__v8di)__A, (__v8di) __B, + (__v8di) __C); +} + +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_shrdv_epi64 (__m512i __A, __mmask8 __B, __m512i __C, __m512i __D) +{ + return (__m512i)__builtin_ia32_vpshrdv_v8di_mask ((__v8di)__A, (__v8di) __C, + (__v8di) __D, (__mmask8)__B); +} + +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_shrdv_epi64 (__mmask8 __A, __m512i __B, __m512i __C, __m512i __D) +{ + return (__m512i)__builtin_ia32_vpshrdv_v8di_maskz ((__v8di)__B, (__v8di) __C, + (__v8di) __D, (__mmask8)__A); +} + + #ifdef __DISABLE_AVX512VBMI2BW__ #undef __DISABLE_AVX512VBMI2BW__ diff --git a/gcc/config/i386/avx512vbmi2vlintrin.h b/gcc/config/i386/avx512vbmi2vlintrin.h index 5d8d88c7009..cf3d4e6be48 100644 --- a/gcc/config/i386/avx512vbmi2vlintrin.h +++ b/gcc/config/i386/avx512vbmi2vlintrin.h @@ -618,6 +618,152 @@ _mm_shldi_epi64 (__m128i __A, __m128i __B, int __C) (__v2di)(__m128i)_mm_setzero_si128 (), (__mmask8)(A)) #endif +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_shrdv_epi16 (__m256i __A, __m256i __B, __m256i __C) +{ + return (__m256i) __builtin_ia32_vpshrdv_v16hi ((__v16hi)__A, (__v16hi) __B, + (__v16hi) __C); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_shrdv_epi16 (__m256i __A, __mmask16 __B, __m256i __C, __m256i __D) +{ + return (__m256i)__builtin_ia32_vpshrdv_v16hi_mask ((__v16hi)__A, + (__v16hi) __C, (__v16hi) __D, (__mmask16)__B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_shrdv_epi16 (__mmask16 __A, __m256i __B, __m256i __C, __m256i __D) +{ + return (__m256i)__builtin_ia32_vpshrdv_v16hi_maskz ((__v16hi)__B, + (__v16hi) __C, (__v16hi) __D, (__mmask16)__A); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_shrdv_epi32 (__m256i __A, __m256i __B, __m256i __C) +{ + return (__m256i) __builtin_ia32_vpshrdv_v8si ((__v8si)__A, (__v8si) __B, + (__v8si) __C); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_shrdv_epi32 (__m256i __A, __mmask8 __B, __m256i __C, __m256i __D) +{ + return (__m256i)__builtin_ia32_vpshrdv_v8si_mask ((__v8si)__A, (__v8si) __C, + (__v8si) __D, (__mmask8)__B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_shrdv_epi32 (__mmask8 __A, __m256i __B, __m256i __C, __m256i __D) +{ + return (__m256i)__builtin_ia32_vpshrdv_v8si_maskz ((__v8si)__B, (__v8si) __C, + (__v8si) __D, (__mmask8)__A); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_shrdv_epi64 (__m256i __A, __m256i __B, __m256i __C) +{ + return (__m256i) __builtin_ia32_vpshrdv_v4di ((__v4di)__A, (__v4di) __B, + (__v4di) __C); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_shrdv_epi64 (__m256i __A, __mmask8 __B, __m256i __C, __m256i __D) +{ + return (__m256i)__builtin_ia32_vpshrdv_v4di_mask ((__v4di)__A, (__v4di) __C, + (__v4di) __D, (__mmask8)__B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_shrdv_epi64 (__mmask8 __A, __m256i __B, __m256i __C, __m256i __D) +{ + return (__m256i)__builtin_ia32_vpshrdv_v4di_maskz ((__v4di)__B, (__v4di) __C, + (__v4di) __D, (__mmask8)__A); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_shrdv_epi16 (__m128i __A, __m128i __B, __m128i __C) +{ + return (__m128i) __builtin_ia32_vpshrdv_v8hi ((__v8hi)__A, (__v8hi) __B, + (__v8hi) __C); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_shrdv_epi16 (__m128i __A, __mmask8 __B, __m128i __C, __m128i __D) +{ + return (__m128i)__builtin_ia32_vpshrdv_v8hi_mask ((__v8hi)__A, (__v8hi) __C, + (__v8hi) __D, (__mmask8)__B); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_shrdv_epi16 (__mmask8 __A, __m128i __B, __m128i __C, __m128i __D) +{ + return (__m128i)__builtin_ia32_vpshrdv_v8hi_maskz ((__v8hi)__B, (__v8hi) __C, + (__v8hi) __D, (__mmask8)__A); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_shrdv_epi32 (__m128i __A, __m128i __B, __m128i __C) +{ + return (__m128i) __builtin_ia32_vpshrdv_v4si ((__v4si)__A, (__v4si) __B, + (__v4si) __C); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_shrdv_epi32 (__m128i __A, __mmask8 __B, __m128i __C, __m128i __D) +{ + return (__m128i)__builtin_ia32_vpshrdv_v4si_mask ((__v4si)__A, (__v4si) __C, + (__v4si) __D, (__mmask8)__B); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_shrdv_epi32 (__mmask8 __A, __m128i __B, __m128i __C, __m128i __D) +{ + return (__m128i)__builtin_ia32_vpshrdv_v4si_maskz ((__v4si)__B, (__v4si) __C, + (__v4si) __D, (__mmask8)__A); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_shrdv_epi64 (__m128i __A, __m128i __B, __m128i __C) +{ + return (__m128i) __builtin_ia32_vpshrdv_v2di ((__v2di)__A, (__v2di) __B, + (__v2di) __C); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_shrdv_epi64 (__m128i __A, __mmask8 __B, __m128i __C, __m128i __D) +{ + return (__m128i)__builtin_ia32_vpshrdv_v2di_mask ((__v2di)__A, (__v2di) __C, + (__v2di) __D, (__mmask8)__B); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_shrdv_epi64 (__mmask8 __A, __m128i __B, __m128i __C, __m128i __D) +{ + return (__m128i)__builtin_ia32_vpshrdv_v2di_maskz ((__v2di)__B, (__v2di) __C, + (__v2di) __D, (__mmask8)__A); +} + + + #ifdef __DISABLE_AVX512VBMI2VL__ #undef __DISABLE_AVX512VBMI2VL__ #pragma GCC pop_options diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index c7e4f642fe9..1423f3ee8b7 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -1244,3 +1244,15 @@ DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, INT, V4DI, INT) DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, INT, V8HI, INT) DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, INT, V4SI, INT) DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, INT, V2DI, INT) +DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, V32HI) +DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, V32HI, INT) +DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, V16HI, INT) +DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, V8HI, INT) +DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI, INT) +DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT) +DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, V8DI) +DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, V8DI, INT) +DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V4DI, INT) +DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI) +DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI, INT) +DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, V2DI, INT) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 8a4466ea02d..045ee391a6c 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2665,6 +2665,34 @@ BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v4di_mask, "__builtin_ia32_v BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v2di, "__builtin_ia32_vpshld_v2di", IX86_BUILTIN_VPSHLDV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT) BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v2di_mask, "__builtin_ia32_vpshld_v2di_mask", IX86_BUILTIN_VPSHLDV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v32hi, "__builtin_ia32_vpshrdv_v32hi", IX86_BUILTIN_VPSHRDVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v32hi_mask, "__builtin_ia32_vpshrdv_v32hi_mask", IX86_BUILTIN_VPSHRDVV32HI_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v32hi_maskz, "__builtin_ia32_vpshrdv_v32hi_maskz", IX86_BUILTIN_VPSHRDVV32HI_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v16hi, "__builtin_ia32_vpshrdv_v16hi", IX86_BUILTIN_VPSHRDVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v16hi_mask, "__builtin_ia32_vpshrdv_v16hi_mask", IX86_BUILTIN_VPSHRDVV16HI_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v16hi_maskz, "__builtin_ia32_vpshrdv_v16hi_maskz", IX86_BUILTIN_VPSHRDVV16HI_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8hi, "__builtin_ia32_vpshrdv_v8hi", IX86_BUILTIN_VPSHRDVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8hi_mask, "__builtin_ia32_vpshrdv_v8hi_mask", IX86_BUILTIN_VPSHRDVV8HI_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8hi_maskz, "__builtin_ia32_vpshrdv_v8hi_maskz", IX86_BUILTIN_VPSHRDVV8HI_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v16si, "__builtin_ia32_vpshrdv_v16si", IX86_BUILTIN_VPSHRDVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v16si_mask, "__builtin_ia32_vpshrdv_v16si_mask", IX86_BUILTIN_VPSHRDVV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v16si_maskz, "__builtin_ia32_vpshrdv_v16si_maskz", IX86_BUILTIN_VPSHRDVV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8si, "__builtin_ia32_vpshrdv_v8si", IX86_BUILTIN_VPSHRDVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8si_mask, "__builtin_ia32_vpshrdv_v8si_mask", IX86_BUILTIN_VPSHRDVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8si_maskz, "__builtin_ia32_vpshrdv_v8si_maskz", IX86_BUILTIN_VPSHRDVV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v4si, "__builtin_ia32_vpshrdv_v4si", IX86_BUILTIN_VPSHRDVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v4si_mask, "__builtin_ia32_vpshrdv_v4si_mask", IX86_BUILTIN_VPSHRDVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v4si_maskz, "__builtin_ia32_vpshrdv_v4si_maskz", IX86_BUILTIN_VPSHRDVV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8di, "__builtin_ia32_vpshrdv_v8di", IX86_BUILTIN_VPSHRDVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8di_mask, "__builtin_ia32_vpshrdv_v8di_mask", IX86_BUILTIN_VPSHRDVV8DI_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v8di_maskz, "__builtin_ia32_vpshrdv_v8di_maskz", IX86_BUILTIN_VPSHRDVV8DI_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v4di, "__builtin_ia32_vpshrdv_v4di", IX86_BUILTIN_VPSHRDVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v4di_mask, "__builtin_ia32_vpshrdv_v4di_mask", IX86_BUILTIN_VPSHRDVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v4di_maskz, "__builtin_ia32_vpshrdv_v4di_maskz", IX86_BUILTIN_VPSHRDVV4DI_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v2di, "__builtin_ia32_vpshrdv_v2di", IX86_BUILTIN_VPSHRDVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v2di_mask, "__builtin_ia32_vpshrdv_v2di_mask", IX86_BUILTIN_VPSHRDVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT) +BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshrdv_v2di_maskz, "__builtin_ia32_vpshrdv_v2di_maskz", IX86_BUILTIN_VPSHRDVV2DI_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT) + BDESC_END (ARGS2, SPECIAL_ARGS2) BDESC_FIRST (special_args2, SPECIAL_ARGS2, OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_compressstorev64qi_mask, "__builtin_ia32_compressstoreuqi512_mask", IX86_BUILTIN_PCOMPRESSBSTORE512, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_UDI) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 379dc826b78..30c5ab36210 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -33828,6 +33828,13 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V8HI_FTYPE_V8DI_V8HI_UQI: case V8SI_FTYPE_V8DI_V8SI_UQI: case V4SI_FTYPE_V4SI_V4SI_V4SI: + case V16SI_FTYPE_V16SI_V16SI_V16SI: + case V8DI_FTYPE_V8DI_V8DI_V8DI: + case V32HI_FTYPE_V32HI_V32HI_V32HI: + case V2DI_FTYPE_V2DI_V2DI_V2DI: + case V16HI_FTYPE_V16HI_V16HI_V16HI: + case V8SI_FTYPE_V8SI_V8SI_V8SI: + case V8HI_FTYPE_V8HI_V8HI_V8HI: nargs = 3; break; case V32QI_FTYPE_V32QI_V32QI_INT: @@ -33989,6 +33996,15 @@ ix86_expand_args_builtin (const struct builtin_description *d, case USI_FTYPE_V32HI_V32HI_INT_USI: case UHI_FTYPE_V16HI_V16HI_INT_UHI: case UQI_FTYPE_V8HI_V8HI_INT_UQI: + case V32HI_FTYPE_V32HI_V32HI_V32HI_INT: + case V16HI_FTYPE_V16HI_V16HI_V16HI_INT: + case V8HI_FTYPE_V8HI_V8HI_V8HI_INT: + case V8SI_FTYPE_V8SI_V8SI_V8SI_INT: + case V4DI_FTYPE_V4DI_V4DI_V4DI_INT: + case V8DI_FTYPE_V8DI_V8DI_V8DI_INT: + case V16SI_FTYPE_V16SI_V16SI_V16SI_INT: + case V2DI_FTYPE_V2DI_V2DI_V2DI_INT: + case V4SI_FTYPE_V4SI_V4SI_V4SI_INT: nargs = 4; mask_pos = 1; nargs_constant = 1; diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 73560d897d7..5a924440007 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -164,6 +164,7 @@ ;; For AVX512VBMI2 support UNSPEC_VPSHLD UNSPEC_VPSHRD + UNSPEC_VPSHRDV ]) (define_c_enum "unspecv" [ @@ -20114,3 +20115,59 @@ "TARGET_AVX512VBMI2" "vpshld\t{%3, %2, %1, %0|%0, %1, %2, %3 }" [(set_attr ("prefix") ("evex"))]) + +(define_insn "vpshrdv_" + [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") + (unspec:VI248_VLBW + [(match_operand:VI248_VLBW 1 "register_operand" "0") + (match_operand:VI248_VLBW 2 "register_operand" "v") + (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm") +] UNSPEC_VPSHRDV))] + "TARGET_AVX512VBMI2" + "vpshrdv\t{%3, %2, %0|%0, %2, %3 }" + [(set_attr ("prefix") ("evex")) + (set_attr "mode" "")]) + +(define_insn "vpshrdv__mask" + [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") + (vec_merge:VI248_VLBW (unspec:VI248_VLBW + [(match_operand:VI248_VLBW 1 "register_operand" "0") + (match_operand:VI248_VLBW 2 "register_operand" "v") + (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm") + ] UNSPEC_VPSHRDV) + (match_dup 1) + (match_operand: 4 "register_operand" "Yk")) +)] + "TARGET_AVX512VBMI2" + "vpshrdv\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }" + [(set_attr ("prefix") ("evex")) + (set_attr "mode" "")]) + +(define_expand "vpshrdv__maskz" + [(match_operand:VI248_VLBW 0 "register_operand") + (match_operand:VI248_VLBW 1 "register_operand") + (match_operand:VI248_VLBW 2 "register_operand") + (match_operand:VI248_VLBW 3 "nonimmediate_operand") + (match_operand: 4 "register_operand")] + "TARGET_AVX512VBMI2" +{ + emit_insn (gen_vpshrdv__maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (mode), operands[4])); + DONE; +}) + +(define_insn "vpshrdv__maskz_1" + [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") + (vec_merge:VI248_VLBW (unspec:VI248_VLBW + [(match_operand:VI248_VLBW 1 "register_operand" "0") + (match_operand:VI248_VLBW 2 "register_operand" "v") + (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm") + ] UNSPEC_VPSHRDV) + (match_operand:VI248_VLBW 4 "const0_operand" "C") + (match_operand: 5 "register_operand" "Yk")) +)] + "TARGET_AVX512VBMI2" + "vpshrdv\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" + [(set_attr ("prefix") ("evex")) + (set_attr "mode" "")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 55b160e44ef..c5af0ddcc6f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2017-11-29 Julia Koval + + * gcc.target/i386/avx512f-vpshrdv-1.c: New test. + * gcc.target/i386/avx512f-vpshrdvd-2.c: Ditto. + * gcc.target/i386/avx512f-vpshrdvq-2.c: Ditto. + * gcc.target/i386/avx512f-vpshrdvw-2.c: Ditto. + * gcc.target/i386/avx512f-vpshrdw-2.c: Ditto. + * gcc.target/i386/avx512vl-vpshrdv-1.c: Ditto. + * gcc.target/i386/avx512vl-vpshrdvd-2.c: Ditto. + * gcc.target/i386/avx512vl-vpshrdvq-2.c: Ditto. + * gcc.target/i386/avx512vl-vpshrdvw-2.c: Ditto. + * gcc.target/i386/avx512vl-vpshrdw-2.c: Ditto. + 2017-11-29 Jakub Jelinek PR tree-optimization/83195 diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vpshrdv-1.c b/gcc/testsuite/gcc.target/i386/avx512f-vpshrdv-1.c new file mode 100644 index 00000000000..6dd3f0fa2b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vpshrdv-1.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -mavx512vbmi2 -mavx512bw -O2" } */ +/* { dg-final { scan-assembler-times "vpshrdvw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvq\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvq\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvq\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + + + +#include + +volatile __m512i x,y,z,z1; +volatile __mmask32 m32; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + x = _mm512_shrdv_epi16 (x, y, z); + x = _mm512_mask_shrdv_epi16 (x, m32, y, z); + x = _mm512_maskz_shrdv_epi16 (m32, x, y, z); + + x = _mm512_shrdv_epi32 (x, y, z); + x = _mm512_mask_shrdv_epi32 (x, m16, y, z); + x = _mm512_maskz_shrdv_epi32 (m16, x, y, z); + + x = _mm512_shrdv_epi64 (x, y, z); + x = _mm512_mask_shrdv_epi64 (x, m8, y, z); + x = _mm512_maskz_shrdv_epi64 (m8, x, y, z); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vpshrdvd-2.c b/gcc/testsuite/gcc.target/i386/avx512f-vpshrdvd-2.c new file mode 100644 index 00000000000..6e08095eade --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vpshrdvd-2.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f -mavx512bw -mavx512vbmi2" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-require-effective-target avx512vbmi2 } */ + +#define AVX512F + +#define AVX512VBMI2 +#include "avx512f-helper.h" + +#define SIZE (AVX512F_LEN / 32) + +#include "avx512f-mask-type.h" + +static void +CALC (int *r, int *dst, int *s1, int *s2) +{ + int i; + for (i = 0; i < SIZE; i++) + { + r[i] = (dst[i] >> (s2[i] & 31)) | (s1[i] << (32 - (s2[i] & 31))); + } +} + +void +TEST (void) +{ + int i; + UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1, src2; + MASK_TYPE mask = MASK_VALUE; + int res_ref[SIZE]; + + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1 + i; + src2.a[i] = 2 + 2*i; + } + + for (i = 0; i < SIZE; i++) + { + res1.a[i] = DEFAULT_VALUE; + res2.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + } + + CALC (res_ref, res1.a, src1.a, src2.a); + + res1.x = INTRINSIC (_shrdv_epi32) (res1.x, src1.x, src2.x); + res2.x = INTRINSIC (_mask_shrdv_epi32) (res2.x, mask, src1.x, src2.x); + res3.x = INTRINSIC (_maskz_shrdv_epi32) (mask, res3.x, src1.x, src2.x); + + if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref)) + abort (); + + MASK_MERGE (i_d) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref)) + abort (); + + MASK_ZERO (i_d) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vpshrdvq-2.c b/gcc/testsuite/gcc.target/i386/avx512f-vpshrdvq-2.c new file mode 100644 index 00000000000..5810fa06e4c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vpshrdvq-2.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f -mavx512bw -mavx512vbmi2" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-require-effective-target avx512vbmi2 } */ + +#define AVX512F + +#define AVX512VBMI2 +#include "avx512f-helper.h" + +#define SIZE (AVX512F_LEN / 64) + +#include "avx512f-mask-type.h" + +static void +CALC (long long *r, long long *dst, long long *s1, long long *s2) +{ + int i; + for (i = 0; i < SIZE; i++) + { + r[i] = (dst[i] >> (s2[i] & 63)) | (s1[i] << (64 - (s2[i] & 63))); + } +} + +void +TEST (void) +{ + int i; + UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1, src2; + MASK_TYPE mask = MASK_VALUE; + long long res_ref[SIZE]; + + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1 + i; + src2.a[i] = 2 + 2*i; + } + + for (i = 0; i < SIZE; i++) + { + res1.a[i] = DEFAULT_VALUE; + res2.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + } + + CALC (res_ref, res1.a, src1.a, src2.a); + + res1.x = INTRINSIC (_shrdv_epi64) (res1.x, src1.x, src2.x); + res2.x = INTRINSIC (_mask_shrdv_epi64) (res2.x, mask, src1.x, src2.x); + res3.x = INTRINSIC (_maskz_shrdv_epi64) (mask, res3.x, src1.x, src2.x); + + if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref)) + abort (); + + MASK_MERGE (i_q) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref)) + abort (); + + MASK_ZERO (i_q) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vpshrdvw-2.c b/gcc/testsuite/gcc.target/i386/avx512f-vpshrdvw-2.c new file mode 100644 index 00000000000..1699c262483 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vpshrdvw-2.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f -mavx512bw -mavx512vbmi2" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-require-effective-target avx512vbmi2 } */ + +#define AVX512F + +#define AVX512VBMI2 +#include "avx512f-helper.h" + +#define SIZE (AVX512F_LEN / 16) + +#include "avx512f-mask-type.h" + +static void +CALC (short *r, short *dst, short *s1, short *s2) +{ + int i; + for (i = 0; i < SIZE; i++) + { + r[i] = (dst[i] >> (s2[i] & 15)) | (s1[i] << (16 - (s2[i] & 15))); + } +} + +void +TEST (void) +{ + int i; + UNION_TYPE (AVX512F_LEN, i_w) res1, res2, res3, src1, src2; + MASK_TYPE mask = MASK_VALUE; + short res_ref[SIZE]; + + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1 + i; + src2.a[i] = 2 + 2*i; + } + + for (i = 0; i < SIZE; i++) + { + res1.a[i] = DEFAULT_VALUE; + res2.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + } + + CALC (res_ref, res1.a, src1.a, src2.a); + + res1.x = INTRINSIC (_shrdv_epi16) (res1.x, src1.x, src2.x); + res2.x = INTRINSIC (_mask_shrdv_epi16) (res2.x, mask, src1.x, src2.x); + res3.x = INTRINSIC (_maskz_shrdv_epi16) (mask, res3.x, src1.x, src2.x); + + if (UNION_CHECK (AVX512F_LEN, i_w) (res1, res_ref)) + abort (); + + MASK_MERGE (i_w) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_w) (res2, res_ref)) + abort (); + + MASK_ZERO (i_w) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_w) (res3, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vpshrdw-2.c b/gcc/testsuite/gcc.target/i386/avx512f-vpshrdw-2.c new file mode 100644 index 00000000000..67596eb7613 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vpshrdw-2.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f -mavx512vbmi2 -mavx512bw" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-require-effective-target avx512vbmi2 } */ + +#define AVX512F + +#define AVX512VBMI2 +#include "avx512f-helper.h" + +#define SIZE (AVX512F_LEN / 16) + +#include "avx512f-mask-type.h" + +static void +CALC (short *r, short *dst, short *s1, short *s2, int imm) +{ + int i; + for (i = 0; i < SIZE; i++) + { + r[i] = (s1[i] >> (imm & 15)) | (s2[i] << (16 - (imm & 15))); + } +} + +void +TEST (void) +{ + int i; + UNION_TYPE (AVX512F_LEN, i_w) res1, res2, res3, src1, src2; + MASK_TYPE mask = MASK_VALUE; + short res_ref[SIZE]; + + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1 + i; + src2.a[i] = 2 + 2*i; + } + + for (i = 0; i < SIZE; i++) + { + res1.a[i] = DEFAULT_VALUE; + res2.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + } + + CALC (res_ref, res1.a, src1.a, src2.a, DEFAULT_VALUE); + + res1.x = INTRINSIC (_shrdi_epi16) (src1.x, src2.x, DEFAULT_VALUE); + res2.x = INTRINSIC (_mask_shrdi_epi16) (res2.x, mask, src1.x, src2.x, DEFAULT_VALUE); + res3.x = INTRINSIC (_maskz_shrdi_epi16) (mask, src1.x, src2.x, DEFAULT_VALUE); + + if (UNION_CHECK (AVX512F_LEN, i_w) (res1, res_ref)) + abort (); + + MASK_MERGE (i_w) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_w) (res2, res_ref)) + abort (); + + MASK_ZERO (i_w) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_w) (res3, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdv-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdv-1.c new file mode 100644 index 00000000000..4e6ceb2787a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdv-1.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512vl -mavx512vbmi2 -mavx512bw -O2" } */ +/* { dg-final { scan-assembler-times "vpshrdvw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvw\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvw\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvw\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpshrdvq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m256i x,y,z; +volatile __m128i x_,y_,z_; +volatile __mmask32 m; + +void extern +avx512f_test (void) +{ + x = _mm256_shrdv_epi16 (x, y, z); + x = _mm256_mask_shrdv_epi16 (x, m, y, z); + x = _mm256_maskz_shrdv_epi16 (m, x, y, z); + + x = _mm256_shrdv_epi32 (x, y, z); + x = _mm256_mask_shrdv_epi32 (x, m, y, z); + x = _mm256_maskz_shrdv_epi32 (m, x, y, z); + + x = _mm256_shrdv_epi64 (x, y, z); + x = _mm256_mask_shrdv_epi64 (x, m, y, z); + x = _mm256_maskz_shrdv_epi64 (m, x, y, z); + + x_ = _mm_shrdv_epi16 (x_, y_, z_); + x_ = _mm_mask_shrdv_epi16 (x_, m, y_, z_); + x_ = _mm_maskz_shrdv_epi16 (m, x_, y_, z_); + + x_ = _mm_shrdv_epi32 (x_, y_, z_); + x_ = _mm_mask_shrdv_epi32 (x_, m, y_, z_); + x_ = _mm_maskz_shrdv_epi32 (m, x_, y_, z_); + + x_ = _mm_shrdv_epi64 (x_, y_, z_); + x_ = _mm_mask_shrdv_epi64 (x_, m, y_, z_); + x_ = _mm_maskz_shrdv_epi64 (m, x_, y_, z_); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdvd-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdvd-2.c new file mode 100644 index 00000000000..6d8ab79bcad --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdvd-2.c @@ -0,0 +1,16 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vl -mavx512bw -mavx512vbmi2" } */ +/* { dg-require-effective-target avx512vl } */ +/* { dg-require-effective-target avx512vbmi2 } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512f-vpshrdvd-2.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512f-vpshrdvd-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdvq-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdvq-2.c new file mode 100644 index 00000000000..da74a62c724 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdvq-2.c @@ -0,0 +1,16 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vl -mavx512bw -mavx512vbmi2" } */ +/* { dg-require-effective-target avx512vl } */ +/* { dg-require-effective-target avx512vbmi2 } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512f-vpshrdvq-2.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512f-vpshrdvq-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdvw-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdvw-2.c new file mode 100644 index 00000000000..50a3c00c640 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdvw-2.c @@ -0,0 +1,16 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vl -mavx512bw -mavx512vbmi2" } */ +/* { dg-require-effective-target avx512vl } */ +/* { dg-require-effective-target avx512vbmi2 } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512f-vpshrdvw-2.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512f-vpshrdvw-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdw-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdw-2.c new file mode 100644 index 00000000000..507034b2288 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpshrdw-2.c @@ -0,0 +1,16 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512vl -mavx512bw -mavx512vbmi2" } */ +/* { dg-require-effective-target avx512vl } */ +/* { dg-require-effective-target avx512vbmi2 } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512f-vpshrdw-2.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512f-vpshrdw-2.c" -- 2.30.2