From 8d4f847645a90a04a55de0757f5db00aa1d31902 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sun, 25 Apr 2021 11:18:29 -0300 Subject: [PATCH] Improve debug information on mtcrf test case --- src/openpower/decoder/isa/test_caller.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/openpower/decoder/isa/test_caller.py b/src/openpower/decoder/isa/test_caller.py index ce934609..710fc6c0 100644 --- a/src/openpower/decoder/isa/test_caller.py +++ b/src/openpower/decoder/isa/test_caller.py @@ -314,7 +314,7 @@ class DecoderTestCase(FHDLTestCase): print("cr", sim.cr) expected = (7-i) # check CR[0]/1/2/3 as well - print("cr%d", sim.crl[i]) + print("cr%d" % i, sim.crl[i].asint(True)) self.assertTrue(SelectableInt(expected, 4) == sim.crl[i]) # check CR itself self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 64)) -- 2.30.2