From 8d5619fb75aba6faaccc0a2433deae44f83fbd5f Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 10 Jun 2022 12:27:22 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index 8a40cceac..1acf572e3 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -65,8 +65,11 @@ hot-loops. The other reason for not adding an SVP64-Prefixed instruction without also having it as a Scalar un-prefixed instruction is that if the -32-bit encoding is ever allocated to a completely unrelated operation +32-bit encoding is ever allocated in a future revision +of the Power ISA +to a completely unrelated operation then how can a Vectorised version of that new instruction ever be added? +The uniformity and RISC Abstraction is irreparably damaged. Bottom line here is that the fundamental RISC Principle is strictly adhered to, even though these are Advanced 64-bit Vector instructions. Advocates of the RISC Principle will appreciate the uniformity of -- 2.30.2