From 8d58cbf230d1bb63d837bcbf6b0fe7029f8dd126 Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 21 Dec 2018 04:21:11 +0000 Subject: [PATCH] back.rtlil: more consistent prefixing for subfragment port wires. --- nmigen/back/rtlil.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 370b42c..c2b8809 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -645,11 +645,9 @@ def convert_fragment(builder, fragment, name, top): sub_ports = OrderedDict() for port, value in sub_port_map.items(): - if isinstance(value, ast.Signal): - sigspec = compiler_state.resolve_curr(value, prefix=sub_name) - else: - sigspec = rhs_compiler(value) - sub_ports[port] = sigspec + for signal in value._rhs_signals(): + compiler_state.resolve_curr(signal, prefix=sub_name) + sub_ports[port] = rhs_compiler(value) module.cell(sub_type, name=sub_name, ports=sub_ports, params=sub_params) -- 2.30.2