From 8d6a1857d6a607895b0086e084cbedc17637849b Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sun, 6 Jun 2021 19:00:46 -0300 Subject: [PATCH] Start a new self-contained test suite for LDSTCompUnit The idea is to use parallel processes, like on the new ALU CompUnit tests. In this case, it will include PortInterface emulation as well. The current goal is to ensure that exception support is properly implemented. --- .../experiment/test/test_compldst_multi.py | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 src/soc/experiment/test/test_compldst_multi.py diff --git a/src/soc/experiment/test/test_compldst_multi.py b/src/soc/experiment/test/test_compldst_multi.py new file mode 100644 index 00000000..f173714f --- /dev/null +++ b/src/soc/experiment/test/test_compldst_multi.py @@ -0,0 +1,33 @@ +"""Self-contained unit test for the Load/Store CompUnit +""" + +import unittest +from nmigen import Module +from nmigen.sim import Simulator +from soc.experiment.compldst_multi import LDSTCompUnit +from soc.experiment.pimem import PortInterface +from soc.fu.ldst.pipe_data import LDSTPipeSpec + + +class TestLDSTCompUnit(unittest.TestCase): + + def test_ldst_compunit(self): + m = Module() + pi = PortInterface(name="pi") + regspec = LDSTPipeSpec.regspec + dut = LDSTCompUnit(pi, regspec) + m.submodules.dut = dut + sim = Simulator(m) + sim.add_clock(1e-6) + + def process(): + yield + + sim.add_sync_process(process) + sim_writer = sim.write_vcd("test_ldst_compunit.vcd") + with sim_writer: + sim.run() + + +if __name__ == '__main__': + unittest.main() -- 2.30.2