From 8d7433188467467c2762e1bb6121d6f9d9f48372 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 11 Aug 2020 15:22:08 +0100 Subject: [PATCH] sigh, remove yet another int regfile read port --- src/soc/regfile/regfiles.py | 4 ++-- src/soc/simple/core.py | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index c3abdf00..0f29bb8f 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -70,8 +70,8 @@ class IntRegs(RegFileArray): self.w_ports = {'o': self.write_port("dest1"), #'o1': self.write_port("dest2") # for now (LD/ST update) } - self.r_ports = {'ra': self.read_port("src1"), - 'rbc': self.read_port("src3"), + self.r_ports = {'rabc': self.read_port("src1"), + #'rbc': self.read_port("src3"), 'dmi': self.read_port("dmi")} # needed for Debug (DMI) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 71a93243..42118085 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -268,8 +268,9 @@ class NonProductionCore(Elaboratable): # argh. an experiment to merge RA and RB in the INT regfile # (we have too many read/write ports) if regfile == 'INT': - fuspecs['rbc'] = [fuspecs.pop('rb')] - fuspecs['rbc'].append(fuspecs.pop('rc')) + fuspecs['rabc'] = [fuspecs.pop('rb')] + fuspecs['rabc'].append(fuspecs.pop('rc')) + fuspecs['rabc'].append(fuspecs.pop('ra')) if regfile == 'FAST': fuspecs['fast1'] = [fuspecs.pop('fast1')] fuspecs['fast1'].append(fuspecs.pop('fast2')) -- 2.30.2