From 8d81845d6808c843310472b623ec4b853f0b48e5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 2 Jun 2021 21:43:30 +0100 Subject: [PATCH] fmuls test showing rounding error against qemu --- src/openpower/decoder/isa/test_caller_fp.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py index 5e745ef4..a5e16b6b 100644 --- a/src/openpower/decoder/isa/test_caller_fp.py +++ b/src/openpower/decoder/isa/test_caller_fp.py @@ -211,6 +211,21 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64)) self.assertEqual(sim.fpr(3), SelectableInt(0xc051266640000000, 64)) + def test_fp_muls2(self): + """>>> lst = ["fmuls 3, 1, 2", + ] + """ + lst = ["fmuls 3, 1, 2", # + ] + + fprs = [0] * 32 + fprs[1] = 0xbfc4e9d700000000 + fprs[2] = 0xbdc5000000000000 + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_fprs=fprs) + self.assertEqual(sim.fpr(3), SelectableInt(0x3d9b72ea40000000, 64)) + def test_fp_mul(self): """>>> lst = ["fmul 3, 1, 2", ] -- 2.30.2