From 8d8a97461a121e02ae2f11f3e6147d68432ee02d Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Mar 2011 03:08:15 +0000 Subject: [PATCH] sim: bfin: allow byteop[123]p src regs to be the same The hardware allows the byteop[123]p insns to use the same src reg pair, so remove the combination check in the sim. Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- sim/bfin/ChangeLog | 5 +++++ sim/bfin/bfin-sim.c | 9 --------- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index 0907c145d46..95e05f8c53c 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,3 +1,8 @@ +2011-03-23 Robin Getz + + * bfin-sim.c (decode_dsp32alu_0): Drop the src0/src1 check for + BYTEOP1P, BYTEOP2P, and BYTEOP3P insns. + 2011-03-23 Mike Frysinger * machs.c (bf50x_dev, bf512_dev, bf516_dev, bf522_dev, bf526_dev, diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c index 64153884870..ad12d2d489b 100644 --- a/sim/bfin/bfin-sim.c +++ b/sim/bfin/bfin-sim.c @@ -4185,9 +4185,6 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) src0 + 1, src0, src1 + 1, src1, opts[HL + (aop << 1)], s ? ", r" : ""); - if (src0 == src1) - illegal_instruction_combination (cpu); - s0L = DREG (src0); s0H = DREG (src0 + 1); s1L = DREG (src1); @@ -4306,9 +4303,6 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) src0 + 1, src0, src1 + 1, src1, HL ? "HI" : "LO", s ? ", R" : ""); - if (src0 == src1) - illegal_instruction_combination (cpu); - s0L = DREG (src0); s0H = DREG (src0 + 1); s1L = DREG (src1); @@ -4796,9 +4790,6 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) TRACE_INSN (cpu, "R%i = BYTEOP1P (R%i:%i, R%i:%i)%s;", dst0, src0 + 1, src0, src1 + 1, src1, opts[s + (aop << 1)]); - if (src0 == src1) - illegal_instruction_combination (cpu); - s0L = DREG (src0); s0H = DREG (src0 + 1); s1L = DREG (src1); -- 2.30.2