From 8d8b7e7e92c2728e484494fbd70b5500394b3f64 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 12 Apr 2022 12:47:28 +0100 Subject: [PATCH] add comments on locations where async bridge needs to be added --- src/ls2.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/ls2.py b/src/ls2.py index af66724..df67247 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -392,11 +392,16 @@ class DDR3SoC(SoC, Elaboratable): self._decoder.add(self.dramcore.bus, addr=dramcore_addr) # map the DRAM onto Wishbone, XXX use stall but set classic below + # XXX WHEN ADDING ASYNCBRIDGE IT IS THE **BRIDGE** THAT MUST + # XXX HAVE THE STALL SIGNAL, AND THE **BRIDGE** THAT MUST HAVE + # XXX stall=stb&~ack APPLIED drambone = gramWishbone(dramcore, features={'stall'}) if fpga == 'sim': self.drambone = drambone else: self.drambone = drs(drambone) + # XXX ADD THE ASYNCBRIDGE NOT THE DRAMBONE.BUS, THEN + # XXX ADD DRAMBONE.BUS TO ASYNCBRIDGE self._decoder.add(self.drambone.bus, addr=ddr_addr) # additional SRAM at address if DRAM is not also at 0x0 @@ -519,6 +524,8 @@ class DDR3SoC(SoC, Elaboratable): m.submodules.dramcore = self.dramcore m.submodules.drambone = drambone = self.drambone # grrr, same problem with drambone: not WB4-pipe compliant + # XXX TAKE THIS OUT, REPLACE WITH ASYNCBRIDGE HAVING + # XXX asyncbridge.bus.stall.eq(asyncbridge.bus.cyc & ...) comb += drambone.bus.stall.eq(drambone.bus.cyc & ~drambone.bus.ack) # add hyperram module -- 2.30.2