From 8d992fe42e782b102eef2fd4c35a285abba32855 Mon Sep 17 00:00:00 2001 From: Cole Poirier Date: Thu, 13 Aug 2020 12:05:10 -0700 Subject: [PATCH] dcache.py add initial imports --- src/soc/experiment/dcache.py | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 0eb44c06..71329987 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1,3 +1,19 @@ +"""Dcache + +based on Anton Blanchard microwatt dcache.vhdl + +""" + +from nmigen import Module, Signal, Elaboratable, + Cat, Repl +from nmigen.cli import main +from nmigen.iocontrol import RecordObject + +from experiment.mem_types import LoadStore1ToDcacheType, + DcacheToLoadStore1Type, + MmuToDcacheType, + DacheToMmuType + # -- # -- Set associative dcache write-through # -- -- 2.30.2