From 8dd2a0d39b254ea6de03888e75b5a0422a1ecf51 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 17 Jun 2020 05:42:10 +0100 Subject: [PATCH] debugging test_issuer, getting FSM working --- src/soc/simple/core.py | 18 ++++++++++-------- src/soc/simple/test/test_core.py | 23 +++++++++++++---------- src/soc/simple/test/test_issuer.py | 4 +++- 3 files changed, 26 insertions(+), 19 deletions(-) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 0b6ea0cb..99622336 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -72,7 +72,7 @@ class NonProductionCore(Elaboratable): # issue/valid/busy signalling self.ivalid_i = self.pdecode2.e.valid # instruction is valid self.issue_i = Signal(reset_less=True) - self.busy_o = Signal(reset_less=True) + self.busy_o = Signal(name="corebusy_o", reset_less=True) # instruction input self.bigendian_i = self.pdecode2.dec.bigendian @@ -390,18 +390,20 @@ class TestIssuer(Elaboratable): # got the instruction: start issue with m.State("INSN_READ"): - sync += core_ivalid_i.eq(1) # say instruction is valid - sync += core_issue_i.eq(1) # and issued (ivalid_i redundant) - sync += core_be_i.eq(0) # little-endian mode - sync += core_opcode_i.eq(current_insn) # actual opcode + comb += core_ivalid_i.eq(1) # say instruction is valid + comb += core_issue_i.eq(1) # and issued (ivalid_i redundant) + comb += core_be_i.eq(0) # little-endian mode + comb += core_opcode_i.eq(current_insn) # actual opcode m.next = "INSN_ACTIVE" # move to "wait for completion" phase # instruction started: must wait till it finishes with m.State("INSN_ACTIVE"): - sync += core_issue_i.eq(0) # issue raises for only one cycle + comb += core_ivalid_i.eq(1) # say instruction is valid + comb += core_opcode_i.eq(current_insn) # actual opcode + #sync += core_issue_i.eq(0) # issue raises for only one cycle with m.If(~core_busy_o): # instruction done! - sync += core_ivalid_i.eq(0) # say instruction is invalid - sync += core_opcode_i.eq(0) # clear out (no good reason) + #sync += core_ivalid_i.eq(0) # say instruction is invalid + #sync += core_opcode_i.eq(0) # clear out (no good reason) # ok here we are not reading the branch unit. TODO # this just blithely overwrites whatever pipeline updated # the PC diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 3382cce4..f3f07e66 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -129,17 +129,20 @@ def check_regs(dut, sim, core, test, code): dut.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code))) -def set_issue(core, dec2, sim): - yield core.issue_i.eq(1) - yield - yield core.issue_i.eq(0) +def wait_for_busy_hi(cu): while True: - busy_o = yield core.busy_o + busy_o = yield cu.busy_o if busy_o: break print("!busy",) yield +def set_issue(core, dec2, sim): + yield core.issue_i.eq(1) + yield + yield core.issue_i.eq(0) + yield from wait_for_busy_hi(core) + def wait_for_busy_clear(cu): while True: @@ -238,12 +241,12 @@ class TestRunner(FHDLTestCase): if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() - suite.addTest(TestRunner(LDSTTestCase.test_data)) - suite.addTest(TestRunner(CRTestCase.test_data)) - suite.addTest(TestRunner(ShiftRotTestCase.test_data)) - suite.addTest(TestRunner(LogicalTestCase.test_data)) + #suite.addTest(TestRunner(LDSTTestCase.test_data)) + #suite.addTest(TestRunner(CRTestCase.test_data)) + #suite.addTest(TestRunner(ShiftRotTestCase.test_data)) + #suite.addTest(TestRunner(LogicalTestCase.test_data)) suite.addTest(TestRunner(ALUTestCase.test_data)) - suite.addTest(TestRunner(BranchTestCase.test_data)) + #suite.addTest(TestRunner(BranchTestCase.test_data)) runner = unittest.TextTestRunner() runner.run(suite) diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index 74ad0543..cd07b500 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -18,7 +18,8 @@ from soc.simple.core import TestIssuer from soc.experiment.compalu_multi import find_ok # hack from soc.simple.test.test_core import (setup_regs, check_regs, - wait_for_busy_clear) + wait_for_busy_clear, + wait_for_busy_hi) from soc.fu.compunits.test.test_compunit import (setup_test_memory, check_sim_memory) @@ -99,6 +100,7 @@ class TestRunner(FHDLTestCase): yield go_insn_i.eq(0) # and don't issue a new insn # wait until executed + yield from wait_for_busy_hi(core) yield from wait_for_busy_clear(core) print ("sim", code) -- 2.30.2