From 8df546fc0a12f28b3b771a81d92f6e54a7d6a654 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 30 May 2023 00:50:42 -0700 Subject: [PATCH] use a different default MSR value for unit tests since 0 isn't a very useful default --- src/openpower/consts.py | 8 +++++++- src/openpower/test/common.py | 4 ++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/openpower/consts.py b/src/openpower/consts.py index 5d6cad85..2197f218 100644 --- a/src/openpower/consts.py +++ b/src/openpower/consts.py @@ -132,6 +132,9 @@ class MSRb(_Const): # use this inside the HDL (where everything is little-endian) MSR = _ConstLE("MSR", names=MSRb, msb=63) +# default MSR value for unit tests, since 0 isn't a good default +DEFAULT_MSR = sum(1 << i for i in ( + MSR.SF, MSR.HV, MSR.FP, MSR.FE0, MSR.FE1, MSR.RI, MSR.LE)) # Listed in V3.0B Book III 7.5.9 "Program Interrupt" @@ -348,4 +351,7 @@ class XERRegsEnum: if __name__ == '__main__': - print ("EXTRA2 pack", EXTRA2.PACK_en, EXTRA2.PACK_en.value) + print("EXTRA2 pack", EXTRA2.PACK_en, EXTRA2.PACK_en.value) + for field in MSR: + if DEFAULT_MSR & (1 << field.value): + print(field) diff --git a/src/openpower/test/common.py b/src/openpower/test/common.py index d6ee02b9..47ffdad3 100644 --- a/src/openpower/test/common.py +++ b/src/openpower/test/common.py @@ -12,7 +12,7 @@ import os from openpower.decoder.power_enums import XER_bits, CryIn, spr_dict from openpower.util import LogKind, log, \ fast_reg_to_spr, slow_reg_to_spr # HACK! -from openpower.consts import XERRegsEnum +from openpower.consts import XERRegsEnum, DEFAULT_MSR # TODO: make this a util routine (somewhere) @@ -116,7 +116,7 @@ class TestAccumulatorBase: self.__subtest_args = old_subtest_args def add_case(self, prog, initial_regs=None, initial_sprs=None, - initial_cr=0, initial_msr=0, + initial_cr=0, initial_msr=DEFAULT_MSR, initial_mem=None, initial_svstate=0, expected=None, -- 2.30.2