From 8df8b77506af4bb609e821719b0ca42f2e72aefc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 4 Jul 2020 18:14:03 +0100 Subject: [PATCH] sort out trap test reg checking --- src/soc/fu/test/common.py | 7 +++++++ src/soc/fu/trap/test/test_pipe_caller.py | 16 +++++++++------- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py index 9cc8ec92..bd0e948e 100644 --- a/src/soc/fu/test/common.py +++ b/src/soc/fu/test/common.py @@ -296,6 +296,13 @@ class ALUHelpers: print(f"expected {expected:x}, actual: {alu_out:x}") dut.assertEqual(expected, alu_out, msg) + def check_fast_spr2(dut, res, sim_o, msg): + if 'fast2' in res: + expected = sim_o['fast2'] + alu_out = res['fast2'] + print(f"expected {expected:x}, actual: {alu_out:x}") + dut.assertEqual(expected, alu_out, msg) + def check_int_o1(dut, res, sim_o, msg): if 'o1' in res: expected = sim_o['o1'] diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index 5ab41ee9..bc7d3c38 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -26,6 +26,7 @@ def get_cu_inputs(dec2, sim): yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # SPR1 + yield from ALUHelpers.get_sim_fast_spr2(res, sim, dec2) # SPR2 ALUHelpers.get_sim_cia(res, sim, dec2) # PC ALUHelpers.get_sim_msr(res, sim, dec2) # MSR @@ -43,6 +44,8 @@ def set_alu_inputs(alu, dec2, sim): inp = yield from get_cu_inputs(dec2, sim) yield from ALUHelpers.set_int_ra(alu, dec2, inp) yield from ALUHelpers.set_int_rb(alu, dec2, inp) + yield from ALUHelpers.set_fast_spr1(alu, dec2, inp) # SPR1 + yield from ALUHelpers.set_fast_spr2(alu, dec2, inp) # SPR1 yield from ALUHelpers.set_cia(alu, dec2, inp) yield from ALUHelpers.set_msr(alu, dec2, inp) @@ -208,17 +211,16 @@ class TestRunner(FHDLTestCase): print ("output", res) yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) - yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) - yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_fast_spr2(sim_o, sim, dec2) ALUHelpers.get_sim_cia(sim_o, sim, dec2) ALUHelpers.get_sim_msr(sim_o, sim, dec2) - ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) - ALUHelpers.check_xer_ov(self, res, sim_o, code) - ALUHelpers.check_xer_ca(self, res, sim_o, code) + print ("sim output", sim_o) + ALUHelpers.check_int_o(self, res, sim_o, code) - ALUHelpers.check_xer_so(self, res, sim_o, code) + ALUHelpers.check_fast_spr1(self, res, sim_o, code) + ALUHelpers.check_fast_spr2(self, res, sim_o, code) if __name__ == "__main__": -- 2.30.2