From 8e00fd3e606769ae9367686a41f612b1d64e60e8 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Oct 2018 09:08:18 +0100
Subject: [PATCH] clarify branch predication pseudocode

---
 simple_v_extension/specification.mdwn | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 7ecf6d3ec..39debb78f 100644
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -523,13 +523,18 @@ complex), this becomes:
         preg = fp_pred_reg[rd]
         reg = fp_regfile
 
+    ps = get_pred_val(I/F==INT, rs);
+
+    preg[rd] = 0; # initialise to zero
     s1 = reg_is_vectorised(src1);
     s2 = reg_is_vectorised(src2);
     if (!s2 && !s1) goto branch;
     for (int i = 0; i < VL; ++i)
-      if (cmp(s1 ? reg[src1+i]:reg[src1],
-              s2 ? reg[src2+i]:reg[src2])
-             preg[rd] |= 1<<i;  # bitfield not vector
+      if (ps & (1<<i)) && (cmp(s1 ? reg[src1+i]:reg[src1],
+                               s2 ? reg[src2+i]:reg[src2])
+          preg[rd] |= 1<<i;  # bitfield not vector
+
+zeroing has been temporarily left out of the above pseudo-code
 
 Notes:
 
-- 
2.30.2