From 8e037eae6823caf5b9cb5b4feb3de838abb25956 Mon Sep 17 00:00:00 2001
From: Jiangshuai Li <jiangshuai_li@linux.alibaba.com>
Date: Fri, 23 Sep 2022 10:46:44 +0800
Subject: [PATCH] gdb/csky add cskyv2-linux.xml for cskyv2-linux.c

Add cskyv2-linux.xml for re-generating cskyv2-linux.c if needed.
Also update cskyv2-linux.c.
---
 gdb/arch/csky.c               |   2 +-
 gdb/features/Makefile         |   1 +
 gdb/features/cskyv2-linux.c   | 162 +++++++++++++++++-----------------
 gdb/features/cskyv2-linux.xml | 102 +++++++++++++++++++++
 4 files changed, 185 insertions(+), 82 deletions(-)
 create mode 100644 gdb/features/cskyv2-linux.xml

diff --git a/gdb/arch/csky.c b/gdb/arch/csky.c
index 887796753c6..3a97cff4919 100644
--- a/gdb/arch/csky.c
+++ b/gdb/arch/csky.c
@@ -32,7 +32,7 @@ csky_create_target_description (void)
   set_tdesc_architecture (tdesc.get (), arch_name.c_str ());
 #endif
 
-  create_feature_cskyv2_linux (tdesc.get ());
+  create_feature_cskyv2_linux (tdesc.get (), 0);
 
   return tdesc;
 }
diff --git a/gdb/features/Makefile b/gdb/features/Makefile
index 061cb2ed032..4bc85962dfe 100644
--- a/gdb/features/Makefile
+++ b/gdb/features/Makefile
@@ -213,6 +213,7 @@ FEATURE_XMLFILES = aarch64-core.xml \
 	arm/arm-vfpv2.xml \
 	arm/arm-vfpv3.xml \
 	arm/xscale-iwmmxt.xml \
+	cskyv2-linux.xml \
 	i386/32bit-core.xml \
 	i386/32bit-sse.xml \
 	i386/32bit-linux.xml \
diff --git a/gdb/features/cskyv2-linux.c b/gdb/features/cskyv2-linux.c
index e49b68c4b8d..dbf3d058bd2 100644
--- a/gdb/features/cskyv2-linux.c
+++ b/gdb/features/cskyv2-linux.c
@@ -1,67 +1,14 @@
 /* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
-   Original: cskyv2-linux.xml */
+  Original: cskyv2-linux.xml */
 
 #include "gdbsupport/tdesc.h"
 
-static void
-create_feature_cskyv2_linux (struct target_desc *result)
+static int
+create_feature_cskyv2_linux (struct target_desc *result, long regnum)
 {
   struct tdesc_feature *feature;
 
   feature = tdesc_create_feature (result, "org.gnu.gdb.csky.abiv2");
-  tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "data_ptr");
-  tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
-
-  tdesc_create_reg (feature, "lo", 36, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "hi", 37, 1, NULL, 32, "int");
-
-  tdesc_create_reg (feature, "fr0", 40, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr1", 41, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr2", 42, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr3", 43, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr4", 44, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr5", 45, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr6", 46, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr7", 47, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr8", 48, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr9", 49, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr10", 50, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr11", 51, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr12", 52, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr13", 53, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr14", 54, 1, NULL, 64, "ieee_double");
-  tdesc_create_reg (feature, "fr15", 55, 1, NULL, 64, "ieee_double");
-
   tdesc_type *element_type;
   element_type = tdesc_named_type (feature, "ieee_single");
   tdesc_create_vector (feature, "v4f", element_type, 4);
@@ -99,29 +46,82 @@ create_feature_cskyv2_linux (struct target_desc *result)
   field_type = tdesc_named_type (feature, "uint128");
   tdesc_add_field (type_with_fields, "uint128", field_type);
 
-
-  tdesc_create_reg (feature, "vr0", 56, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr1", 57, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr2", 58, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr3", 59, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr4", 60, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr5", 61, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr6", 62, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr7", 63, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr8", 64, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr9", 65, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr10", 66, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr11", 67, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr12", 68, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr13", 69, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr14", 70, 1, NULL, 128, "vec128");
-  tdesc_create_reg (feature, "vr15", 71, 1, NULL, 128, "vec128");
-
-  tdesc_create_reg (feature, "pc", 72, 1, NULL, 32, "code_ptr");
-  tdesc_create_reg (feature, "psr", 89, 1, NULL, 32, "int");
-
-  tdesc_create_reg (feature, "fid", 121, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "fcr", 122, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "fesr", 123, 1, NULL, 32, "int");
-  tdesc_create_reg (feature, "usp", 127, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r0", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r1", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r2", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r3", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r4", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r5", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r6", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r7", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r8", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r9", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r10", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r11", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r12", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r13", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r14", regnum++, 1, NULL, 32, "data_ptr");
+  tdesc_create_reg (feature, "r15", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r16", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r17", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r18", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r19", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r20", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r21", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r22", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r23", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r24", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r25", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r26", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r27", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r28", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r29", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r30", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "r31", regnum++, 1, NULL, 32, "int");
+  regnum = 36;
+  tdesc_create_reg (feature, "hi", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "lo", regnum++, 1, NULL, 32, "int");
+  regnum = 40;
+  tdesc_create_reg (feature, "fr0", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr1", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr2", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr3", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr4", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr5", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr6", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr7", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr8", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr9", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr10", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr11", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr12", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr13", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr14", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "fr15", regnum++, 1, NULL, 64, "ieee_double");
+  tdesc_create_reg (feature, "vr0", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr1", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr2", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr3", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr4", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr5", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr6", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr7", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr8", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr9", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr10", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr11", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr12", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr13", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr14", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "vr15", regnum++, 1, NULL, 128, "vec128");
+  tdesc_create_reg (feature, "pc", regnum++, 1, NULL, 32, "code_ptr");
+  regnum = 89;
+  tdesc_create_reg (feature, "psr", regnum++, 1, NULL, 32, "int");
+  regnum = 121;
+  tdesc_create_reg (feature, "fid", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "fcr", regnum++, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "fesr", regnum++, 1, NULL, 32, "int");
+  regnum = 127;
+  tdesc_create_reg (feature, "usp", regnum++, 1, NULL, 32, "int");
+  return regnum;
 }
diff --git a/gdb/features/cskyv2-linux.xml b/gdb/features/cskyv2-linux.xml
new file mode 100644
index 00000000000..d4d45c36fad
--- /dev/null
+++ b/gdb/features/cskyv2-linux.xml
@@ -0,0 +1,102 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2022 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.csky.abiv2">
+  <reg name="r0"  bitsize="32" regnum="0"/>
+  <reg name="r1"  bitsize="32"/>
+  <reg name="r2"  bitsize="32"/>
+  <reg name="r3"  bitsize="32"/>
+  <reg name="r4"  bitsize="32"/>
+  <reg name="r5"  bitsize="32"/>
+  <reg name="r6"  bitsize="32"/>
+  <reg name="r7"  bitsize="32"/>
+  <reg name="r8"  bitsize="32"/>
+  <reg name="r9"  bitsize="32"/>
+  <reg name="r10" bitsize="32"/>
+  <reg name="r11" bitsize="32"/>
+  <reg name="r12" bitsize="32"/>
+  <reg name="r13" bitsize="32"/>
+  <reg name="r14" bitsize="32" type="data_ptr"/>
+  <reg name="r15" bitsize="32"/>
+  <reg name="r16" bitsize="32"/>
+  <reg name="r17" bitsize="32"/>
+  <reg name="r18" bitsize="32"/>
+  <reg name="r19" bitsize="32"/>
+  <reg name="r20" bitsize="32"/>
+  <reg name="r21" bitsize="32"/>
+  <reg name="r22" bitsize="32"/>
+  <reg name="r23" bitsize="32"/>
+  <reg name="r24" bitsize="32"/>
+  <reg name="r25" bitsize="32"/>
+  <reg name="r26" bitsize="32"/>
+  <reg name="r27" bitsize="32"/>
+  <reg name="r28" bitsize="32"/>
+  <reg name="r29" bitsize="32"/>
+  <reg name="r30" bitsize="32"/>
+  <reg name="r31" bitsize="32"/>
+
+  <reg name="hi" bitsize="32" regnum="36"/>
+  <reg name="lo" bitsize="32"/>
+
+  <reg name="fr0"  bitsize="64" type="ieee_double" regnum="40"/>
+  <reg name="fr1"  bitsize="64" type="ieee_double"/>
+  <reg name="fr2"  bitsize="64" type="ieee_double"/>
+  <reg name="fr3"  bitsize="64" type="ieee_double"/>
+  <reg name="fr4"  bitsize="64" type="ieee_double"/>
+  <reg name="fr5"  bitsize="64" type="ieee_double"/>
+  <reg name="fr6"  bitsize="64" type="ieee_double"/>
+  <reg name="fr7"  bitsize="64" type="ieee_double"/>
+  <reg name="fr8"  bitsize="64" type="ieee_double"/>
+  <reg name="fr9"  bitsize="64" type="ieee_double"/>
+  <reg name="fr10" bitsize="64" type="ieee_double"/>
+  <reg name="fr11" bitsize="64" type="ieee_double"/>
+  <reg name="fr12" bitsize="64" type="ieee_double"/>
+  <reg name="fr13" bitsize="64" type="ieee_double"/>
+  <reg name="fr14" bitsize="64" type="ieee_double"/>
+  <reg name="fr15" bitsize="64" type="ieee_double"/>
+
+  <vector id="v4f"   type="ieee_single" count="4"/>
+  <vector id="v2d"   type="ieee_double" count="2"/>
+  <vector id="v16i8" type="int8" count="16"/>
+  <vector id="v8i16" type="int16" count="8"/>
+  <vector id="v4i32" type="int32" count="4"/>
+  <vector id="v2i64" type="int64" count="2"/>
+  <union id="vec128">
+    <field name="v4_float"  type="v4f"/>
+    <field name="v2_double" type="v2d"/>
+    <field name="v16_int8"  type="v16i8"/>
+    <field name="v8_int16"  type="v8i16"/>
+    <field name="v4_int32"  type="v4i32"/>
+    <field name="v2_int64"  type="v2i64"/>
+    <field name="uint128"   type="uint128"/>
+  </union>
+  <reg name="vr0"  bitsize="128" type="vec128" regnum="56"/>
+  <reg name="vr1"  bitsize="128" type="vec128"/>
+  <reg name="vr2"  bitsize="128" type="vec128"/>
+  <reg name="vr3"  bitsize="128" type="vec128"/>
+  <reg name="vr4"  bitsize="128" type="vec128"/>
+  <reg name="vr5"  bitsize="128" type="vec128"/>
+  <reg name="vr6"  bitsize="128" type="vec128"/>
+  <reg name="vr7"  bitsize="128" type="vec128"/>
+  <reg name="vr8"  bitsize="128" type="vec128"/>
+  <reg name="vr9"  bitsize="128" type="vec128"/>
+  <reg name="vr10" bitsize="128" type="vec128"/>
+  <reg name="vr11" bitsize="128" type="vec128"/>
+  <reg name="vr12" bitsize="128" type="vec128"/>
+  <reg name="vr13" bitsize="128" type="vec128"/>
+  <reg name="vr14" bitsize="128" type="vec128"/>
+  <reg name="vr15" bitsize="128" type="vec128"/>
+
+  <reg name="pc"   bitsize="32" type="code_ptr" regnum="72"/>
+  <reg name="psr"  bitsize="32" regnum="89"/>
+
+  <reg name="fid"  bitsize="32" regnum="121"/>
+  <reg name="fcr"  bitsize="32"/>
+  <reg name="fesr" bitsize="32"/>
+  <reg name="usp"  bitsize="32" regnum="127"/>
+</feature>
-- 
2.30.2