From 8e137f8ec29dd3a347fb837425372bfde0572177 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Tue, 24 Mar 2020 13:23:36 +0100 Subject: [PATCH] Re: [libre-riscv-dev] Advanced Topics on RISCV --- 6f/43ac86b9a244302de1e8121b687f9c06311b9b | 164 ++++++++++++++++++++++ 1 file changed, 164 insertions(+) create mode 100644 6f/43ac86b9a244302de1e8121b687f9c06311b9b diff --git a/6f/43ac86b9a244302de1e8121b687f9c06311b9b b/6f/43ac86b9a244302de1e8121b687f9c06311b9b new file mode 100644 index 0000000..0f20cb7 --- /dev/null +++ b/6f/43ac86b9a244302de1e8121b687f9c06311b9b @@ -0,0 +1,164 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Tue, 24 Mar 2020 12:23:47 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jGiaw-0002QH-KX; Tue, 24 Mar 2020 12:23:46 +0000 +Received: from isis.lip6.fr ([132.227.60.2]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) + (Exim 4.89) (envelope-from ) + id 1jGiav-0002QB-Pb + for libre-riscv-dev@lists.libre-riscv.org; Tue, 24 Mar 2020 12:23:45 +0000 +Received: from asim.lip6.fr (asim.lip6.fr [132.227.86.2]) + by isis.lip6.fr (8.15.2/8.15.2) with ESMTPS id 02OCNjsu007285 + (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO) + for ; + Tue, 24 Mar 2020 13:23:45 +0100 (CET) +Received: from localhost (melon [132.227.103.13]) + by asim.lip6.fr (8.15.2/8.14.4) with ESMTP id 02OCNib4011025 + for ; + Tue, 24 Mar 2020 13:23:44 +0100 (MET) +Message-ID: <686f9b58ae6f6a3e11caff9714db66a0406e8b0b.camel@lip6.fr> +From: Jean-Paul Chaput +To: Libre-RISCV General Development +Date: Tue, 24 Mar 2020 13:23:36 +0100 +In-Reply-To: <0F80A1BC-0241-49FE-B374-B4F1D8F3F5BD@gatech.edu> +References: <0F80A1BC-0241-49FE-B374-B4F1D8F3F5BD@gatech.edu> +Organization: UPMC +X-Mailer: Evolution 3.28.5 (3.28.5-5.el7) +Mime-Version: 1.0 +X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.4.3 + (isis.lip6.fr [132.227.60.2]); Tue, 24 Mar 2020 13:23:45 +0100 (CET) +X-Scanned-By: MIMEDefang 2.78 on 132.227.60.2 +X-Content-Filtered-By: Mailman/MimeDel 2.1.23 +Subject: Re: [libre-riscv-dev] Advanced Topics on RISCV +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: multipart/mixed; boundary="===============1176392427724861224==" +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + + +--===============1176392427724861224== +Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; + boundary="=-uMTCeTJLxmVTQeWr/JCW" + + +--=-uMTCeTJLxmVTQeWr/JCW +Content-Type: text/plain; charset="UTF-8" +Content-Transfer-Encoding: quoted-printable + + + +Hello Immanuel, + +About manycores, we did a lot of work on that topic in our lab +(Sorbonne Universit=C3=A9/LIP6). I send you a reference toward the +project we developed. This is a huge lot of work and may take +a lot of time to understand. But, we made a real chip with +16 cores to prove it works (and it do work). I cannot give you +more technical information as it not my field of expertise. + +You must distinguish two case: + +* Multi cores ( < 16) in that case, simpler solutions can be + used. + +* Many cores ( > 16) in this case, the TSAR project can be + of interest. + +TSAR (Tera-Scale ARchitecture). + +You can see details here: + https://www-soc.lip6.fr/trac/tsar + +Best regards, + + +PS: Already signaled it to Luke. + + +On Tue, 2020-03-24 at 11:51 +0000, Immanuel, Yehowshua U wrote: +> I=E2=80=99ve read through the Spike page and a good portion of the simple= +V page. +>=20 +> My two goals at the moment are: +> 1. Understand how RISCV handles multiple processes and does page walking +> 2. Understand how multicore ROSCV would work +>=20 +> I=E2=80=99m hoping to play with FreeRTOS soon so I can run through its co= +debase for setting up +> page tables. +> Also, do you know if spike tests the special instructions like exception = +instructions? +> Also, what RISCV instructions would a kernel use to set up the pagetables= +? +>=20 +> Lastly, do you know any good resources for intro to multicore systems? RI= +SCV doesn=E2=80=99t +> seem to have any multicore specific instructions. My current questions wo= +uld include +> things like: +>=20 +> 1. How can the kernel assign tasks to a certain core? If you have a proce= +ss with +> multiple threads, it would make sense to spread out the threads among ava= +ilable +> processors instead of concentrating them on a single core. How might this= + work with +> respect to RISCV? +>=20 +> 2. Does the hardware ensure cache coherency - that is - externally - soft= +ware sees one +> big cache all though I imagine each core would have a local cache that wo= +uld have to +> communicate with other caches? +>=20 +> Yehowshua +> _______________________________________________ +> libre-riscv-dev mailing list +> libre-riscv-dev@lists.libre-riscv.org +> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev +--=20 + + .-. J e a n - P a u l C h a p u t / Administrateur Systeme + /v\ Jean-Paul.Chaput@lip6.fr + /(___)\ work: (33) 01.44.27.53.99 =20 + ^^ ^^ cell: 06.66.25.35.55 home: 09.65.29.83.38 + + U P M C Universite Pierre & Marie Curie + L I P 6 Laboratoire d'Informatique de Paris VI + S o C System On Chip + +--=-uMTCeTJLxmVTQeWr/JCW-- + + + +--===============1176392427724861224== +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: base64 +Content-Disposition: inline + +X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz +Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn +Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj +di1kZXYK + +--===============1176392427724861224==-- + + + -- 2.30.2