From 8e1d528663a8691f6dd3570b83166053fd0a2c9b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 28 Feb 2020 09:48:48 +0100 Subject: [PATCH] targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets). --- litex/boards/targets/ulx3s.py | 14 +++++++++----- litex/boards/targets/versa_ecp5.py | 10 ++++------ 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 5ba068fa..ee641e66 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -12,6 +12,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import ulx3s +from litex.build.lattice.trellis import trellis_args, trellis_argdict + from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -50,7 +52,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, device="LFE5U-45F", toolchain="diamond", + def __init__(self, device="LFE5U-45F", toolchain="trellis", sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", **kwargs): platform = ulx3s.Platform(device=device, toolchain=toolchain) @@ -72,16 +74,17 @@ class BaseSoC(SoCSDRAM): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond", - help='gateware toolchain to use, diamond (default) or trellis') + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", + help="gateware toolchain to use, trellis (default) or diamond") parser.add_argument("--device", dest="device", default="LFE5U-45F", - help='FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F') + help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F") parser.add_argument("--sys-clk-freq", default=50e6, help="system clock frequency (default=50MHz)") parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") builder_args(parser) soc_sdram_args(parser) + trellis_args(parser) args = parser.parse_args() soc = BaseSoC(device=args.device, toolchain=args.toolchain, @@ -89,7 +92,8 @@ def main(): sdram_module_cls=args.sdram_module, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} + builder.build(**builder_kargs) if __name__ == "__main__": main() diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index e2647593..5fe17147 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -102,7 +102,7 @@ class EthernetSoC(BaseSoC): } mem_map.update(BaseSoC.mem_map) - def __init__(self, toolchain="diamond", **kwargs): + def __init__(self, toolchain="trellis", **kwargs): BaseSoC.__init__(self, toolchain=toolchain, **kwargs) # Ethernet --------------------------------------------------------------------------------- @@ -130,8 +130,8 @@ class EthernetSoC(BaseSoC): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond", - help='gateware toolchain to use, diamond (default) or trellis') + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", + help="gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) @@ -144,9 +144,7 @@ def main(): cls = EthernetSoC if args.with_ethernet else BaseSoC soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder_kargs = {} - if args.toolchain == "trellis": - builder_kargs == trellis_argdict(args) + builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} builder.build(**builder_kargs) if __name__ == "__main__": -- 2.30.2