From 8e3fd4d0be5cba1ebc530858786a81136e8c6271 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 27 Jun 2020 20:12:55 +0100 Subject: [PATCH] increase (double) address width in TstL0CacheBuffer --- src/soc/fu/compunits/test/test_compunit.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index 37258ea3..7b4c41cf 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -160,7 +160,8 @@ class TestRunner(FHDLTestCase): if self.funit == Function.LDST: from soc.experiment.l0_cache import TstL0CacheBuffer m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64, - addrwid=3) + addrwid=3, + ifacetype='test_bare_wb') pi = l0.l0.dports[0] m.submodules.cu = cu = self.fukls(pi, awid=3) m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel -- 2.30.2