From 8e5ad071e1838de2bd665c5a3c01c3dcf77e7e4a Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 16 Dec 2020 12:32:45 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64/discussion.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn index 13faceb48..ccb40ffb6 100644 --- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn +++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn @@ -99,7 +99,7 @@ Some examples on different operation widths: Mode types: -* **sz dz predicate zeroing** if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero. +* **sz dz predicate zeroing** if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero. otherwise the element is ignored or skipped, depending on context. * **ffirst** or data-dependent fail-on-first: see separate section. * **sat mode** or saturation: clamps the result to a min/max rather than overflows / wraps. allows signed and unsigned clamping. * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero. When Rc=1 the CR element (CR0) however is still stored in the CR regfile. This scheme does not apply to crops (crand, cror). -- 2.30.2