From 8e5f50f6daafde89b6f508c774c12619570209f5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 1 Jun 2020 13:27:00 +0100 Subject: [PATCH] allow M*-Form shiftrot to swap RS/RB back to consistent positions --- src/soc/decoder/power_decoder2.py | 19 ++++++++++++++----- src/soc/decoder/power_enums.py | 2 ++ 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index dffc9da7..81ab7143 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -85,7 +85,9 @@ class DecodeB(Elaboratable): """DecodeB from instruction decodes register RB, different forms of immediate (signed, unsigned), - and implicit SPRs + and implicit SPRs. register B is basically "lane 2" into the CompUnits. + by industry-standard convention, "lane 2" is where fully-decoded + immediates are muxed in. """ def __init__(self, dec): @@ -105,6 +107,9 @@ class DecodeB(Elaboratable): with m.Case(In2Sel.RB): comb += self.reg_out.data.eq(self.dec.RB) comb += self.reg_out.ok.eq(1) + with m.Case(In2Sel.RS): + comb += self.reg_out.data.eq(self.dec.RS) # for M-Form shiftrot + comb += self.reg_out.ok.eq(1) with m.Case(In2Sel.CONST_UI): comb += self.imm_out.data.eq(self.dec.UI) comb += self.imm_out.ok.eq(1) @@ -155,7 +160,7 @@ class DecodeB(Elaboratable): class DecodeC(Elaboratable): """DecodeC from instruction - decodes register RC + decodes register RC. this is "lane 3" into some CompUnits (not many) """ def __init__(self, dec): @@ -169,9 +174,13 @@ class DecodeC(Elaboratable): comb = m.d.comb # select Register C field - with m.If(self.sel_in == In3Sel.RS): - comb += self.reg_out.data.eq(self.dec.RS) - comb += self.reg_out.ok.eq(1) + with m.Switch(self.sel_in): + with m.Case(In3Sel.RB): + comb += self.reg_out.data.eq(self.dec.RB) # for M-Form shiftrot + comb += self.reg_out.ok.eq(1) + with m.Case(In3Sel.RS): + comb += self.reg_out.data.eq(self.dec.RS) + comb += self.reg_out.ok.eq(1) return m diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py index a9e4c745..05353d2f 100644 --- a/src/soc/decoder/power_enums.py +++ b/src/soc/decoder/power_enums.py @@ -188,12 +188,14 @@ class In2Sel(Enum): CONST_SH = 10 CONST_SH32 = 11 SPR = 12 + RS = 13 # for shiftrot (M-Form) @unique class In3Sel(Enum): NONE = 0 RS = 1 + RB = 2 # for shiftrot (M-Form) @unique -- 2.30.2