From 8e92560a9c9c57dfed3283c48ef5e46a7e0204b1 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Fri, 20 Nov 2015 15:19:09 +0000 Subject: [PATCH] [ARM] Do not expand movmisalign pattern if not in 32-bit mode * config/arm/arm.c (arm_option_override): Require TARGET_32BIT for unaligned_access. * config/arm/arm.md (unaligned_loadsi): Remove redundant TARGET_32BIT from matching condition. (unaligned_loadhis): Likewise. (unaligned_loadhiu): Likewise. (unaligned_storesi): Likewise. (unaligned_storehi): Likewise. * gcc.target/arm/armv6-unaligned-load-ice.c: New test. From-SVN: r230664 --- gcc/ChangeLog | 11 +++++++++++ gcc/config/arm/arm.c | 5 +++-- gcc/config/arm/arm.md | 10 +++++----- gcc/testsuite/ChangeLog | 4 ++++ .../gcc.target/arm/armv6-unaligned-load-ice.c | 18 ++++++++++++++++++ 5 files changed, 41 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/armv6-unaligned-load-ice.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 235a3b0cdc9..a16d09c0a4e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2015-11-20 Kyrylo Tkachov + + * config/arm/arm.c (arm_option_override): Require TARGET_32BIT + for unaligned_access. + * config/arm/arm.md (unaligned_loadsi): Remove redundant TARGET_32BIT + from matching condition. + (unaligned_loadhis): Likewise. + (unaligned_loadhiu): Likewise. + (unaligned_storesi): Likewise. + (unaligned_storehi): Likewise. + 2015-11-20 Kyrylo Tkachov PR target/68149 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 805335ce354..290b537ae16 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3282,7 +3282,8 @@ arm_option_override (void) } /* Enable -munaligned-access by default for - - all ARMv6 architecture-based processors + - all ARMv6 architecture-based processors when compiling for a 32-bit ISA + i.e. Thumb2 and ARM state only. - ARMv7-A, ARMv7-R, and ARMv7-M architecture-based processors. - ARMv8 architecture-base processors. @@ -3292,7 +3293,7 @@ arm_option_override (void) if (unaligned_access == 2) { - if (arm_arch6 && (arm_arch_notm || arm_arch7)) + if (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) unaligned_access = 1; else unaligned_access = 0; diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 227a9bd3f3d..effe7eb799d 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4219,7 +4219,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=l,r") (unspec:SI [(match_operand:SI 1 "memory_operand" "Uw,m")] UNSPEC_UNALIGNED_LOAD))] - "unaligned_access && TARGET_32BIT" + "unaligned_access" "ldr%?\t%0, %1\t@ unaligned" [(set_attr "arch" "t2,any") (set_attr "length" "2,4") @@ -4232,7 +4232,7 @@ (sign_extend:SI (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,Uh")] UNSPEC_UNALIGNED_LOAD)))] - "unaligned_access && TARGET_32BIT" + "unaligned_access" "ldrsh%?\t%0, %1\t@ unaligned" [(set_attr "arch" "t2,any") (set_attr "length" "2,4") @@ -4245,7 +4245,7 @@ (zero_extend:SI (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,m")] UNSPEC_UNALIGNED_LOAD)))] - "unaligned_access && TARGET_32BIT" + "unaligned_access" "ldrh%?\t%0, %1\t@ unaligned" [(set_attr "arch" "t2,any") (set_attr "length" "2,4") @@ -4257,7 +4257,7 @@ [(set (match_operand:SI 0 "memory_operand" "=Uw,m") (unspec:SI [(match_operand:SI 1 "s_register_operand" "l,r")] UNSPEC_UNALIGNED_STORE))] - "unaligned_access && TARGET_32BIT" + "unaligned_access" "str%?\t%1, %0\t@ unaligned" [(set_attr "arch" "t2,any") (set_attr "length" "2,4") @@ -4269,7 +4269,7 @@ [(set (match_operand:HI 0 "memory_operand" "=Uw,m") (unspec:HI [(match_operand:HI 1 "s_register_operand" "l,r")] UNSPEC_UNALIGNED_STORE))] - "unaligned_access && TARGET_32BIT" + "unaligned_access" "strh%?\t%1, %0\t@ unaligned" [(set_attr "arch" "t2,any") (set_attr "length" "2,4") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b6810c8fd78..d55f6dd231b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2015-11-20 Kyrylo Tkachov + + * gcc.target/arm/armv6-unaligned-load-ice.c: New test. + 2015-11-20 Paul Thomas PR fortran/68237 diff --git a/gcc/testsuite/gcc.target/arm/armv6-unaligned-load-ice.c b/gcc/testsuite/gcc.target/arm/armv6-unaligned-load-ice.c new file mode 100644 index 00000000000..88528f11e12 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv6-unaligned-load-ice.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6k" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */ +/* { dg-options "-mthumb -Os -mfloat-abi=softfp" } */ +/* { dg-add-options arm_arch_v6k } */ + +long +get_number (char *s, long size, int unsigned_p) +{ + long x; + unsigned char *p = (unsigned char *) s; + switch (size) + { + case 4: + x = ((long) p[3] << 24) | ((long) p[2] << 16) | (p[1] << 8) | p[0]; + return x; + } +} -- 2.30.2