From 8ebbd20d2f9ea8830fd80ba7d00cc23e3a256047 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Mar 2021 21:09:25 +0000
Subject: [PATCH] litex expects wishbone "err" signals, added to sram 4k

---
 .../non_generated/full_core_4_4ksram_ls180.il | 10618 ++++++++--------
 1 file changed, 5313 insertions(+), 5305 deletions(-)

diff --git a/experiments9/non_generated/full_core_4_4ksram_ls180.il b/experiments9/non_generated/full_core_4_4ksram_ls180.il
index 5f87ea6..83848eb 100644
--- a/experiments9/non_generated/full_core_4_4ksram_ls180.il
+++ b/experiments9/non_generated/full_core_4_4ksram_ls180.il
@@ -30738,9 +30738,9 @@ module \adr_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:21041.7-21041.15"
   wire \initial
@@ -30942,9 +30942,9 @@ module \adrok_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 6 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:21103.7-21103.15"
   wire \initial
@@ -32036,9 +32036,9 @@ module \alu0
   wire \alui_l_r_alui$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
   wire \alui_l_s_alui
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 41 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire output 33 \cr_a_ok
@@ -35145,9 +35145,9 @@ module \alu_alu0
   wire input 18 \alu_op__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire \alu_op__zero_a$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 38 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 4 output 28 \cr_a
@@ -36176,9 +36176,9 @@ module \alu_branch0
   wire input 13 \br_op__lk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire \br_op__lk$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 23 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 20 \cr_a
@@ -36518,9 +36518,9 @@ attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0"
 attribute \generator "nMigen"
 module \alu_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 21 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 4 output 12 \cr_a
@@ -37036,9 +37036,9 @@ attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0"
 attribute \generator "nMigen"
 module \alu_div0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 35 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 4 output 27 \cr_a
@@ -38542,9 +38542,9 @@ module \alu_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:26073.7-26073.15"
   wire \initial
@@ -38746,9 +38746,9 @@ module \alu_l$107
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:26135.7-26135.15"
   wire \initial
@@ -38950,9 +38950,9 @@ module \alu_l$125
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:26197.7-26197.15"
   wire \initial
@@ -39154,9 +39154,9 @@ module \alu_l$128
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:26259.7-26259.15"
   wire \initial
@@ -39358,9 +39358,9 @@ module \alu_l$16
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:26321.7-26321.15"
   wire \initial
@@ -39562,9 +39562,9 @@ module \alu_l$29
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:26383.7-26383.15"
   wire \initial
@@ -39766,9 +39766,9 @@ module \alu_l$45
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:26445.7-26445.15"
   wire \initial
@@ -39970,9 +39970,9 @@ module \alu_l$61
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:26507.7-26507.15"
   wire \initial
@@ -40174,9 +40174,9 @@ module \alu_l$73
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:26569.7-26569.15"
   wire \initial
@@ -40378,9 +40378,9 @@ module \alu_l$90
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:26631.7-26631.15"
   wire \initial
@@ -40540,9 +40540,9 @@ attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0"
 attribute \generator "nMigen"
 module \alu_logical0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 31 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 4 output 25 \cr_a
@@ -41554,9 +41554,9 @@ attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0"
 attribute \generator "nMigen"
 module \alu_mul0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 29 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 4 output 21 \cr_a
@@ -42770,9 +42770,9 @@ attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0"
 attribute \generator "nMigen"
 module \alu_shift_rot0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 34 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 4 output 25 \cr_a
@@ -43804,9 +43804,9 @@ attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0"
 attribute \generator "nMigen"
 module \alu_spr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 28 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 64 output 16 \fast1
@@ -44365,9 +44365,9 @@ attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0"
 attribute \generator "nMigen"
 module \alu_trap0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 29 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 64 output 19 \fast1
@@ -45281,9 +45281,9 @@ module \alui_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:31347.7-31347.15"
   wire \initial
@@ -45485,9 +45485,9 @@ module \alui_l$106
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:31409.7-31409.15"
   wire \initial
@@ -45689,9 +45689,9 @@ module \alui_l$124
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:31471.7-31471.15"
   wire \initial
@@ -45893,9 +45893,9 @@ module \alui_l$15
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:31533.7-31533.15"
   wire \initial
@@ -46097,9 +46097,9 @@ module \alui_l$28
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:31595.7-31595.15"
   wire \initial
@@ -46301,9 +46301,9 @@ module \alui_l$44
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:31657.7-31657.15"
   wire \initial
@@ -46505,9 +46505,9 @@ module \alui_l$60
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:31719.7-31719.15"
   wire \initial
@@ -46709,9 +46709,9 @@ module \alui_l$72
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:31781.7-31781.15"
   wire \initial
@@ -46913,9 +46913,9 @@ module \alui_l$89
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:31843.7-31843.15"
   wire \initial
@@ -50356,9 +50356,9 @@ module \branch0
   wire \alui_l_r_alui$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
   wire \alui_l_s_alui
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 26 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
   wire output 11 \cu_busy_o
@@ -52593,9 +52593,9 @@ module \busy_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:34308.7-34308.15"
   wire \initial
@@ -62182,9 +62182,9 @@ module \core
   wire width 3 input 27 \core_xer_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:95"
   wire output 2 \corebusy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 96 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182"
   wire width 2 \counter
@@ -85619,9 +85619,9 @@ module \cr
   wire width 4 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
   wire width 4 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 16 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 4 input 14 \data_i
@@ -87266,9 +87266,9 @@ module \cr0
   wire \alui_l_r_alui$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
   wire \alui_l_s_alui
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 24 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire output 22 \cr_a_ok
@@ -90629,9 +90629,9 @@ module \cyc_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:51203.7-51203.15"
   wire \initial
@@ -91186,7 +91186,7 @@ module \dbg
   wire \$97
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227"
   wire \$99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 24 \clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17"
   wire width 64 input 11 \core_dbg_msr
@@ -91274,7 +91274,7 @@ module \dbg
   wire width 64 \log_dmi_data
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:119"
   wire width 32 \log_write_addr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 1 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:134"
   wire width 64 \stat_reg
@@ -205242,9 +205242,9 @@ module \div0
   wire \alui_l_r_alui$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
   wire \alui_l_s_alui
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 38 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire output 32 \cr_a_ok
@@ -208442,9 +208442,9 @@ module \fast
   wire width 3 \_1_
   attribute \src "libresoc.v:131323.13-131323.16"
   wire width 3 \_2_
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 17 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 3 input 15 \dest1__addr
@@ -208924,9 +208924,9 @@ attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.fus"
 attribute \generator "nMigen"
 module \fus
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 330 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire output 257 \cr_a_ok
@@ -210921,9 +210921,9 @@ module \idx_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:133339.7-133339.15"
   wire \initial
@@ -211305,7 +211305,7 @@ module \imem
   wire \a_stall_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
   wire input 3 \a_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 15 \clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
   wire width 45 \f_badaddr_o
@@ -211351,7 +211351,7 @@ module \imem
   wire width 64 \ibus_rdata$next
   attribute \src "libresoc.v:133401.7-133401.15"
   wire \initial
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 1 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93"
   wire input 7 \wb_icache_en
@@ -214796,9 +214796,9 @@ module \int
   wire width 5 \_2_
   attribute \src "libresoc.v:135916.13-135916.16"
   wire width 5 \_3_
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 17 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 5 input 15 \dest1__addr
@@ -217029,7 +217029,7 @@ module \jtag
   wire width 4 \_irblock_ir
   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128"
   wire \_irblock_tdo
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 331 \clk
   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
   wire input 6 \dmi0__ack_o
@@ -217479,7 +217479,7 @@ module \jtag
   wire input 75 \pwm_1__core__o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire output 230 \pwm_1__pad__o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 1 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire input 79 \sd0_clk__core__o
@@ -222747,9 +222747,9 @@ attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.l0"
 attribute \generator "nMigen"
 module \l0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 31 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
   wire input 23 \dbus__ack
@@ -223095,9 +223095,9 @@ module \l0$130
   wire width 96 \$31
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136"
   wire width 96 \$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 33 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46"
   wire \idx_l$23
@@ -223894,9 +223894,9 @@ module \ld_active
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:139348.7-139348.15"
   wire \initial
@@ -224812,9 +224812,9 @@ module \ldst0
   wire \alu_ok$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270"
   wire \alu_valid
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 53 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
   wire input 3 \cu_ad__go_i
@@ -229860,9 +229860,9 @@ module \lod_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:141397.7-141397.15"
   wire \initial
@@ -230820,9 +230820,9 @@ module \logical0
   wire \alui_l_r_alui$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
   wire \alui_l_s_alui
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 34 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire output 32 \cr_a_ok
@@ -233387,9 +233387,9 @@ module \logical_pipe1
   wire $and$libresoc.v:143649$6840_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
   wire \$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 53 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 4 output 25 \cr_a
@@ -235566,9 +235566,9 @@ module \logical_pipe2
   wire $and$libresoc.v:144752$6962_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
   wire \$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 54 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 4 input 25 \cr_a
@@ -248610,24 +248610,24 @@ module \ls180
   wire \builder_sync_rhs_array_muxed6
   attribute \src "ls180.v:2011.6-2011.18"
   wire \builder_wait
-  attribute \src "ls180.v:30.19-30.23"
-  wire width 3 input 26 \eint
-  attribute \src "ls180.v:194.12-194.18"
+  attribute \src "ls180.v:5.19-5.23"
+  wire width 3 input 1 \eint
+  attribute \src "ls180.v:171.12-171.18"
   wire width 3 \eint_1
-  attribute \src "ls180.v:5.20-5.26"
-  wire width 16 input 1 \gpio_i
-  attribute \src "ls180.v:6.20-6.26"
-  wire width 16 output 2 \gpio_o
-  attribute \src "ls180.v:7.20-7.27"
-  wire width 16 output 3 \gpio_oe
-  attribute \src "ls180.v:8.14-8.21"
-  wire output 4 \i2c_scl
-  attribute \src "ls180.v:9.13-9.22"
-  wire input 5 \i2c_sda_i
-  attribute \src "ls180.v:10.14-10.23"
-  wire output 6 \i2c_sda_o
-  attribute \src "ls180.v:11.14-11.24"
-  wire output 7 \i2c_sda_oe
+  attribute \src "ls180.v:32.20-32.26"
+  wire width 16 input 28 \gpio_i
+  attribute \src "ls180.v:33.20-33.26"
+  wire width 16 output 29 \gpio_o
+  attribute \src "ls180.v:34.20-34.27"
+  wire width 16 output 30 \gpio_oe
+  attribute \src "ls180.v:35.14-35.21"
+  wire output 31 \i2c_scl
+  attribute \src "ls180.v:36.13-36.22"
+  wire input 32 \i2c_sda_i
+  attribute \src "ls180.v:37.14-37.23"
+  wire output 33 \i2c_sda_o
+  attribute \src "ls180.v:38.14-38.24"
+  wire output 34 \i2c_sda_oe
   attribute \src "ls180.v:49.13-49.21"
   wire input 45 \jtag_tck
   attribute \src "ls180.v:50.13-50.21"
@@ -248986,65 +248986,65 @@ module \ls180
   wire width 64 \main_libresocsim_libresoc2
   attribute \src "ls180.v:169.12-169.45"
   wire width 2 \main_libresocsim_libresoc_clk_sel
-  attribute \src "ls180.v:171.13-171.67"
+  attribute \src "ls180.v:193.13-193.67"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i
-  attribute \src "ls180.v:172.13-172.67"
+  attribute \src "ls180.v:194.13-194.67"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o
-  attribute \src "ls180.v:173.13-173.68"
+  attribute \src "ls180.v:195.13-195.68"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe
-  attribute \src "ls180.v:174.6-174.61"
+  attribute \src "ls180.v:196.6-196.61"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl
-  attribute \src "ls180.v:175.6-175.63"
+  attribute \src "ls180.v:197.6-197.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
-  attribute \src "ls180.v:176.6-176.63"
+  attribute \src "ls180.v:198.6-198.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
-  attribute \src "ls180.v:177.6-177.64"
+  attribute \src "ls180.v:199.6-199.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
-  attribute \src "ls180.v:195.6-195.64"
+  attribute \src "ls180.v:172.6-172.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
-  attribute \src "ls180.v:196.6-196.66"
+  attribute \src "ls180.v:173.6-173.66"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
-  attribute \src "ls180.v:197.6-197.66"
+  attribute \src "ls180.v:174.6-174.66"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
-  attribute \src "ls180.v:198.6-198.67"
+  attribute \src "ls180.v:175.6-175.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
-  attribute \src "ls180.v:182.13-182.68"
+  attribute \src "ls180.v:181.13-181.68"
   wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a
-  attribute \src "ls180.v:191.12-191.68"
+  attribute \src "ls180.v:190.12-190.68"
   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba
-  attribute \src "ls180.v:188.6-188.65"
+  attribute \src "ls180.v:187.6-187.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
-  attribute \src "ls180.v:190.6-190.63"
+  attribute \src "ls180.v:189.6-189.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke
-  attribute \src "ls180.v:189.6-189.64"
+  attribute \src "ls180.v:188.6-188.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
-  attribute \src "ls180.v:192.12-192.68"
+  attribute \src "ls180.v:191.12-191.68"
   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm
-  attribute \src "ls180.v:183.13-183.71"
+  attribute \src "ls180.v:182.13-182.71"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i
-  attribute \src "ls180.v:184.13-184.71"
+  attribute \src "ls180.v:183.13-183.71"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o
-  attribute \src "ls180.v:185.6-185.65"
+  attribute \src "ls180.v:184.6-184.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
-  attribute \src "ls180.v:187.6-187.65"
+  attribute \src "ls180.v:186.6-186.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
-  attribute \src "ls180.v:186.6-186.64"
+  attribute \src "ls180.v:185.6-185.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
-  attribute \src "ls180.v:199.6-199.67"
+  attribute \src "ls180.v:200.6-200.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk
-  attribute \src "ls180.v:201.6-201.68"
-  wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
   attribute \src "ls180.v:202.6-202.68"
+  wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
+  attribute \src "ls180.v:203.6-203.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso
-  attribute \src "ls180.v:200.6-200.68"
+  attribute \src "ls180.v:201.6-201.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
-  attribute \src "ls180.v:178.6-178.67"
+  attribute \src "ls180.v:177.6-177.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk
-  attribute \src "ls180.v:180.6-180.68"
+  attribute \src "ls180.v:179.6-179.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n
-  attribute \src "ls180.v:181.6-181.68"
+  attribute \src "ls180.v:180.6-180.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso
-  attribute \src "ls180.v:179.6-179.68"
+  attribute \src "ls180.v:178.6-178.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi
   attribute \src "ls180.v:72.6-72.40"
   wire \main_libresocsim_libresoc_dbus_ack
@@ -252374,24 +252374,24 @@ module \ls180
   wire width 24 input 48 \nc
   attribute \src "ls180.v:338.6-338.13"
   wire \por_clk
-  attribute \src "ls180.v:42.19-42.22"
-  wire width 2 output 38 \pwm
-  attribute \src "ls180.v:203.12-203.17"
+  attribute \src "ls180.v:13.19-13.22"
+  wire width 2 output 9 \pwm
+  attribute \src "ls180.v:176.12-176.17"
   wire width 2 \pwm_1
-  attribute \src "ls180.v:31.13-31.23"
-  wire output 27 \sdcard_clk
-  attribute \src "ls180.v:32.13-32.25"
-  wire input 28 \sdcard_cmd_i
-  attribute \src "ls180.v:33.13-33.25"
-  wire output 29 \sdcard_cmd_o
-  attribute \src "ls180.v:34.13-34.26"
-  wire output 30 \sdcard_cmd_oe
-  attribute \src "ls180.v:35.19-35.32"
-  wire width 4 input 31 \sdcard_data_i
-  attribute \src "ls180.v:36.19-36.32"
-  wire width 4 output 32 \sdcard_data_o
-  attribute \src "ls180.v:37.13-37.27"
-  wire output 33 \sdcard_data_oe
+  attribute \src "ls180.v:6.13-6.23"
+  wire output 2 \sdcard_clk
+  attribute \src "ls180.v:7.13-7.25"
+  wire input 3 \sdcard_cmd_i
+  attribute \src "ls180.v:8.13-8.25"
+  wire output 4 \sdcard_cmd_o
+  attribute \src "ls180.v:9.13-9.26"
+  wire output 5 \sdcard_cmd_oe
+  attribute \src "ls180.v:10.19-10.32"
+  wire width 4 input 6 \sdcard_data_i
+  attribute \src "ls180.v:11.19-11.32"
+  wire width 4 output 7 \sdcard_data_o
+  attribute \src "ls180.v:12.13-12.27"
+  wire output 8 \sdcard_data_oe
   attribute \src "ls180.v:18.20-18.27"
   wire width 13 output 14 \sdram_a
   attribute \src "ls180.v:27.19-27.27"
@@ -252402,7 +252402,7 @@ module \ls180
   wire output 22 \sdram_cke
   attribute \src "ls180.v:29.13-29.24"
   wire output 25 \sdram_clock
-  attribute \src "ls180.v:193.6-193.19"
+  attribute \src "ls180.v:192.6-192.19"
   wire \sdram_clock_1
   attribute \src "ls180.v:25.13-25.23"
   wire output 21 \sdram_cs_n
@@ -252556,14 +252556,14 @@ module \ls180
   wire \sdrio_clk_8
   attribute \src "ls180.v:2769.6-2769.17"
   wire \sdrio_clk_9
-  attribute \src "ls180.v:38.13-38.26"
-  wire output 34 \spimaster_clk
-  attribute \src "ls180.v:40.13-40.27"
-  wire output 36 \spimaster_cs_n
+  attribute \src "ls180.v:39.13-39.26"
+  wire output 35 \spimaster_clk
   attribute \src "ls180.v:41.13-41.27"
-  wire input 37 \spimaster_miso
-  attribute \src "ls180.v:39.13-39.27"
-  wire output 35 \spimaster_mosi
+  wire output 37 \spimaster_cs_n
+  attribute \src "ls180.v:42.13-42.27"
+  wire input 38 \spimaster_miso
+  attribute \src "ls180.v:40.13-40.27"
+  wire output 36 \spimaster_mosi
   attribute \src "ls180.v:14.13-14.26"
   wire output 10 \spisdcard_clk
   attribute \src "ls180.v:16.13-16.27"
@@ -252586,10 +252586,10 @@ module \ls180
   wire input 40 \sys_rst
   attribute \src "ls180.v:337.6-337.15"
   wire \sys_rst_1
-  attribute \src "ls180.v:13.13-13.20"
-  wire input 9 \uart_rx
-  attribute \src "ls180.v:12.13-12.20"
-  wire output 8 \uart_tx
+  attribute \src "ls180.v:31.13-31.20"
+  wire input 27 \uart_rx
+  attribute \src "ls180.v:30.13-30.20"
+  wire output 26 \uart_tx
   attribute \src "ls180.v:10348.12-10348.15"
   memory width 64 size 64 \mem
   attribute \src "ls180.v:10376.12-10376.17"
@@ -295591,6 +295591,11 @@ module \ls180
     assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3]
     assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3]
     sync posedge \sdrio_clk
+      update \sdcard_clk $0\sdcard_clk[0:0]
+      update \sdcard_cmd_o $0\sdcard_cmd_o[0:0]
+      update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0]
+      update \sdcard_data_o $0\sdcard_data_o[3:0]
+      update \sdcard_data_oe $0\sdcard_data_oe[0:0]
       update \sdram_a $0\sdram_a[12:0]
       update \sdram_dq_o $0\sdram_dq_o[15:0]
       update \sdram_dq_oe $0\sdram_dq_oe[0:0]
@@ -295602,11 +295607,6 @@ module \ls180
       update \sdram_ba $0\sdram_ba[1:0]
       update \sdram_dm $0\sdram_dm[1:0]
       update \sdram_clock $0\sdram_clock[0:0]
-      update \sdcard_clk $0\sdcard_clk[0:0]
-      update \sdcard_cmd_o $0\sdcard_cmd_o[0:0]
-      update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0]
-      update \sdcard_data_o $0\sdcard_data_o[3:0]
-      update \sdcard_data_oe $0\sdcard_data_oe[0:0]
       update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0]
       update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0]
       update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0]
@@ -295629,14 +295629,14 @@ module \ls180
   end
   attribute \src "ls180.v:7702.1-10346.4"
   process $proc$ls180.v:7702$2573
-    assign $0\uart_tx[0:0] \uart_tx
+    assign $0\pwm[1:0] \pwm
     assign $0\spisdcard_clk[0:0] \spisdcard_clk
     assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
     assign { } { }
+    assign $0\uart_tx[0:0] \uart_tx
     assign $0\spimaster_clk[0:0] \spimaster_clk
     assign $0\spimaster_mosi[0:0] \spimaster_mosi
     assign { } { }
-    assign $0\pwm[1:0] \pwm
     assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage
     assign { } { }
     assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage
@@ -300209,14 +300209,14 @@ module \ls180
         assign $0\main_libresocsim_scratch_storage[31:0] 305419896
         assign $0\main_libresocsim_scratch_re[0:0] 1'0
         assign $0\main_libresocsim_bus_errors[31:0] 0
-        assign $0\uart_tx[0:0] 1'1
+        assign $0\pwm[1:0] 2'00
         assign $0\spisdcard_clk[0:0] 1'0
         assign $0\spisdcard_mosi[0:0] 1'0
         assign $0\spisdcard_cs_n[0:0] 1'0
+        assign $0\uart_tx[0:0] 1'1
         assign $0\spimaster_clk[0:0] 1'0
         assign $0\spimaster_mosi[0:0] 1'0
         assign $0\spimaster_cs_n[0:0] 1'0
-        assign $0\pwm[1:0] 2'00
         assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0
         assign $0\main_libresocsim_load_storage[31:0] 0
         assign $0\main_libresocsim_load_re[0:0] 1'0
@@ -300504,14 +300504,14 @@ module \ls180
       case 
     end
     sync posedge \sys_clk_1
-      update \uart_tx $0\uart_tx[0:0]
+      update \pwm $0\pwm[1:0]
       update \spisdcard_clk $0\spisdcard_clk[0:0]
       update \spisdcard_mosi $0\spisdcard_mosi[0:0]
       update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
+      update \uart_tx $0\uart_tx[0:0]
       update \spimaster_clk $0\spimaster_clk[0:0]
       update \spimaster_mosi $0\spimaster_mosi[0:0]
       update \spimaster_cs_n $0\spimaster_cs_n[0:0]
-      update \pwm $0\pwm[1:0]
       update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0]
       update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0]
       update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0]
@@ -303640,9 +303640,9 @@ module \lsd_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:144987.7-144987.15"
   wire \initial
@@ -304134,9 +304134,9 @@ module \lsmem
   wire \$93
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154"
   wire \$95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 21 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
   wire input 13 \dbus__ack
@@ -314816,9 +314816,9 @@ module \mul0
   wire \alui_l_r_alui$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
   wire \alui_l_s_alui
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 32 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire output 26 \cr_a_ok
@@ -318933,9 +318933,9 @@ module \mul_pipe1
   wire $and$libresoc.v:152785$7921_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
   wire \$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 40 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:151854.7-151854.15"
   wire \initial
@@ -320761,9 +320761,9 @@ module \mul_pipe2
   wire $and$libresoc.v:153751$8014_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
   wire \$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 41 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:153061.7-153061.15"
   wire \initial
@@ -322308,9 +322308,9 @@ module \mul_pipe3
   wire $and$libresoc.v:154957$8134_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
   wire \$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 44 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 4 output 38 \cr_a
@@ -325458,9 +325458,9 @@ module \opc_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:155980.7-155980.15"
   wire \initial
@@ -325662,9 +325662,9 @@ module \opc_l$102
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:156042.7-156042.15"
   wire \initial
@@ -325866,9 +325866,9 @@ module \opc_l$11
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:156104.7-156104.15"
   wire \initial
@@ -326070,9 +326070,9 @@ module \opc_l$120
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:156166.7-156166.15"
   wire \initial
@@ -326274,9 +326274,9 @@ module \opc_l$126
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:156228.7-156228.15"
   wire \initial
@@ -326478,9 +326478,9 @@ module \opc_l$24
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:156290.7-156290.15"
   wire \initial
@@ -326682,9 +326682,9 @@ module \opc_l$40
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:156352.7-156352.15"
   wire \initial
@@ -326886,9 +326886,9 @@ module \opc_l$56
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:156414.7-156414.15"
   wire \initial
@@ -327090,9 +327090,9 @@ module \opc_l$68
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:156476.7-156476.15"
   wire \initial
@@ -327294,9 +327294,9 @@ module \opc_l$85
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:156538.7-156538.15"
   wire \initial
@@ -332696,9 +332696,9 @@ module \pimem
   wire \busy_l_r_busy
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
   wire \busy_l_s_busy
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 23 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
   wire \cyc_l_q_cyc
@@ -334516,9 +334516,9 @@ module \pipe
   wire $and$libresoc.v:160942$8724_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
   wire \$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 26 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 11 \cr_a
@@ -336056,9 +336056,9 @@ module \pipe$19
   wire output 25 \br_op__lk$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire \br_op__lk$8$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 33 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 15 \cr_a
@@ -337134,9 +337134,9 @@ module \pipe$64
   wire $and$libresoc.v:162637$8892_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
   wire \$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 34 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 11 \fast1
@@ -339205,9 +339205,9 @@ module \pipe1
   wire \alu_op__zero_a$79
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire \alu_op__zero_a$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 58 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 4 output 25 \cr_a
@@ -341191,9 +341191,9 @@ module \pipe1$110
   wire $and$libresoc.v:165468$9144_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
   wire \$65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 55 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 4 output 24 \cr_a
@@ -343358,9 +343358,9 @@ module \pipe1$32
   wire $and$libresoc.v:166454$9272_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
   wire \$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 34 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \dummy_fast1
@@ -345247,9 +345247,9 @@ module \pipe2
   wire \alu_op__zero_a$11$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire \alu_op__zero_a$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 64 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 4 input 25 \cr_a
@@ -346910,9 +346910,9 @@ module \pipe2$115
   wire $and$libresoc.v:168633$9542_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
   wire \$51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 56 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 4 input 24 \cr_a
@@ -348721,9 +348721,9 @@ module \pipe2$35
   wire $and$libresoc.v:169592$9708_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
   wire \$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 40 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 16 \fast1
@@ -350429,9 +350429,9 @@ module \pipe_end
   wire $and$libresoc.v:170985$9832_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
   wire \$74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 62 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 4 output 56 \cr_a
@@ -352935,9 +352935,9 @@ module \pipe_middle_0
   wire \$63
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
   wire \$66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 65 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
   wire input 30 \div_by_zero
@@ -355155,9 +355155,9 @@ module \pipe_start
   wire $and$libresoc.v:173442$10262_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
   wire \$66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 58 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
   wire output 30 \div_by_zero
@@ -361329,9 +361329,9 @@ module \reg_0
   wire \$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 18 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 4 input 9 \dest10__data_i
@@ -362380,9 +362380,9 @@ module \reg_0$132
   wire \$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 18 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 2 input 9 \dest10__data_i
@@ -363338,9 +363338,9 @@ module \reg_0$135
   wire width 64 \cia0__data_o$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire input 2 \cia0__ren
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 16 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 64 input 15 \d_wr10__data_i
@@ -364157,9 +364157,9 @@ module \reg_1
   wire \$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 18 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 4 input 9 \dest11__data_i
@@ -365208,9 +365208,9 @@ module \reg_1$133
   wire \$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 18 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 2 input 9 \dest11__data_i
@@ -366166,9 +366166,9 @@ module \reg_1$136
   wire width 64 \cia1__data_o$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire input 2 \cia1__ren
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 16 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 64 input 15 \d_wr11__data_i
@@ -366985,9 +366985,9 @@ module \reg_2
   wire \$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 18 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 4 input 9 \dest12__data_i
@@ -368036,9 +368036,9 @@ module \reg_2$134
   wire \$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 18 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 2 input 9 \dest12__data_i
@@ -368994,9 +368994,9 @@ module \reg_2$137
   wire width 64 \cia2__data_o$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire input 2 \cia2__ren
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 16 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 64 input 15 \d_wr12__data_i
@@ -369813,9 +369813,9 @@ module \reg_3
   wire \$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 18 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 4 input 9 \dest13__data_i
@@ -370878,9 +370878,9 @@ module \reg_4
   wire \$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 18 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 4 input 9 \dest14__data_i
@@ -371943,9 +371943,9 @@ module \reg_5
   wire \$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 18 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 4 input 9 \dest15__data_i
@@ -373008,9 +373008,9 @@ module \reg_6
   wire \$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 18 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 4 input 9 \dest16__data_i
@@ -374073,9 +374073,9 @@ module \reg_7
   wire \$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 18 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 4 input 9 \dest17__data_i
@@ -375004,9 +375004,9 @@ module \req_l
   wire width 5 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 5 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:181506.7-181506.15"
   wire \initial
@@ -375208,9 +375208,9 @@ module \req_l$103
   wire width 4 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 4 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:181568.7-181568.15"
   wire \initial
@@ -375412,9 +375412,9 @@ module \req_l$12
   wire width 3 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 3 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:181630.7-181630.15"
   wire \initial
@@ -375616,9 +375616,9 @@ module \req_l$121
   wire width 3 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 3 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:181692.7-181692.15"
   wire \initial
@@ -375820,9 +375820,9 @@ module \req_l$25
   wire width 3 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 3 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:181754.7-181754.15"
   wire \initial
@@ -376024,9 +376024,9 @@ module \req_l$41
   wire width 5 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 5 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:181816.7-181816.15"
   wire \initial
@@ -376228,9 +376228,9 @@ module \req_l$57
   wire width 2 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 2 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:181878.7-181878.15"
   wire \initial
@@ -376432,9 +376432,9 @@ module \req_l$69
   wire width 6 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 6 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:181940.7-181940.15"
   wire \initial
@@ -376636,9 +376636,9 @@ module \req_l$86
   wire width 4 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 4 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:182002.7-182002.15"
   wire \initial
@@ -376828,9 +376828,9 @@ module \reset_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:182064.7-182064.15"
   wire \initial
@@ -376987,9 +376987,9 @@ module \reset_l$131
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:182117.7-182117.15"
   wire \initial
@@ -378987,9 +378987,9 @@ module \rok_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:182761.7-182761.15"
   wire \initial
@@ -379191,9 +379191,9 @@ module \rok_l$105
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:182823.7-182823.15"
   wire \initial
@@ -379395,9 +379395,9 @@ module \rok_l$123
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:182885.7-182885.15"
   wire \initial
@@ -379599,9 +379599,9 @@ module \rok_l$14
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:182947.7-182947.15"
   wire \initial
@@ -379803,9 +379803,9 @@ module \rok_l$27
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:183009.7-183009.15"
   wire \initial
@@ -380007,9 +380007,9 @@ module \rok_l$43
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:183071.7-183071.15"
   wire \initial
@@ -380211,9 +380211,9 @@ module \rok_l$59
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:183133.7-183133.15"
   wire \initial
@@ -380415,9 +380415,9 @@ module \rok_l$71
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:183195.7-183195.15"
   wire \initial
@@ -380619,9 +380619,9 @@ module \rok_l$88
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:183257.7-183257.15"
   wire \initial
@@ -381864,9 +381864,9 @@ module \rst_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 4 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:183692.7-183692.15"
   wire \initial
@@ -382068,9 +382068,9 @@ module \rst_l$104
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 4 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:183754.7-183754.15"
   wire \initial
@@ -382272,9 +382272,9 @@ module \rst_l$122
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 4 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:183816.7-183816.15"
   wire \initial
@@ -382476,9 +382476,9 @@ module \rst_l$129
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:183878.7-183878.15"
   wire \initial
@@ -382680,9 +382680,9 @@ module \rst_l$13
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 4 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:183940.7-183940.15"
   wire \initial
@@ -382884,9 +382884,9 @@ module \rst_l$26
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 4 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:184002.7-184002.15"
   wire \initial
@@ -383088,9 +383088,9 @@ module \rst_l$42
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 4 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:184064.7-184064.15"
   wire \initial
@@ -383292,9 +383292,9 @@ module \rst_l$58
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 4 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:184126.7-184126.15"
   wire \initial
@@ -383496,9 +383496,9 @@ module \rst_l$70
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 4 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:184188.7-184188.15"
   wire \initial
@@ -383700,9 +383700,9 @@ module \rst_l$87
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 4 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:184250.7-184250.15"
   wire \initial
@@ -385446,9 +385446,9 @@ module \shiftrot0
   wire \alui_l_r_alui$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
   wire \alui_l_s_alui
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 37 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire output 33 \cr_a_ok
@@ -388019,9 +388019,9 @@ module \spr
   wire width 64 $memwr$\memory$libresoc.v:186081$12699_EN
   attribute \src "libresoc.v:186078.13-186078.16"
   wire width 7 \_0_
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 8 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:185928.7-185928.15"
   wire \initial
@@ -390111,9 +390111,9 @@ module \spr0
   wire \alui_l_r_alui$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
   wire \alui_l_s_alui
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 31 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
   wire output 7 \cu_busy_o
@@ -396007,7 +396007,7 @@ module \sram4k_0
   wire \$1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40"
   wire width 9 \a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 11 \clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43"
   wire width 64 \d
@@ -396017,7 +396017,7 @@ module \sram4k_0
   wire \initial
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42"
   wire width 64 \q
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 1 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
   wire output 5 \sram4k_0_wb__ack
@@ -396333,7 +396333,7 @@ module \sram4k_1
   wire \$1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40"
   wire width 9 \a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 11 \clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43"
   wire width 64 \d
@@ -396343,7 +396343,7 @@ module \sram4k_1
   wire \initial
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42"
   wire width 64 \q
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 1 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
   wire output 5 \sram4k_1_wb__ack
@@ -396659,7 +396659,7 @@ module \sram4k_2
   wire \$1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40"
   wire width 9 \a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 11 \clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43"
   wire width 64 \d
@@ -396669,7 +396669,7 @@ module \sram4k_2
   wire \initial
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42"
   wire width 64 \q
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 1 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
   wire output 5 \sram4k_2_wb__ack
@@ -396985,7 +396985,7 @@ module \sram4k_3
   wire \$1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40"
   wire width 9 \a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 11 \clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43"
   wire width 64 \d
@@ -396995,7 +396995,7 @@ module \sram4k_3
   wire \initial
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42"
   wire width 64 \q
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 1 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
   wire output 5 \sram4k_3_wb__ack
@@ -397305,9 +397305,9 @@ module \src_l
   wire width 4 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 4 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:190145.7-190145.15"
   wire \initial
@@ -397509,9 +397509,9 @@ module \src_l$10
   wire width 6 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 6 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:190207.7-190207.15"
   wire \initial
@@ -397713,9 +397713,9 @@ module \src_l$101
   wire width 3 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 3 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:190269.7-190269.15"
   wire \initial
@@ -397917,9 +397917,9 @@ module \src_l$119
   wire width 5 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 5 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:190331.7-190331.15"
   wire \initial
@@ -398121,9 +398121,9 @@ module \src_l$127
   wire width 3 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 3 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:190393.7-190393.15"
   wire \initial
@@ -398325,9 +398325,9 @@ module \src_l$23
   wire width 3 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 3 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:190455.7-190455.15"
   wire \initial
@@ -398529,9 +398529,9 @@ module \src_l$39
   wire width 4 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 4 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:190517.7-190517.15"
   wire \initial
@@ -398733,9 +398733,9 @@ module \src_l$55
   wire width 3 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 3 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:190579.7-190579.15"
   wire \initial
@@ -398937,9 +398937,9 @@ module \src_l$67
   wire width 6 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 6 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:190641.7-190641.15"
   wire \initial
@@ -399141,9 +399141,9 @@ module \src_l$84
   wire width 3 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire width 3 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:190703.7-190703.15"
   wire \initial
@@ -399345,9 +399345,9 @@ module \st_active
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:190765.7-190765.15"
   wire \initial
@@ -399549,9 +399549,9 @@ module \st_done
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:190827.7-190827.15"
   wire \initial
@@ -399789,9 +399789,9 @@ module \state
   wire width 64 output 3 \cia__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 3 input 2 \cia__ren
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 16 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 64 input 7 \data_i
@@ -400332,9 +400332,9 @@ module \sto_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "libresoc.v:191189.7-191189.15"
   wire \initial
@@ -400642,7 +400642,7 @@ module \svp64
   connect \major \opcode_in [31:26]
   connect \opcode_in \$1
 end
-attribute \src "libresoc.v:191310.1-192539.10"
+attribute \src "libresoc.v:191310.1-192547.10"
 attribute \cells_not_processed 1
 attribute \top 1
 attribute \nmigen.hierarchy "test_issuer"
@@ -400656,13 +400656,13 @@ module \test_issuer
   wire output 6 \TAP_bus__tdo
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
   wire input 8 \TAP_bus__tms
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:128"
   wire output 5 \busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
-  wire input 400 \clk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  wire input 404 \clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10"
-  wire width 2 input 402 \clk_sel_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:126"
+  wire width 2 input 406 \clk_sel_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:127"
   wire input 4 \core_bigendian_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
   wire input 344 \dbus__ack
@@ -400913,43 +400913,43 @@ module \test_issuer
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire input 334 \ibus__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
-  wire output 387 \icp_wb__ack
+  wire output 391 \icp_wb__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
-  wire width 28 input 381 \icp_wb__adr
+  wire width 28 input 385 \icp_wb__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
-  wire input 385 \icp_wb__cyc
+  wire input 389 \icp_wb__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
-  wire width 32 output 383 \icp_wb__dat_r
+  wire width 32 output 387 \icp_wb__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
-  wire width 32 input 382 \icp_wb__dat_w
+  wire width 32 input 386 \icp_wb__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
-  wire input 389 \icp_wb__err
+  wire input 393 \icp_wb__err
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
-  wire width 4 input 384 \icp_wb__sel
+  wire width 4 input 388 \icp_wb__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
-  wire input 386 \icp_wb__stb
+  wire input 390 \icp_wb__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81"
-  wire input 388 \icp_wb__we
+  wire input 392 \icp_wb__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
-  wire output 396 \ics_wb__ack
+  wire output 400 \ics_wb__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
-  wire width 28 input 390 \ics_wb__adr
+  wire width 28 input 394 \ics_wb__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
-  wire input 394 \ics_wb__cyc
+  wire input 398 \ics_wb__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
-  wire width 32 output 392 \ics_wb__dat_r
+  wire width 32 output 396 \ics_wb__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
-  wire width 32 input 391 \ics_wb__dat_w
+  wire width 32 input 395 \ics_wb__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
-  wire input 398 \ics_wb__err
+  wire input 402 \ics_wb__err
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
-  wire width 4 input 393 \ics_wb__sel
+  wire width 4 input 397 \ics_wb__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
-  wire input 395 \ics_wb__stb
+  wire input 399 \ics_wb__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
-  wire input 397 \ics_wb__we
+  wire input 401 \ics_wb__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
-  wire width 16 input 399 \int_level_i
+  wire width 16 input 403 \int_level_i
   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
   wire input 17 \jtag_wb__ack
   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
@@ -400968,7 +400968,7 @@ module \test_issuer
   wire output 15 \jtag_wb__stb
   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
   wire output 16 \jtag_wb__we
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:129"
   wire input 3 \memerr_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire input 121 \mspi0_clk__core__o
@@ -401019,24 +401019,24 @@ module \test_issuer
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire output 142 \mtwi_sda__pad__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
-  wire width 64 input 405 \pc_i
+  wire width 64 input 409 \pc_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire input 1 \pc_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:124"
   wire width 64 output 2 \pc_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:716"
-  wire output 403 \pll_18_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717"
+  wire output 407 \pll_18_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9"
   wire \pll_clk_24_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11"
   wire \pll_clk_pll_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13"
-  wire output 404 \pll_lck_o
+  wire output 408 \pll_lck_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12"
   wire \pll_pll_18_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732"
   wire \pllclk_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732"
   wire \pllclk_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire input 145 \pwm_0__core__o
@@ -401046,8 +401046,8 @@ module \test_issuer
   wire input 147 \pwm_1__core__o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire output 148 \pwm_1__pad__o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
-  wire input 401 \rst
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  wire input 405 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire input 155 \sd0_clk__core__o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
@@ -401415,63 +401415,71 @@ module \test_issuer
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
   wire width 64 input 350 \sram4k_0_wb__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
+  wire input 357 \sram4k_0_wb__err
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
   wire width 8 input 352 \sram4k_0_wb__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
   wire input 354 \sram4k_0_wb__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
   wire input 355 \sram4k_0_wb__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire output 364 \sram4k_1_wb__ack
+  wire output 365 \sram4k_1_wb__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire width 9 input 357 \sram4k_1_wb__adr
+  wire width 9 input 358 \sram4k_1_wb__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire input 361 \sram4k_1_wb__cyc
+  wire input 362 \sram4k_1_wb__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire width 64 output 359 \sram4k_1_wb__dat_r
+  wire width 64 output 360 \sram4k_1_wb__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire width 64 input 358 \sram4k_1_wb__dat_w
+  wire width 64 input 359 \sram4k_1_wb__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire width 8 input 360 \sram4k_1_wb__sel
+  wire input 366 \sram4k_1_wb__err
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire input 362 \sram4k_1_wb__stb
+  wire width 8 input 361 \sram4k_1_wb__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire input 363 \sram4k_1_wb__we
+  wire input 363 \sram4k_1_wb__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire output 372 \sram4k_2_wb__ack
+  wire input 364 \sram4k_1_wb__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire width 9 input 365 \sram4k_2_wb__adr
+  wire output 374 \sram4k_2_wb__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire input 369 \sram4k_2_wb__cyc
+  wire width 9 input 367 \sram4k_2_wb__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire width 64 output 367 \sram4k_2_wb__dat_r
+  wire input 371 \sram4k_2_wb__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire width 64 input 366 \sram4k_2_wb__dat_w
+  wire width 64 output 369 \sram4k_2_wb__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire width 8 input 368 \sram4k_2_wb__sel
+  wire width 64 input 368 \sram4k_2_wb__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire input 370 \sram4k_2_wb__stb
+  wire input 375 \sram4k_2_wb__err
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire input 371 \sram4k_2_wb__we
+  wire width 8 input 370 \sram4k_2_wb__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire output 380 \sram4k_3_wb__ack
+  wire input 372 \sram4k_2_wb__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire width 9 input 373 \sram4k_3_wb__adr
+  wire input 373 \sram4k_2_wb__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire input 377 \sram4k_3_wb__cyc
+  wire output 383 \sram4k_3_wb__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire width 64 output 375 \sram4k_3_wb__dat_r
+  wire width 9 input 376 \sram4k_3_wb__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire width 64 input 374 \sram4k_3_wb__dat_w
+  wire input 380 \sram4k_3_wb__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire width 8 input 376 \sram4k_3_wb__sel
+  wire width 64 output 378 \sram4k_3_wb__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire input 378 \sram4k_3_wb__stb
+  wire width 64 input 377 \sram4k_3_wb__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
-  wire input 379 \sram4k_3_wb__we
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  wire input 384 \sram4k_3_wb__err
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
+  wire width 8 input 379 \sram4k_3_wb__sel
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
+  wire input 381 \sram4k_3_wb__stb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
+  wire input 382 \sram4k_3_wb__we
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire \ti_coresync_clk
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:192133.7-192139.4"
+  attribute \src "libresoc.v:192141.7-192147.4"
   cell \pll \pll
     connect \clk_24_i \pll_clk_24_i
     connect \clk_pll_o \pll_clk_pll_o
@@ -401480,7 +401488,7 @@ module \test_issuer
     connect \pll_lck_o \pll_lck_o
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:192140.6-192533.4"
+  attribute \src "libresoc.v:192148.6-192541.4"
   cell \ti \ti
     connect \TAP_bus__tck \TAP_bus__tck
     connect \TAP_bus__tdi \TAP_bus__tdi
@@ -401881,2026 +401889,2026 @@ module \test_issuer
   connect \pll_clk_24_i \clk
   connect \pllclk_clk \pll_clk_pll_o
 end
-attribute \src "libresoc.v:192543.1-197394.10"
+attribute \src "libresoc.v:192551.1-197402.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti"
 attribute \generator "nMigen"
 module \ti
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $0\core_asmcode$next[7:0]$13879
-  attribute \src "libresoc.v:195029.3-195030.41"
+  attribute \src "libresoc.v:195037.3-195038.41"
   wire width 8 $0\core_asmcode[7:0]
-  attribute \src "libresoc.v:195942.3-195974.6"
+  attribute \src "libresoc.v:195950.3-195982.6"
   wire $0\core_bigendian_i$10$next[0:0]$13668
-  attribute \src "libresoc.v:195179.3-195180.57"
+  attribute \src "libresoc.v:195187.3-195188.57"
   wire $0\core_bigendian_i$10[0:0]$13596
-  attribute \src "libresoc.v:192724.7-192724.35"
+  attribute \src "libresoc.v:192732.7-192732.35"
   wire $0\core_bigendian_i$10[0:0]$14204
-  attribute \src "libresoc.v:196501.3-196513.6"
+  attribute \src "libresoc.v:196509.3-196521.6"
   wire width 3 $0\core_cia__ren[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 64 $0\core_core_core_cia$next[63:0]$13880
-  attribute \src "libresoc.v:195103.3-195104.53"
+  attribute \src "libresoc.v:195111.3-195112.53"
   wire width 64 $0\core_core_core_cia[63:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $0\core_core_core_cr_rd$next[7:0]$13881
-  attribute \src "libresoc.v:195147.3-195148.57"
+  attribute \src "libresoc.v:195155.3-195156.57"
   wire width 8 $0\core_core_core_cr_rd[7:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_core_cr_rd_ok$next[0:0]$13882
-  attribute \src "libresoc.v:195149.3-195150.63"
+  attribute \src "libresoc.v:195157.3-195158.63"
   wire $0\core_core_core_cr_rd_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $0\core_core_core_cr_wr$next[7:0]$13883
-  attribute \src "libresoc.v:195151.3-195152.57"
+  attribute \src "libresoc.v:195159.3-195160.57"
   wire width 8 $0\core_core_core_cr_wr[7:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_core_exc_$signal$3$next[0:0]$13884
-  attribute \src "libresoc.v:195129.3-195130.75"
+  attribute \src "libresoc.v:195137.3-195138.75"
   wire $0\core_core_core_exc_$signal$3[0:0]$13564
-  attribute \src "libresoc.v:192750.7-192750.44"
+  attribute \src "libresoc.v:192758.7-192758.44"
   wire $0\core_core_core_exc_$signal$3[0:0]$14212
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_core_exc_$signal$4$next[0:0]$13885
-  attribute \src "libresoc.v:195131.3-195132.75"
+  attribute \src "libresoc.v:195139.3-195140.75"
   wire $0\core_core_core_exc_$signal$4[0:0]$13566
-  attribute \src "libresoc.v:192754.7-192754.44"
+  attribute \src "libresoc.v:192762.7-192762.44"
   wire $0\core_core_core_exc_$signal$4[0:0]$14214
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_core_exc_$signal$5$next[0:0]$13886
-  attribute \src "libresoc.v:195133.3-195134.75"
+  attribute \src "libresoc.v:195141.3-195142.75"
   wire $0\core_core_core_exc_$signal$5[0:0]$13568
-  attribute \src "libresoc.v:192758.7-192758.44"
+  attribute \src "libresoc.v:192766.7-192766.44"
   wire $0\core_core_core_exc_$signal$5[0:0]$14216
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_core_exc_$signal$6$next[0:0]$13887
-  attribute \src "libresoc.v:195137.3-195138.75"
+  attribute \src "libresoc.v:195145.3-195146.75"
   wire $0\core_core_core_exc_$signal$6[0:0]$13571
-  attribute \src "libresoc.v:192762.7-192762.44"
+  attribute \src "libresoc.v:192770.7-192770.44"
   wire $0\core_core_core_exc_$signal$6[0:0]$14218
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_core_exc_$signal$7$next[0:0]$13888
-  attribute \src "libresoc.v:195139.3-195140.75"
+  attribute \src "libresoc.v:195147.3-195148.75"
   wire $0\core_core_core_exc_$signal$7[0:0]$13573
-  attribute \src "libresoc.v:192766.7-192766.44"
+  attribute \src "libresoc.v:192774.7-192774.44"
   wire $0\core_core_core_exc_$signal$7[0:0]$14220
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_core_exc_$signal$8$next[0:0]$13889
-  attribute \src "libresoc.v:195141.3-195142.75"
+  attribute \src "libresoc.v:195149.3-195150.75"
   wire $0\core_core_core_exc_$signal$8[0:0]$13575
-  attribute \src "libresoc.v:192770.7-192770.44"
+  attribute \src "libresoc.v:192778.7-192778.44"
   wire $0\core_core_core_exc_$signal$8[0:0]$14222
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_core_exc_$signal$9$next[0:0]$13890
-  attribute \src "libresoc.v:195143.3-195144.75"
+  attribute \src "libresoc.v:195151.3-195152.75"
   wire $0\core_core_core_exc_$signal$9[0:0]$13577
-  attribute \src "libresoc.v:192774.7-192774.44"
+  attribute \src "libresoc.v:192782.7-192782.44"
   wire $0\core_core_core_exc_$signal$9[0:0]$14224
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_core_exc_$signal$next[0:0]$13891
-  attribute \src "libresoc.v:195127.3-195128.71"
+  attribute \src "libresoc.v:195135.3-195136.71"
   wire $0\core_core_core_exc_$signal[0:0]$13562
-  attribute \src "libresoc.v:192748.7-192748.42"
+  attribute \src "libresoc.v:192756.7-192756.42"
   wire $0\core_core_core_exc_$signal[0:0]$14210
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 13 $0\core_core_core_fn_unit$next[12:0]$13892
-  attribute \src "libresoc.v:195109.3-195110.61"
+  attribute \src "libresoc.v:195117.3-195118.61"
   wire width 13 $0\core_core_core_fn_unit[12:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 2 $0\core_core_core_input_carry$next[1:0]$13893
-  attribute \src "libresoc.v:195123.3-195124.69"
+  attribute \src "libresoc.v:195131.3-195132.69"
   wire width 2 $0\core_core_core_input_carry[1:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 32 $0\core_core_core_insn$next[31:0]$13894
-  attribute \src "libresoc.v:195105.3-195106.55"
+  attribute \src "libresoc.v:195113.3-195114.55"
   wire width 32 $0\core_core_core_insn[31:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $0\core_core_core_insn_type$next[6:0]$13895
-  attribute \src "libresoc.v:195107.3-195108.65"
+  attribute \src "libresoc.v:195115.3-195116.65"
   wire width 7 $0\core_core_core_insn_type[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_core_is_32bit$next[0:0]$13896
-  attribute \src "libresoc.v:195155.3-195156.63"
+  attribute \src "libresoc.v:195163.3-195164.63"
   wire $0\core_core_core_is_32bit[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 64 $0\core_core_core_msr$next[63:0]$13897
-  attribute \src "libresoc.v:195101.3-195102.53"
+  attribute \src "libresoc.v:195109.3-195110.53"
   wire width 64 $0\core_core_core_msr[63:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_core_oe$next[0:0]$13898
-  attribute \src "libresoc.v:195119.3-195120.51"
+  attribute \src "libresoc.v:195127.3-195128.51"
   wire $0\core_core_core_oe[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_core_oe_ok$next[0:0]$13899
-  attribute \src "libresoc.v:195121.3-195122.57"
+  attribute \src "libresoc.v:195129.3-195130.57"
   wire $0\core_core_core_oe_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_core_rc$next[0:0]$13900
-  attribute \src "libresoc.v:195115.3-195116.51"
+  attribute \src "libresoc.v:195123.3-195124.51"
   wire $0\core_core_core_rc[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_core_rc_ok$next[0:0]$13901
-  attribute \src "libresoc.v:195117.3-195118.57"
+  attribute \src "libresoc.v:195125.3-195126.57"
   wire $0\core_core_core_rc_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 13 $0\core_core_core_trapaddr$next[12:0]$13902
-  attribute \src "libresoc.v:195145.3-195146.63"
+  attribute \src "libresoc.v:195153.3-195154.63"
   wire width 13 $0\core_core_core_trapaddr[12:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $0\core_core_core_traptype$next[7:0]$13903
-  attribute \src "libresoc.v:195125.3-195126.63"
+  attribute \src "libresoc.v:195133.3-195134.63"
   wire width 8 $0\core_core_core_traptype[7:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $0\core_core_cr_in1$next[6:0]$13904
-  attribute \src "libresoc.v:195083.3-195084.49"
+  attribute \src "libresoc.v:195091.3-195092.49"
   wire width 7 $0\core_core_cr_in1[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_cr_in1_ok$next[0:0]$13905
-  attribute \src "libresoc.v:195085.3-195086.55"
+  attribute \src "libresoc.v:195093.3-195094.55"
   wire $0\core_core_cr_in1_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $0\core_core_cr_in2$1$next[6:0]$13906
-  attribute \src "libresoc.v:195093.3-195094.55"
+  attribute \src "libresoc.v:195101.3-195102.55"
   wire width 7 $0\core_core_cr_in2$1[6:0]$13543
-  attribute \src "libresoc.v:192930.13-192930.41"
+  attribute \src "libresoc.v:192938.13-192938.41"
   wire width 7 $0\core_core_cr_in2$1[6:0]$14241
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $0\core_core_cr_in2$next[6:0]$13907
-  attribute \src "libresoc.v:195087.3-195088.49"
+  attribute \src "libresoc.v:195095.3-195096.49"
   wire width 7 $0\core_core_cr_in2[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_cr_in2_ok$2$next[0:0]$13908
-  attribute \src "libresoc.v:195095.3-195096.61"
+  attribute \src "libresoc.v:195103.3-195104.61"
   wire $0\core_core_cr_in2_ok$2[0:0]$13545
-  attribute \src "libresoc.v:192938.7-192938.37"
+  attribute \src "libresoc.v:192946.7-192946.37"
   wire $0\core_core_cr_in2_ok$2[0:0]$14244
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_cr_in2_ok$next[0:0]$13909
-  attribute \src "libresoc.v:195089.3-195090.55"
+  attribute \src "libresoc.v:195097.3-195098.55"
   wire $0\core_core_cr_in2_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $0\core_core_cr_out$next[6:0]$13910
-  attribute \src "libresoc.v:195097.3-195098.49"
+  attribute \src "libresoc.v:195105.3-195106.49"
   wire width 7 $0\core_core_cr_out[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_cr_wr_ok$next[0:0]$13911
-  attribute \src "libresoc.v:195153.3-195154.53"
+  attribute \src "libresoc.v:195161.3-195162.53"
   wire $0\core_core_cr_wr_ok[0:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $0\core_core_dststep$next[6:0]$13620
-  attribute \src "libresoc.v:195019.3-195020.51"
+  attribute \src "libresoc.v:195027.3-195028.51"
   wire width 7 $0\core_core_dststep[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $0\core_core_ea$next[6:0]$13912
-  attribute \src "libresoc.v:195035.3-195036.41"
+  attribute \src "libresoc.v:195043.3-195044.41"
   wire width 7 $0\core_core_ea[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $0\core_core_fast1$next[2:0]$13913
-  attribute \src "libresoc.v:195065.3-195066.47"
+  attribute \src "libresoc.v:195073.3-195074.47"
   wire width 3 $0\core_core_fast1[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_fast1_ok$next[0:0]$13914
-  attribute \src "libresoc.v:195067.3-195068.53"
+  attribute \src "libresoc.v:195075.3-195076.53"
   wire $0\core_core_fast1_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $0\core_core_fast2$next[2:0]$13915
-  attribute \src "libresoc.v:195071.3-195072.47"
+  attribute \src "libresoc.v:195079.3-195080.47"
   wire width 3 $0\core_core_fast2[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_fast2_ok$next[0:0]$13916
-  attribute \src "libresoc.v:195073.3-195074.53"
+  attribute \src "libresoc.v:195081.3-195082.53"
   wire $0\core_core_fast2_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $0\core_core_fasto1$next[2:0]$13917
-  attribute \src "libresoc.v:195075.3-195076.49"
+  attribute \src "libresoc.v:195083.3-195084.49"
   wire width 3 $0\core_core_fasto1[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $0\core_core_fasto2$next[2:0]$13918
-  attribute \src "libresoc.v:195079.3-195080.49"
+  attribute \src "libresoc.v:195087.3-195088.49"
   wire width 3 $0\core_core_fasto2[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_lk$next[0:0]$13919
-  attribute \src "libresoc.v:195111.3-195112.41"
+  attribute \src "libresoc.v:195119.3-195120.41"
   wire $0\core_core_lk[0:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $0\core_core_maxvl$next[6:0]$13621
-  attribute \src "libresoc.v:195027.3-195028.47"
+  attribute \src "libresoc.v:195035.3-195036.47"
   wire width 7 $0\core_core_maxvl[6:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 64 $0\core_core_pc$next[63:0]$13622
-  attribute \src "libresoc.v:195005.3-195006.41"
+  attribute \src "libresoc.v:195013.3-195014.41"
   wire width 64 $0\core_core_pc[63:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $0\core_core_reg1$next[6:0]$13920
-  attribute \src "libresoc.v:195039.3-195040.45"
+  attribute \src "libresoc.v:195047.3-195048.45"
   wire width 7 $0\core_core_reg1[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_reg1_ok$next[0:0]$13921
-  attribute \src "libresoc.v:195041.3-195042.51"
+  attribute \src "libresoc.v:195049.3-195050.51"
   wire $0\core_core_reg1_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $0\core_core_reg2$next[6:0]$13922
-  attribute \src "libresoc.v:195043.3-195044.45"
+  attribute \src "libresoc.v:195051.3-195052.45"
   wire width 7 $0\core_core_reg2[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_reg2_ok$next[0:0]$13923
-  attribute \src "libresoc.v:195045.3-195046.51"
+  attribute \src "libresoc.v:195053.3-195054.51"
   wire $0\core_core_reg2_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $0\core_core_reg3$next[6:0]$13924
-  attribute \src "libresoc.v:195049.3-195050.45"
+  attribute \src "libresoc.v:195057.3-195058.45"
   wire width 7 $0\core_core_reg3[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_reg3_ok$next[0:0]$13925
-  attribute \src "libresoc.v:195051.3-195052.51"
+  attribute \src "libresoc.v:195059.3-195060.51"
   wire $0\core_core_reg3_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $0\core_core_rego$next[6:0]$13926
-  attribute \src "libresoc.v:195031.3-195032.45"
+  attribute \src "libresoc.v:195039.3-195040.45"
   wire width 7 $0\core_core_rego[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 10 $0\core_core_spr1$next[9:0]$13927
-  attribute \src "libresoc.v:195057.3-195058.45"
+  attribute \src "libresoc.v:195065.3-195066.45"
   wire width 10 $0\core_core_spr1[9:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_core_spr1_ok$next[0:0]$13928
-  attribute \src "libresoc.v:195059.3-195060.51"
+  attribute \src "libresoc.v:195067.3-195068.51"
   wire $0\core_core_spr1_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 10 $0\core_core_spro$next[9:0]$13929
-  attribute \src "libresoc.v:195053.3-195054.45"
+  attribute \src "libresoc.v:195061.3-195062.45"
   wire width 10 $0\core_core_spro[9:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $0\core_core_srcstep$next[6:0]$13623
-  attribute \src "libresoc.v:195021.3-195022.51"
+  attribute \src "libresoc.v:195029.3-195030.51"
   wire width 7 $0\core_core_srcstep[6:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 2 $0\core_core_subvl$next[1:0]$13624
-  attribute \src "libresoc.v:195017.3-195018.47"
+  attribute \src "libresoc.v:195025.3-195026.47"
   wire width 2 $0\core_core_subvl[1:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 2 $0\core_core_svstep$next[1:0]$13625
-  attribute \src "libresoc.v:195015.3-195016.49"
+  attribute \src "libresoc.v:195023.3-195024.49"
   wire width 2 $0\core_core_svstep[1:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $0\core_core_vl$next[6:0]$13626
-  attribute \src "libresoc.v:195023.3-195024.41"
+  attribute \src "libresoc.v:195031.3-195032.41"
   wire width 7 $0\core_core_vl[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $0\core_core_xer_in$next[2:0]$13930
-  attribute \src "libresoc.v:195061.3-195062.49"
+  attribute \src "libresoc.v:195069.3-195070.49"
   wire width 3 $0\core_core_xer_in[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_cr_out_ok$next[0:0]$13931
-  attribute \src "libresoc.v:195099.3-195100.45"
+  attribute \src "libresoc.v:195107.3-195108.45"
   wire $0\core_cr_out_ok[0:0]
-  attribute \src "libresoc.v:196012.3-196021.6"
+  attribute \src "libresoc.v:196020.3-196029.6"
   wire width 64 $0\core_data_i$12[63:0]$13680
-  attribute \src "libresoc.v:196587.3-196612.6"
+  attribute \src "libresoc.v:196595.3-196620.6"
   wire width 64 $0\core_data_i[63:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 64 $0\core_dec$next[63:0]$13627
-  attribute \src "libresoc.v:195013.3-195014.33"
+  attribute \src "libresoc.v:195021.3-195022.33"
   wire width 64 $0\core_dec[63:0]
-  attribute \src "libresoc.v:196199.3-196208.6"
+  attribute \src "libresoc.v:196207.3-196216.6"
   wire width 5 $0\core_dmi__addr[4:0]
-  attribute \src "libresoc.v:196209.3-196218.6"
+  attribute \src "libresoc.v:196217.3-196226.6"
   wire $0\core_dmi__ren[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_ea_ok$next[0:0]$13932
-  attribute \src "libresoc.v:195037.3-195038.37"
+  attribute \src "libresoc.v:195045.3-195046.37"
   wire $0\core_ea_ok[0:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire $0\core_eint$next[0:0]$13628
-  attribute \src "libresoc.v:195011.3-195012.35"
+  attribute \src "libresoc.v:195019.3-195020.35"
   wire $0\core_eint[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_fasto1_ok$next[0:0]$13933
-  attribute \src "libresoc.v:195077.3-195078.45"
+  attribute \src "libresoc.v:195085.3-195086.45"
   wire $0\core_fasto1_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_fasto2_ok$next[0:0]$13934
-  attribute \src "libresoc.v:195081.3-195082.45"
+  attribute \src "libresoc.v:195089.3-195090.45"
   wire $0\core_fasto2_ok[0:0]
-  attribute \src "libresoc.v:196248.3-196257.6"
+  attribute \src "libresoc.v:196256.3-196265.6"
   wire width 8 $0\core_full_rd2__ren[7:0]
-  attribute \src "libresoc.v:196287.3-196296.6"
+  attribute \src "libresoc.v:196295.3-196304.6"
   wire width 3 $0\core_full_rd__ren[2:0]
-  attribute \src "libresoc.v:196395.3-196409.6"
+  attribute \src "libresoc.v:196403.3-196417.6"
   wire width 3 $0\core_issue__addr$13[2:0]$13733
-  attribute \src "libresoc.v:196326.3-196340.6"
+  attribute \src "libresoc.v:196334.3-196348.6"
   wire width 3 $0\core_issue__addr[2:0]
-  attribute \src "libresoc.v:196425.3-196439.6"
+  attribute \src "libresoc.v:196433.3-196447.6"
   wire width 64 $0\core_issue__data_i[63:0]
-  attribute \src "libresoc.v:196341.3-196355.6"
+  attribute \src "libresoc.v:196349.3-196363.6"
   wire $0\core_issue__ren[0:0]
-  attribute \src "libresoc.v:196410.3-196424.6"
+  attribute \src "libresoc.v:196418.3-196432.6"
   wire $0\core_issue__wen[0:0]
-  attribute \src "libresoc.v:196058.3-196073.6"
+  attribute \src "libresoc.v:196066.3-196081.6"
   wire $0\core_issue_i[0:0]
-  attribute \src "libresoc.v:196033.3-196057.6"
+  attribute \src "libresoc.v:196041.3-196065.6"
   wire $0\core_ivalid_i[0:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 64 $0\core_msr$next[63:0]$13629
-  attribute \src "libresoc.v:195009.3-195010.33"
+  attribute \src "libresoc.v:195017.3-195018.33"
   wire width 64 $0\core_msr[63:0]
-  attribute \src "libresoc.v:196613.3-196628.6"
+  attribute \src "libresoc.v:196621.3-196636.6"
   wire width 3 $0\core_msr__ren[2:0]
-  attribute \src "libresoc.v:195909.3-195941.6"
+  attribute \src "libresoc.v:195917.3-195949.6"
   wire width 32 $0\core_raw_insn_i$next[31:0]$13661
-  attribute \src "libresoc.v:194983.3-194984.47"
+  attribute \src "libresoc.v:194991.3-194992.47"
   wire width 32 $0\core_raw_insn_i[31:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_rego_ok$next[0:0]$13935
-  attribute \src "libresoc.v:195033.3-195034.41"
+  attribute \src "libresoc.v:195041.3-195042.41"
   wire $0\core_rego_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_spro_ok$next[0:0]$13936
-  attribute \src "libresoc.v:195055.3-195056.41"
+  attribute \src "libresoc.v:195063.3-195064.41"
   wire $0\core_spro_ok[0:0]
-  attribute \src "libresoc.v:197161.3-197191.6"
+  attribute \src "libresoc.v:197169.3-197199.6"
   wire $0\core_stopped_i[0:0]
-  attribute \src "libresoc.v:196539.3-196551.6"
+  attribute \src "libresoc.v:196547.3-196559.6"
   wire width 3 $0\core_sv__ren[2:0]
-  attribute \src "libresoc.v:196002.3-196011.6"
+  attribute \src "libresoc.v:196010.3-196019.6"
   wire width 3 $0\core_wen$11[2:0]$13677
-  attribute \src "libresoc.v:196561.3-196586.6"
+  attribute \src "libresoc.v:196569.3-196594.6"
   wire width 3 $0\core_wen[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $0\core_xer_out$next[0:0]$13937
-  attribute \src "libresoc.v:195063.3-195064.41"
+  attribute \src "libresoc.v:195071.3-195072.41"
   wire $0\core_xer_out[0:0]
-  attribute \src "libresoc.v:194989.3-194990.43"
+  attribute \src "libresoc.v:194997.3-194998.43"
   wire $0\cu_st__rel_o_dly[0:0]
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $0\cur_cur_dststep$next[6:0]$13774
-  attribute \src "libresoc.v:195189.3-195190.47"
+  attribute \src "libresoc.v:195197.3-195198.47"
   wire width 7 $0\cur_cur_dststep[6:0]
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $0\cur_cur_maxvl$next[6:0]$13775
-  attribute \src "libresoc.v:195195.3-195196.43"
+  attribute \src "libresoc.v:195203.3-195204.43"
   wire width 7 $0\cur_cur_maxvl[6:0]
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 2 $0\cur_cur_subvl$next[1:0]$13776
-  attribute \src "libresoc.v:195187.3-195188.43"
+  attribute \src "libresoc.v:195195.3-195196.43"
   wire width 2 $0\cur_cur_subvl[1:0]
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 2 $0\cur_cur_svstep$next[1:0]$13777
-  attribute \src "libresoc.v:195185.3-195186.45"
+  attribute \src "libresoc.v:195193.3-195194.45"
   wire width 2 $0\cur_cur_svstep[1:0]
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $0\cur_cur_vl$next[6:0]$13778
-  attribute \src "libresoc.v:195193.3-195194.37"
+  attribute \src "libresoc.v:195201.3-195202.37"
   wire width 7 $0\cur_cur_vl[6:0]
-  attribute \src "libresoc.v:196258.3-196266.6"
+  attribute \src "libresoc.v:196266.3-196274.6"
   wire $0\d_cr_delay$next[0:0]$13715
-  attribute \src "libresoc.v:195069.3-195070.37"
+  attribute \src "libresoc.v:195077.3-195078.37"
   wire $0\d_cr_delay[0:0]
-  attribute \src "libresoc.v:196219.3-196227.6"
+  attribute \src "libresoc.v:196227.3-196235.6"
   wire $0\d_reg_delay$next[0:0]$13709
-  attribute \src "libresoc.v:195091.3-195092.39"
+  attribute \src "libresoc.v:195099.3-195100.39"
   wire $0\d_reg_delay[0:0]
-  attribute \src "libresoc.v:196297.3-196305.6"
+  attribute \src "libresoc.v:196305.3-196313.6"
   wire $0\d_xer_delay$next[0:0]$13721
-  attribute \src "libresoc.v:195047.3-195048.39"
+  attribute \src "libresoc.v:195055.3-195056.39"
   wire $0\d_xer_delay[0:0]
-  attribute \src "libresoc.v:197192.3-197222.6"
+  attribute \src "libresoc.v:197200.3-197230.6"
   wire $0\dbg_core_stopped_i[0:0]
-  attribute \src "libresoc.v:196277.3-196286.6"
+  attribute \src "libresoc.v:196285.3-196294.6"
   wire $0\dbg_d_cr_ack[0:0]
-  attribute \src "libresoc.v:196267.3-196276.6"
+  attribute \src "libresoc.v:196275.3-196284.6"
   wire width 64 $0\dbg_d_cr_data[63:0]
-  attribute \src "libresoc.v:196238.3-196247.6"
+  attribute \src "libresoc.v:196246.3-196255.6"
   wire $0\dbg_d_gpr_ack[0:0]
-  attribute \src "libresoc.v:196228.3-196237.6"
+  attribute \src "libresoc.v:196236.3-196245.6"
   wire width 64 $0\dbg_d_gpr_data[63:0]
-  attribute \src "libresoc.v:196316.3-196325.6"
+  attribute \src "libresoc.v:196324.3-196333.6"
   wire $0\dbg_d_xer_ack[0:0]
-  attribute \src "libresoc.v:196306.3-196315.6"
+  attribute \src "libresoc.v:196314.3-196323.6"
   wire width 64 $0\dbg_d_xer_data[63:0]
-  attribute \src "libresoc.v:195831.3-195839.6"
+  attribute \src "libresoc.v:195839.3-195847.6"
   wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13608
-  attribute \src "libresoc.v:195007.3-195008.45"
+  attribute \src "libresoc.v:195015.3-195016.45"
   wire width 4 $0\dbg_dmi_addr_i[3:0]
-  attribute \src "libresoc.v:196552.3-196560.6"
+  attribute \src "libresoc.v:196560.3-196568.6"
   wire width 64 $0\dbg_dmi_din$next[63:0]$13756
-  attribute \src "libresoc.v:194999.3-195000.39"
+  attribute \src "libresoc.v:195007.3-195008.39"
   wire width 64 $0\dbg_dmi_din[63:0]
-  attribute \src "libresoc.v:195840.3-195848.6"
+  attribute \src "libresoc.v:195848.3-195856.6"
   wire $0\dbg_dmi_req_i$next[0:0]$13611
-  attribute \src "libresoc.v:195003.3-195004.43"
+  attribute \src "libresoc.v:195011.3-195012.43"
   wire $0\dbg_dmi_req_i[0:0]
-  attribute \src "libresoc.v:196467.3-196475.6"
+  attribute \src "libresoc.v:196475.3-196483.6"
   wire $0\dbg_dmi_we_i$next[0:0]$13743
-  attribute \src "libresoc.v:195001.3-195002.41"
+  attribute \src "libresoc.v:195009.3-195010.41"
   wire $0\dbg_dmi_we_i[0:0]
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $0\dec2_cur_cur_srcstep$next[6:0]$13779
-  attribute \src "libresoc.v:195191.3-195192.57"
+  attribute \src "libresoc.v:195199.3-195200.57"
   wire width 7 $0\dec2_cur_cur_srcstep[6:0]
-  attribute \src "libresoc.v:196440.3-196455.6"
+  attribute \src "libresoc.v:196448.3-196463.6"
   wire width 64 $0\dec2_cur_dec$next[63:0]$13738
-  attribute \src "libresoc.v:194981.3-194982.41"
+  attribute \src "libresoc.v:194989.3-194990.41"
   wire width 64 $0\dec2_cur_dec[63:0]
-  attribute \src "libresoc.v:195849.3-195857.6"
+  attribute \src "libresoc.v:195857.3-195865.6"
   wire $0\dec2_cur_eint$next[0:0]$13614
-  attribute \src "libresoc.v:194993.3-194994.43"
+  attribute \src "libresoc.v:195001.3-195002.43"
   wire $0\dec2_cur_eint[0:0]
-  attribute \src "libresoc.v:196936.3-196956.6"
+  attribute \src "libresoc.v:196944.3-196964.6"
   wire width 64 $0\dec2_cur_msr$next[63:0]$13823
-  attribute \src "libresoc.v:195177.3-195178.41"
+  attribute \src "libresoc.v:195185.3-195186.41"
   wire width 64 $0\dec2_cur_msr[63:0]
-  attribute \src "libresoc.v:196775.3-196795.6"
+  attribute \src "libresoc.v:196783.3-196803.6"
   wire width 64 $0\dec2_cur_pc$next[63:0]$13769
-  attribute \src "libresoc.v:195197.3-195198.39"
+  attribute \src "libresoc.v:195205.3-195206.39"
   wire width 64 $0\dec2_cur_pc[63:0]
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 9 $0\dec2_dec_svp64__extra$next[8:0]$13830
-  attribute \src "libresoc.v:195165.3-195166.59"
+  attribute \src "libresoc.v:195173.3-195174.59"
   wire width 9 $0\dec2_dec_svp64__extra[8:0]
-  attribute \src "libresoc.v:195199.3-195200.40"
+  attribute \src "libresoc.v:195207.3-195208.40"
   wire width 32 $0\dec2_raw_opcode_in[31:0]
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 2 $0\dec_svp64__elwidth$next[1:0]$13831
-  attribute \src "libresoc.v:195171.3-195172.53"
+  attribute \src "libresoc.v:195179.3-195180.53"
   wire width 2 $0\dec_svp64__elwidth[1:0]
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 2 $0\dec_svp64__ewsrc$next[1:0]$13832
-  attribute \src "libresoc.v:195169.3-195170.49"
+  attribute \src "libresoc.v:195177.3-195178.49"
   wire width 2 $0\dec_svp64__ewsrc[1:0]
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 3 $0\dec_svp64__mask$next[2:0]$13833
-  attribute \src "libresoc.v:195173.3-195174.47"
+  attribute \src "libresoc.v:195181.3-195182.47"
   wire width 3 $0\dec_svp64__mask[2:0]
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire $0\dec_svp64__mmode$next[0:0]$13834
-  attribute \src "libresoc.v:195175.3-195176.49"
+  attribute \src "libresoc.v:195183.3-195184.49"
   wire $0\dec_svp64__mmode[0:0]
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 5 $0\dec_svp64__mode$next[4:0]$13835
-  attribute \src "libresoc.v:195163.3-195164.47"
+  attribute \src "libresoc.v:195171.3-195172.47"
   wire width 5 $0\dec_svp64__mode[4:0]
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 2 $0\dec_svp64__subvl$next[1:0]$13836
-  attribute \src "libresoc.v:195167.3-195168.49"
+  attribute \src "libresoc.v:195175.3-195176.49"
   wire width 2 $0\dec_svp64__subvl[1:0]
-  attribute \src "libresoc.v:195858.3-195867.6"
+  attribute \src "libresoc.v:195866.3-195875.6"
   wire width 2 $0\delay$next[1:0]$13617
-  attribute \src "libresoc.v:194991.3-194992.27"
+  attribute \src "libresoc.v:194999.3-195000.27"
   wire width 2 $0\delay[1:0]
-  attribute \src "libresoc.v:196074.3-196108.6"
+  attribute \src "libresoc.v:196082.3-196116.6"
   wire $0\exec_fsm_state$next[0:0]$13686
-  attribute \src "libresoc.v:195157.3-195158.45"
+  attribute \src "libresoc.v:195165.3-195166.45"
   wire $0\exec_fsm_state[0:0]
-  attribute \src "libresoc.v:196022.3-196032.6"
+  attribute \src "libresoc.v:196030.3-196040.6"
   wire $0\exec_insn_ready_o[0:0]
-  attribute \src "libresoc.v:195975.3-195985.6"
+  attribute \src "libresoc.v:195983.3-195993.6"
   wire $0\exec_insn_valid_i[0:0]
-  attribute \src "libresoc.v:196183.3-196198.6"
+  attribute \src "libresoc.v:196191.3-196206.6"
   wire $0\exec_pc_ready_i[0:0]
-  attribute \src "libresoc.v:195986.3-196001.6"
+  attribute \src "libresoc.v:195994.3-196009.6"
   wire $0\exec_pc_valid_o[0:0]
-  attribute \src "libresoc.v:196874.3-196935.6"
+  attribute \src "libresoc.v:196882.3-196943.6"
   wire width 2 $0\fetch_fsm_state$next[1:0]$13814
-  attribute \src "libresoc.v:195181.3-195182.47"
+  attribute \src "libresoc.v:195189.3-195190.47"
   wire width 2 $0\fetch_fsm_state[1:0]
-  attribute \src "libresoc.v:197052.3-197087.6"
+  attribute \src "libresoc.v:197060.3-197095.6"
   wire width 32 $0\fetch_insn_o[31:0]
-  attribute \src "libresoc.v:197234.3-197244.6"
+  attribute \src "libresoc.v:197242.3-197252.6"
   wire $0\fetch_insn_ready_i[0:0]
-  attribute \src "libresoc.v:197088.3-197098.6"
+  attribute \src "libresoc.v:197096.3-197106.6"
   wire $0\fetch_insn_valid_o[0:0]
-  attribute \src "libresoc.v:196638.3-196648.6"
+  attribute \src "libresoc.v:196646.3-196656.6"
   wire $0\fetch_pc_ready_o[0:0]
-  attribute \src "libresoc.v:197223.3-197233.6"
+  attribute \src "libresoc.v:197231.3-197241.6"
   wire $0\fetch_pc_valid_i[0:0]
-  attribute \src "libresoc.v:196356.3-196383.6"
+  attribute \src "libresoc.v:196364.3-196391.6"
   wire width 2 $0\fsm_state$next[1:0]$13728
-  attribute \src "libresoc.v:195025.3-195026.35"
+  attribute \src "libresoc.v:195033.3-195034.35"
   wire width 2 $0\fsm_state[1:0]
-  attribute \src "libresoc.v:196649.3-196684.6"
+  attribute \src "libresoc.v:196657.3-196692.6"
   wire width 48 $0\imem_a_pc_i[47:0]
-  attribute \src "libresoc.v:196685.3-196729.6"
+  attribute \src "libresoc.v:196693.3-196737.6"
   wire $0\imem_a_valid_i[0:0]
-  attribute \src "libresoc.v:196730.3-196774.6"
+  attribute \src "libresoc.v:196738.3-196782.6"
   wire $0\imem_f_valid_i[0:0]
-  attribute \src "libresoc.v:192544.7-192544.20"
+  attribute \src "libresoc.v:192552.7-192552.20"
   wire $0\initial[0:0]
-  attribute \src "libresoc.v:196167.3-196182.6"
+  attribute \src "libresoc.v:196175.3-196190.6"
   wire $0\insn_done[0:0]
-  attribute \src "libresoc.v:197099.3-197160.6"
+  attribute \src "libresoc.v:197107.3-197168.6"
   wire width 3 $0\issue_fsm_state$next[2:0]$13865
-  attribute \src "libresoc.v:195159.3-195160.47"
+  attribute \src "libresoc.v:195167.3-195168.47"
   wire width 3 $0\issue_fsm_state[2:0]
-  attribute \src "libresoc.v:196629.3-196637.6"
+  attribute \src "libresoc.v:196637.3-196645.6"
   wire $0\jtag_dmi0__ack_o$next[0:0]$13762
-  attribute \src "libresoc.v:194997.3-194998.49"
+  attribute \src "libresoc.v:195005.3-195006.49"
   wire $0\jtag_dmi0__ack_o[0:0]
-  attribute \src "libresoc.v:196835.3-196843.6"
+  attribute \src "libresoc.v:196843.3-196851.6"
   wire width 64 $0\jtag_dmi0__dout$next[63:0]$13805
-  attribute \src "libresoc.v:194995.3-194996.47"
+  attribute \src "libresoc.v:195003.3-195004.47"
   wire width 64 $0\jtag_dmi0__dout[63:0]
-  attribute \src "libresoc.v:196844.3-196873.6"
+  attribute \src "libresoc.v:196852.3-196881.6"
   wire $0\msr_read$next[0:0]$13808
-  attribute \src "libresoc.v:195183.3-195184.33"
+  attribute \src "libresoc.v:195191.3-195192.33"
   wire $0\msr_read[0:0]
-  attribute \src "libresoc.v:196384.3-196394.6"
+  attribute \src "libresoc.v:196392.3-196402.6"
   wire width 64 $0\new_dec[63:0]
-  attribute \src "libresoc.v:196456.3-196466.6"
+  attribute \src "libresoc.v:196464.3-196474.6"
   wire width 64 $0\new_tb[63:0]
-  attribute \src "libresoc.v:197033.3-197051.6"
+  attribute \src "libresoc.v:197041.3-197059.6"
   wire width 64 $0\nia$next[63:0]$13859
-  attribute \src "libresoc.v:195161.3-195162.23"
+  attribute \src "libresoc.v:195169.3-195170.23"
   wire width 64 $0\nia[63:0]
-  attribute \src "libresoc.v:196485.3-196500.6"
+  attribute \src "libresoc.v:196493.3-196508.6"
   wire width 64 $0\pc[63:0]
-  attribute \src "libresoc.v:196138.3-196166.6"
+  attribute \src "libresoc.v:196146.3-196174.6"
   wire $0\pc_changed$next[0:0]$13699
-  attribute \src "libresoc.v:195113.3-195114.37"
+  attribute \src "libresoc.v:195121.3-195122.37"
   wire $0\pc_changed[0:0]
-  attribute \src "libresoc.v:196476.3-196484.6"
+  attribute \src "libresoc.v:196484.3-196492.6"
   wire $0\pc_ok_delay$next[0:0]$13746
-  attribute \src "libresoc.v:194987.3-194988.39"
+  attribute \src "libresoc.v:194995.3-194996.39"
   wire $0\pc_ok_delay[0:0]
-  attribute \src "libresoc.v:196109.3-196137.6"
+  attribute \src "libresoc.v:196117.3-196145.6"
   wire $0\sv_changed$next[0:0]$13693
-  attribute \src "libresoc.v:195135.3-195136.37"
+  attribute \src "libresoc.v:195143.3-195144.37"
   wire $0\sv_changed[0:0]
-  attribute \src "libresoc.v:196976.3-196994.6"
+  attribute \src "libresoc.v:196984.3-197002.6"
   wire $0\svp64_bigendian[0:0]
-  attribute \src "libresoc.v:196957.3-196975.6"
+  attribute \src "libresoc.v:196965.3-196983.6"
   wire width 32 $0\svp64_raw_opcode_in[31:0]
-  attribute \src "libresoc.v:196523.3-196538.6"
+  attribute \src "libresoc.v:196531.3-196546.6"
   wire width 64 $0\svstate[63:0]
-  attribute \src "libresoc.v:196514.3-196522.6"
+  attribute \src "libresoc.v:196522.3-196530.6"
   wire $0\svstate_ok_delay$next[0:0]$13751
-  attribute \src "libresoc.v:194985.3-194986.49"
+  attribute \src "libresoc.v:194993.3-194994.49"
   wire $0\svstate_ok_delay[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $1\core_asmcode$next[7:0]$13938
-  attribute \src "libresoc.v:192718.13-192718.33"
+  attribute \src "libresoc.v:192726.13-192726.33"
   wire width 8 $1\core_asmcode[7:0]
-  attribute \src "libresoc.v:195942.3-195974.6"
+  attribute \src "libresoc.v:195950.3-195982.6"
   wire $1\core_bigendian_i$10$next[0:0]$13669
-  attribute \src "libresoc.v:196501.3-196513.6"
+  attribute \src "libresoc.v:196509.3-196521.6"
   wire width 3 $1\core_cia__ren[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 64 $1\core_core_core_cia$next[63:0]$13939
-  attribute \src "libresoc.v:192732.14-192732.55"
+  attribute \src "libresoc.v:192740.14-192740.55"
   wire width 64 $1\core_core_core_cia[63:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $1\core_core_core_cr_rd$next[7:0]$13940
-  attribute \src "libresoc.v:192736.13-192736.41"
+  attribute \src "libresoc.v:192744.13-192744.41"
   wire width 8 $1\core_core_core_cr_rd[7:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_core_cr_rd_ok$next[0:0]$13941
-  attribute \src "libresoc.v:192740.7-192740.37"
+  attribute \src "libresoc.v:192748.7-192748.37"
   wire $1\core_core_core_cr_rd_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $1\core_core_core_cr_wr$next[7:0]$13942
-  attribute \src "libresoc.v:192744.13-192744.41"
+  attribute \src "libresoc.v:192752.13-192752.41"
   wire width 8 $1\core_core_core_cr_wr[7:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_core_exc_$signal$3$next[0:0]$13943
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_core_exc_$signal$4$next[0:0]$13944
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_core_exc_$signal$5$next[0:0]$13945
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_core_exc_$signal$6$next[0:0]$13946
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_core_exc_$signal$7$next[0:0]$13947
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_core_exc_$signal$8$next[0:0]$13948
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_core_exc_$signal$9$next[0:0]$13949
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_core_exc_$signal$next[0:0]$13950
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 13 $1\core_core_core_fn_unit$next[12:0]$13951
-  attribute \src "libresoc.v:192794.14-192794.47"
+  attribute \src "libresoc.v:192802.14-192802.47"
   wire width 13 $1\core_core_core_fn_unit[12:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 2 $1\core_core_core_input_carry$next[1:0]$13952
-  attribute \src "libresoc.v:192802.13-192802.46"
+  attribute \src "libresoc.v:192810.13-192810.46"
   wire width 2 $1\core_core_core_input_carry[1:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 32 $1\core_core_core_insn$next[31:0]$13953
-  attribute \src "libresoc.v:192806.14-192806.41"
+  attribute \src "libresoc.v:192814.14-192814.41"
   wire width 32 $1\core_core_core_insn[31:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $1\core_core_core_insn_type$next[6:0]$13954
-  attribute \src "libresoc.v:192884.13-192884.45"
+  attribute \src "libresoc.v:192892.13-192892.45"
   wire width 7 $1\core_core_core_insn_type[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_core_is_32bit$next[0:0]$13955
-  attribute \src "libresoc.v:192888.7-192888.37"
+  attribute \src "libresoc.v:192896.7-192896.37"
   wire $1\core_core_core_is_32bit[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 64 $1\core_core_core_msr$next[63:0]$13956
-  attribute \src "libresoc.v:192892.14-192892.55"
+  attribute \src "libresoc.v:192900.14-192900.55"
   wire width 64 $1\core_core_core_msr[63:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_core_oe$next[0:0]$13957
-  attribute \src "libresoc.v:192896.7-192896.31"
+  attribute \src "libresoc.v:192904.7-192904.31"
   wire $1\core_core_core_oe[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_core_oe_ok$next[0:0]$13958
-  attribute \src "libresoc.v:192900.7-192900.34"
+  attribute \src "libresoc.v:192908.7-192908.34"
   wire $1\core_core_core_oe_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_core_rc$next[0:0]$13959
-  attribute \src "libresoc.v:192904.7-192904.31"
+  attribute \src "libresoc.v:192912.7-192912.31"
   wire $1\core_core_core_rc[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_core_rc_ok$next[0:0]$13960
-  attribute \src "libresoc.v:192908.7-192908.34"
+  attribute \src "libresoc.v:192916.7-192916.34"
   wire $1\core_core_core_rc_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 13 $1\core_core_core_trapaddr$next[12:0]$13961
-  attribute \src "libresoc.v:192912.14-192912.48"
+  attribute \src "libresoc.v:192920.14-192920.48"
   wire width 13 $1\core_core_core_trapaddr[12:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $1\core_core_core_traptype$next[7:0]$13962
-  attribute \src "libresoc.v:192916.13-192916.44"
+  attribute \src "libresoc.v:192924.13-192924.44"
   wire width 8 $1\core_core_core_traptype[7:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $1\core_core_cr_in1$next[6:0]$13963
-  attribute \src "libresoc.v:192920.13-192920.37"
+  attribute \src "libresoc.v:192928.13-192928.37"
   wire width 7 $1\core_core_cr_in1[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_cr_in1_ok$next[0:0]$13964
-  attribute \src "libresoc.v:192924.7-192924.33"
+  attribute \src "libresoc.v:192932.7-192932.33"
   wire $1\core_core_cr_in1_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $1\core_core_cr_in2$1$next[6:0]$13965
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $1\core_core_cr_in2$next[6:0]$13966
-  attribute \src "libresoc.v:192928.13-192928.37"
+  attribute \src "libresoc.v:192936.13-192936.37"
   wire width 7 $1\core_core_cr_in2[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_cr_in2_ok$2$next[0:0]$13967
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_cr_in2_ok$next[0:0]$13968
-  attribute \src "libresoc.v:192936.7-192936.33"
+  attribute \src "libresoc.v:192944.7-192944.33"
   wire $1\core_core_cr_in2_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $1\core_core_cr_out$next[6:0]$13969
-  attribute \src "libresoc.v:192944.13-192944.37"
+  attribute \src "libresoc.v:192952.13-192952.37"
   wire width 7 $1\core_core_cr_out[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_cr_wr_ok$next[0:0]$13970
-  attribute \src "libresoc.v:192948.7-192948.32"
+  attribute \src "libresoc.v:192956.7-192956.32"
   wire $1\core_core_cr_wr_ok[0:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $1\core_core_dststep$next[6:0]$13630
-  attribute \src "libresoc.v:192952.13-192952.38"
+  attribute \src "libresoc.v:192960.13-192960.38"
   wire width 7 $1\core_core_dststep[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $1\core_core_ea$next[6:0]$13971
-  attribute \src "libresoc.v:192956.13-192956.33"
+  attribute \src "libresoc.v:192964.13-192964.33"
   wire width 7 $1\core_core_ea[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $1\core_core_fast1$next[2:0]$13972
-  attribute \src "libresoc.v:192960.13-192960.35"
+  attribute \src "libresoc.v:192968.13-192968.35"
   wire width 3 $1\core_core_fast1[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_fast1_ok$next[0:0]$13973
-  attribute \src "libresoc.v:192964.7-192964.32"
+  attribute \src "libresoc.v:192972.7-192972.32"
   wire $1\core_core_fast1_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $1\core_core_fast2$next[2:0]$13974
-  attribute \src "libresoc.v:192968.13-192968.35"
+  attribute \src "libresoc.v:192976.13-192976.35"
   wire width 3 $1\core_core_fast2[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_fast2_ok$next[0:0]$13975
-  attribute \src "libresoc.v:192972.7-192972.32"
+  attribute \src "libresoc.v:192980.7-192980.32"
   wire $1\core_core_fast2_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $1\core_core_fasto1$next[2:0]$13976
-  attribute \src "libresoc.v:192976.13-192976.36"
+  attribute \src "libresoc.v:192984.13-192984.36"
   wire width 3 $1\core_core_fasto1[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $1\core_core_fasto2$next[2:0]$13977
-  attribute \src "libresoc.v:192980.13-192980.36"
+  attribute \src "libresoc.v:192988.13-192988.36"
   wire width 3 $1\core_core_fasto2[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_lk$next[0:0]$13978
-  attribute \src "libresoc.v:192984.7-192984.26"
+  attribute \src "libresoc.v:192992.7-192992.26"
   wire $1\core_core_lk[0:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $1\core_core_maxvl$next[6:0]$13631
-  attribute \src "libresoc.v:192988.13-192988.36"
+  attribute \src "libresoc.v:192996.13-192996.36"
   wire width 7 $1\core_core_maxvl[6:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 64 $1\core_core_pc$next[63:0]$13632
-  attribute \src "libresoc.v:192992.14-192992.49"
+  attribute \src "libresoc.v:193000.14-193000.49"
   wire width 64 $1\core_core_pc[63:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $1\core_core_reg1$next[6:0]$13979
-  attribute \src "libresoc.v:192996.13-192996.35"
+  attribute \src "libresoc.v:193004.13-193004.35"
   wire width 7 $1\core_core_reg1[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_reg1_ok$next[0:0]$13980
-  attribute \src "libresoc.v:193000.7-193000.31"
+  attribute \src "libresoc.v:193008.7-193008.31"
   wire $1\core_core_reg1_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $1\core_core_reg2$next[6:0]$13981
-  attribute \src "libresoc.v:193004.13-193004.35"
+  attribute \src "libresoc.v:193012.13-193012.35"
   wire width 7 $1\core_core_reg2[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_reg2_ok$next[0:0]$13982
-  attribute \src "libresoc.v:193008.7-193008.31"
+  attribute \src "libresoc.v:193016.7-193016.31"
   wire $1\core_core_reg2_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $1\core_core_reg3$next[6:0]$13983
-  attribute \src "libresoc.v:193012.13-193012.35"
+  attribute \src "libresoc.v:193020.13-193020.35"
   wire width 7 $1\core_core_reg3[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_reg3_ok$next[0:0]$13984
-  attribute \src "libresoc.v:193016.7-193016.31"
+  attribute \src "libresoc.v:193024.7-193024.31"
   wire $1\core_core_reg3_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $1\core_core_rego$next[6:0]$13985
-  attribute \src "libresoc.v:193020.13-193020.35"
+  attribute \src "libresoc.v:193028.13-193028.35"
   wire width 7 $1\core_core_rego[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 10 $1\core_core_spr1$next[9:0]$13986
-  attribute \src "libresoc.v:193138.13-193138.37"
+  attribute \src "libresoc.v:193146.13-193146.37"
   wire width 10 $1\core_core_spr1[9:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_core_spr1_ok$next[0:0]$13987
-  attribute \src "libresoc.v:193142.7-193142.31"
+  attribute \src "libresoc.v:193150.7-193150.31"
   wire $1\core_core_spr1_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 10 $1\core_core_spro$next[9:0]$13988
-  attribute \src "libresoc.v:193260.13-193260.37"
+  attribute \src "libresoc.v:193268.13-193268.37"
   wire width 10 $1\core_core_spro[9:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $1\core_core_srcstep$next[6:0]$13633
-  attribute \src "libresoc.v:193264.13-193264.38"
+  attribute \src "libresoc.v:193272.13-193272.38"
   wire width 7 $1\core_core_srcstep[6:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 2 $1\core_core_subvl$next[1:0]$13634
-  attribute \src "libresoc.v:193268.13-193268.35"
+  attribute \src "libresoc.v:193276.13-193276.35"
   wire width 2 $1\core_core_subvl[1:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 2 $1\core_core_svstep$next[1:0]$13635
-  attribute \src "libresoc.v:193272.13-193272.36"
+  attribute \src "libresoc.v:193280.13-193280.36"
   wire width 2 $1\core_core_svstep[1:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $1\core_core_vl$next[6:0]$13636
-  attribute \src "libresoc.v:193278.13-193278.33"
+  attribute \src "libresoc.v:193286.13-193286.33"
   wire width 7 $1\core_core_vl[6:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $1\core_core_xer_in$next[2:0]$13989
-  attribute \src "libresoc.v:193282.13-193282.36"
+  attribute \src "libresoc.v:193290.13-193290.36"
   wire width 3 $1\core_core_xer_in[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_cr_out_ok$next[0:0]$13990
-  attribute \src "libresoc.v:193290.7-193290.28"
+  attribute \src "libresoc.v:193298.7-193298.28"
   wire $1\core_cr_out_ok[0:0]
-  attribute \src "libresoc.v:196012.3-196021.6"
+  attribute \src "libresoc.v:196020.3-196029.6"
   wire width 64 $1\core_data_i$12[63:0]$13681
-  attribute \src "libresoc.v:196587.3-196612.6"
+  attribute \src "libresoc.v:196595.3-196620.6"
   wire width 64 $1\core_data_i[63:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 64 $1\core_dec$next[63:0]$13637
-  attribute \src "libresoc.v:193318.14-193318.45"
+  attribute \src "libresoc.v:193326.14-193326.45"
   wire width 64 $1\core_dec[63:0]
-  attribute \src "libresoc.v:196199.3-196208.6"
+  attribute \src "libresoc.v:196207.3-196216.6"
   wire width 5 $1\core_dmi__addr[4:0]
-  attribute \src "libresoc.v:196209.3-196218.6"
+  attribute \src "libresoc.v:196217.3-196226.6"
   wire $1\core_dmi__ren[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_ea_ok$next[0:0]$13991
-  attribute \src "libresoc.v:193328.7-193328.24"
+  attribute \src "libresoc.v:193336.7-193336.24"
   wire $1\core_ea_ok[0:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire $1\core_eint$next[0:0]$13638
-  attribute \src "libresoc.v:193332.7-193332.23"
+  attribute \src "libresoc.v:193340.7-193340.23"
   wire $1\core_eint[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_fasto1_ok$next[0:0]$13992
-  attribute \src "libresoc.v:193336.7-193336.28"
+  attribute \src "libresoc.v:193344.7-193344.28"
   wire $1\core_fasto1_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_fasto2_ok$next[0:0]$13993
-  attribute \src "libresoc.v:193340.7-193340.28"
+  attribute \src "libresoc.v:193348.7-193348.28"
   wire $1\core_fasto2_ok[0:0]
-  attribute \src "libresoc.v:196248.3-196257.6"
+  attribute \src "libresoc.v:196256.3-196265.6"
   wire width 8 $1\core_full_rd2__ren[7:0]
-  attribute \src "libresoc.v:196287.3-196296.6"
+  attribute \src "libresoc.v:196295.3-196304.6"
   wire width 3 $1\core_full_rd__ren[2:0]
-  attribute \src "libresoc.v:196395.3-196409.6"
+  attribute \src "libresoc.v:196403.3-196417.6"
   wire width 3 $1\core_issue__addr$13[2:0]$13734
-  attribute \src "libresoc.v:196326.3-196340.6"
+  attribute \src "libresoc.v:196334.3-196348.6"
   wire width 3 $1\core_issue__addr[2:0]
-  attribute \src "libresoc.v:196425.3-196439.6"
+  attribute \src "libresoc.v:196433.3-196447.6"
   wire width 64 $1\core_issue__data_i[63:0]
-  attribute \src "libresoc.v:196341.3-196355.6"
+  attribute \src "libresoc.v:196349.3-196363.6"
   wire $1\core_issue__ren[0:0]
-  attribute \src "libresoc.v:196410.3-196424.6"
+  attribute \src "libresoc.v:196418.3-196432.6"
   wire $1\core_issue__wen[0:0]
-  attribute \src "libresoc.v:196058.3-196073.6"
+  attribute \src "libresoc.v:196066.3-196081.6"
   wire $1\core_issue_i[0:0]
-  attribute \src "libresoc.v:196033.3-196057.6"
+  attribute \src "libresoc.v:196041.3-196065.6"
   wire $1\core_ivalid_i[0:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 64 $1\core_msr$next[63:0]$13639
-  attribute \src "libresoc.v:193368.14-193368.45"
+  attribute \src "libresoc.v:193376.14-193376.45"
   wire width 64 $1\core_msr[63:0]
-  attribute \src "libresoc.v:196613.3-196628.6"
+  attribute \src "libresoc.v:196621.3-196636.6"
   wire width 3 $1\core_msr__ren[2:0]
-  attribute \src "libresoc.v:195909.3-195941.6"
+  attribute \src "libresoc.v:195917.3-195949.6"
   wire width 32 $1\core_raw_insn_i$next[31:0]$13662
-  attribute \src "libresoc.v:193376.14-193376.37"
+  attribute \src "libresoc.v:193384.14-193384.37"
   wire width 32 $1\core_raw_insn_i[31:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_rego_ok$next[0:0]$13994
-  attribute \src "libresoc.v:193380.7-193380.26"
+  attribute \src "libresoc.v:193388.7-193388.26"
   wire $1\core_rego_ok[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_spro_ok$next[0:0]$13995
-  attribute \src "libresoc.v:193384.7-193384.26"
+  attribute \src "libresoc.v:193392.7-193392.26"
   wire $1\core_spro_ok[0:0]
-  attribute \src "libresoc.v:197161.3-197191.6"
+  attribute \src "libresoc.v:197169.3-197199.6"
   wire $1\core_stopped_i[0:0]
-  attribute \src "libresoc.v:196539.3-196551.6"
+  attribute \src "libresoc.v:196547.3-196559.6"
   wire width 3 $1\core_sv__ren[2:0]
-  attribute \src "libresoc.v:196002.3-196011.6"
+  attribute \src "libresoc.v:196010.3-196019.6"
   wire width 3 $1\core_wen$11[2:0]$13678
-  attribute \src "libresoc.v:196561.3-196586.6"
+  attribute \src "libresoc.v:196569.3-196594.6"
   wire width 3 $1\core_wen[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $1\core_xer_out$next[0:0]$13996
-  attribute \src "libresoc.v:193402.7-193402.26"
+  attribute \src "libresoc.v:193410.7-193410.26"
   wire $1\core_xer_out[0:0]
-  attribute \src "libresoc.v:193408.7-193408.30"
+  attribute \src "libresoc.v:193416.7-193416.30"
   wire $1\cu_st__rel_o_dly[0:0]
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $1\cur_cur_dststep$next[6:0]$13780
-  attribute \src "libresoc.v:193414.13-193414.36"
+  attribute \src "libresoc.v:193422.13-193422.36"
   wire width 7 $1\cur_cur_dststep[6:0]
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $1\cur_cur_maxvl$next[6:0]$13781
-  attribute \src "libresoc.v:193418.13-193418.34"
+  attribute \src "libresoc.v:193426.13-193426.34"
   wire width 7 $1\cur_cur_maxvl[6:0]
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 2 $1\cur_cur_subvl$next[1:0]$13782
-  attribute \src "libresoc.v:193422.13-193422.33"
+  attribute \src "libresoc.v:193430.13-193430.33"
   wire width 2 $1\cur_cur_subvl[1:0]
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 2 $1\cur_cur_svstep$next[1:0]$13783
-  attribute \src "libresoc.v:193426.13-193426.34"
+  attribute \src "libresoc.v:193434.13-193434.34"
   wire width 2 $1\cur_cur_svstep[1:0]
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $1\cur_cur_vl$next[6:0]$13784
-  attribute \src "libresoc.v:193430.13-193430.31"
+  attribute \src "libresoc.v:193438.13-193438.31"
   wire width 7 $1\cur_cur_vl[6:0]
-  attribute \src "libresoc.v:196258.3-196266.6"
+  attribute \src "libresoc.v:196266.3-196274.6"
   wire $1\d_cr_delay$next[0:0]$13716
-  attribute \src "libresoc.v:193434.7-193434.24"
+  attribute \src "libresoc.v:193442.7-193442.24"
   wire $1\d_cr_delay[0:0]
-  attribute \src "libresoc.v:196219.3-196227.6"
+  attribute \src "libresoc.v:196227.3-196235.6"
   wire $1\d_reg_delay$next[0:0]$13710
-  attribute \src "libresoc.v:193438.7-193438.25"
+  attribute \src "libresoc.v:193446.7-193446.25"
   wire $1\d_reg_delay[0:0]
-  attribute \src "libresoc.v:196297.3-196305.6"
+  attribute \src "libresoc.v:196305.3-196313.6"
   wire $1\d_xer_delay$next[0:0]$13722
-  attribute \src "libresoc.v:193442.7-193442.25"
+  attribute \src "libresoc.v:193450.7-193450.25"
   wire $1\d_xer_delay[0:0]
-  attribute \src "libresoc.v:197192.3-197222.6"
+  attribute \src "libresoc.v:197200.3-197230.6"
   wire $1\dbg_core_stopped_i[0:0]
-  attribute \src "libresoc.v:196277.3-196286.6"
+  attribute \src "libresoc.v:196285.3-196294.6"
   wire $1\dbg_d_cr_ack[0:0]
-  attribute \src "libresoc.v:196267.3-196276.6"
+  attribute \src "libresoc.v:196275.3-196284.6"
   wire width 64 $1\dbg_d_cr_data[63:0]
-  attribute \src "libresoc.v:196238.3-196247.6"
+  attribute \src "libresoc.v:196246.3-196255.6"
   wire $1\dbg_d_gpr_ack[0:0]
-  attribute \src "libresoc.v:196228.3-196237.6"
+  attribute \src "libresoc.v:196236.3-196245.6"
   wire width 64 $1\dbg_d_gpr_data[63:0]
-  attribute \src "libresoc.v:196316.3-196325.6"
+  attribute \src "libresoc.v:196324.3-196333.6"
   wire $1\dbg_d_xer_ack[0:0]
-  attribute \src "libresoc.v:196306.3-196315.6"
+  attribute \src "libresoc.v:196314.3-196323.6"
   wire width 64 $1\dbg_d_xer_data[63:0]
-  attribute \src "libresoc.v:195831.3-195839.6"
+  attribute \src "libresoc.v:195839.3-195847.6"
   wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13609
-  attribute \src "libresoc.v:193478.13-193478.34"
+  attribute \src "libresoc.v:193486.13-193486.34"
   wire width 4 $1\dbg_dmi_addr_i[3:0]
-  attribute \src "libresoc.v:196552.3-196560.6"
+  attribute \src "libresoc.v:196560.3-196568.6"
   wire width 64 $1\dbg_dmi_din$next[63:0]$13757
-  attribute \src "libresoc.v:193482.14-193482.48"
+  attribute \src "libresoc.v:193490.14-193490.48"
   wire width 64 $1\dbg_dmi_din[63:0]
-  attribute \src "libresoc.v:195840.3-195848.6"
+  attribute \src "libresoc.v:195848.3-195856.6"
   wire $1\dbg_dmi_req_i$next[0:0]$13612
-  attribute \src "libresoc.v:193488.7-193488.27"
+  attribute \src "libresoc.v:193496.7-193496.27"
   wire $1\dbg_dmi_req_i[0:0]
-  attribute \src "libresoc.v:196467.3-196475.6"
+  attribute \src "libresoc.v:196475.3-196483.6"
   wire $1\dbg_dmi_we_i$next[0:0]$13744
-  attribute \src "libresoc.v:193492.7-193492.26"
+  attribute \src "libresoc.v:193500.7-193500.26"
   wire $1\dbg_dmi_we_i[0:0]
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $1\dec2_cur_cur_srcstep$next[6:0]$13785
-  attribute \src "libresoc.v:193546.13-193546.41"
+  attribute \src "libresoc.v:193554.13-193554.41"
   wire width 7 $1\dec2_cur_cur_srcstep[6:0]
-  attribute \src "libresoc.v:196440.3-196455.6"
+  attribute \src "libresoc.v:196448.3-196463.6"
   wire width 64 $1\dec2_cur_dec$next[63:0]$13739
-  attribute \src "libresoc.v:193550.14-193550.49"
+  attribute \src "libresoc.v:193558.14-193558.49"
   wire width 64 $1\dec2_cur_dec[63:0]
-  attribute \src "libresoc.v:195849.3-195857.6"
+  attribute \src "libresoc.v:195857.3-195865.6"
   wire $1\dec2_cur_eint$next[0:0]$13615
-  attribute \src "libresoc.v:193554.7-193554.27"
+  attribute \src "libresoc.v:193562.7-193562.27"
   wire $1\dec2_cur_eint[0:0]
-  attribute \src "libresoc.v:196936.3-196956.6"
+  attribute \src "libresoc.v:196944.3-196964.6"
   wire width 64 $1\dec2_cur_msr$next[63:0]$13824
-  attribute \src "libresoc.v:193558.14-193558.49"
+  attribute \src "libresoc.v:193566.14-193566.49"
   wire width 64 $1\dec2_cur_msr[63:0]
-  attribute \src "libresoc.v:196775.3-196795.6"
+  attribute \src "libresoc.v:196783.3-196803.6"
   wire width 64 $1\dec2_cur_pc$next[63:0]$13770
-  attribute \src "libresoc.v:193562.14-193562.48"
+  attribute \src "libresoc.v:193570.14-193570.48"
   wire width 64 $1\dec2_cur_pc[63:0]
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 9 $1\dec2_dec_svp64__extra$next[8:0]$13837
-  attribute \src "libresoc.v:193566.13-193566.43"
+  attribute \src "libresoc.v:193574.13-193574.43"
   wire width 9 $1\dec2_dec_svp64__extra[8:0]
-  attribute \src "libresoc.v:193716.14-193716.40"
+  attribute \src "libresoc.v:193724.14-193724.40"
   wire width 32 $1\dec2_raw_opcode_in[31:0]
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 2 $1\dec_svp64__elwidth$next[1:0]$13838
-  attribute \src "libresoc.v:193984.13-193984.38"
+  attribute \src "libresoc.v:193992.13-193992.38"
   wire width 2 $1\dec_svp64__elwidth[1:0]
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 2 $1\dec_svp64__ewsrc$next[1:0]$13839
-  attribute \src "libresoc.v:193988.13-193988.36"
+  attribute \src "libresoc.v:193996.13-193996.36"
   wire width 2 $1\dec_svp64__ewsrc[1:0]
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 3 $1\dec_svp64__mask$next[2:0]$13840
-  attribute \src "libresoc.v:193992.13-193992.35"
+  attribute \src "libresoc.v:194000.13-194000.35"
   wire width 3 $1\dec_svp64__mask[2:0]
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire $1\dec_svp64__mmode$next[0:0]$13841
-  attribute \src "libresoc.v:193996.7-193996.30"
+  attribute \src "libresoc.v:194004.7-194004.30"
   wire $1\dec_svp64__mmode[0:0]
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 5 $1\dec_svp64__mode$next[4:0]$13842
-  attribute \src "libresoc.v:194000.13-194000.36"
+  attribute \src "libresoc.v:194008.13-194008.36"
   wire width 5 $1\dec_svp64__mode[4:0]
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 2 $1\dec_svp64__subvl$next[1:0]$13843
-  attribute \src "libresoc.v:194004.13-194004.36"
+  attribute \src "libresoc.v:194012.13-194012.36"
   wire width 2 $1\dec_svp64__subvl[1:0]
-  attribute \src "libresoc.v:195858.3-195867.6"
+  attribute \src "libresoc.v:195866.3-195875.6"
   wire width 2 $1\delay$next[1:0]$13618
-  attribute \src "libresoc.v:194008.13-194008.25"
+  attribute \src "libresoc.v:194016.13-194016.25"
   wire width 2 $1\delay[1:0]
-  attribute \src "libresoc.v:196074.3-196108.6"
+  attribute \src "libresoc.v:196082.3-196116.6"
   wire $1\exec_fsm_state$next[0:0]$13687
-  attribute \src "libresoc.v:194024.7-194024.28"
+  attribute \src "libresoc.v:194032.7-194032.28"
   wire $1\exec_fsm_state[0:0]
-  attribute \src "libresoc.v:196022.3-196032.6"
+  attribute \src "libresoc.v:196030.3-196040.6"
   wire $1\exec_insn_ready_o[0:0]
-  attribute \src "libresoc.v:195975.3-195985.6"
+  attribute \src "libresoc.v:195983.3-195993.6"
   wire $1\exec_insn_valid_i[0:0]
-  attribute \src "libresoc.v:196183.3-196198.6"
+  attribute \src "libresoc.v:196191.3-196206.6"
   wire $1\exec_pc_ready_i[0:0]
-  attribute \src "libresoc.v:195986.3-196001.6"
+  attribute \src "libresoc.v:195994.3-196009.6"
   wire $1\exec_pc_valid_o[0:0]
-  attribute \src "libresoc.v:196874.3-196935.6"
+  attribute \src "libresoc.v:196882.3-196943.6"
   wire width 2 $1\fetch_fsm_state$next[1:0]$13815
-  attribute \src "libresoc.v:194036.13-194036.35"
+  attribute \src "libresoc.v:194044.13-194044.35"
   wire width 2 $1\fetch_fsm_state[1:0]
-  attribute \src "libresoc.v:197052.3-197087.6"
+  attribute \src "libresoc.v:197060.3-197095.6"
   wire width 32 $1\fetch_insn_o[31:0]
-  attribute \src "libresoc.v:197234.3-197244.6"
+  attribute \src "libresoc.v:197242.3-197252.6"
   wire $1\fetch_insn_ready_i[0:0]
-  attribute \src "libresoc.v:197088.3-197098.6"
+  attribute \src "libresoc.v:197096.3-197106.6"
   wire $1\fetch_insn_valid_o[0:0]
-  attribute \src "libresoc.v:196638.3-196648.6"
+  attribute \src "libresoc.v:196646.3-196656.6"
   wire $1\fetch_pc_ready_o[0:0]
-  attribute \src "libresoc.v:197223.3-197233.6"
+  attribute \src "libresoc.v:197231.3-197241.6"
   wire $1\fetch_pc_valid_i[0:0]
-  attribute \src "libresoc.v:196356.3-196383.6"
+  attribute \src "libresoc.v:196364.3-196391.6"
   wire width 2 $1\fsm_state$next[1:0]$13729
-  attribute \src "libresoc.v:194050.13-194050.29"
+  attribute \src "libresoc.v:194058.13-194058.29"
   wire width 2 $1\fsm_state[1:0]
-  attribute \src "libresoc.v:196649.3-196684.6"
+  attribute \src "libresoc.v:196657.3-196692.6"
   wire width 48 $1\imem_a_pc_i[47:0]
-  attribute \src "libresoc.v:196685.3-196729.6"
+  attribute \src "libresoc.v:196693.3-196737.6"
   wire $1\imem_a_valid_i[0:0]
-  attribute \src "libresoc.v:196730.3-196774.6"
+  attribute \src "libresoc.v:196738.3-196782.6"
   wire $1\imem_f_valid_i[0:0]
-  attribute \src "libresoc.v:196167.3-196182.6"
+  attribute \src "libresoc.v:196175.3-196190.6"
   wire $1\insn_done[0:0]
-  attribute \src "libresoc.v:197099.3-197160.6"
+  attribute \src "libresoc.v:197107.3-197168.6"
   wire width 3 $1\issue_fsm_state$next[2:0]$13866
-  attribute \src "libresoc.v:194306.13-194306.35"
+  attribute \src "libresoc.v:194314.13-194314.35"
   wire width 3 $1\issue_fsm_state[2:0]
-  attribute \src "libresoc.v:196629.3-196637.6"
+  attribute \src "libresoc.v:196637.3-196645.6"
   wire $1\jtag_dmi0__ack_o$next[0:0]$13763
-  attribute \src "libresoc.v:194310.7-194310.30"
+  attribute \src "libresoc.v:194318.7-194318.30"
   wire $1\jtag_dmi0__ack_o[0:0]
-  attribute \src "libresoc.v:196835.3-196843.6"
+  attribute \src "libresoc.v:196843.3-196851.6"
   wire width 64 $1\jtag_dmi0__dout$next[63:0]$13806
-  attribute \src "libresoc.v:194318.14-194318.52"
+  attribute \src "libresoc.v:194326.14-194326.52"
   wire width 64 $1\jtag_dmi0__dout[63:0]
-  attribute \src "libresoc.v:196844.3-196873.6"
+  attribute \src "libresoc.v:196852.3-196881.6"
   wire $1\msr_read$next[0:0]$13809
-  attribute \src "libresoc.v:194376.7-194376.22"
+  attribute \src "libresoc.v:194384.7-194384.22"
   wire $1\msr_read[0:0]
-  attribute \src "libresoc.v:196384.3-196394.6"
+  attribute \src "libresoc.v:196392.3-196402.6"
   wire width 64 $1\new_dec[63:0]
-  attribute \src "libresoc.v:196456.3-196466.6"
+  attribute \src "libresoc.v:196464.3-196474.6"
   wire width 64 $1\new_tb[63:0]
-  attribute \src "libresoc.v:197033.3-197051.6"
+  attribute \src "libresoc.v:197041.3-197059.6"
   wire width 64 $1\nia$next[63:0]$13860
-  attribute \src "libresoc.v:194412.14-194412.40"
+  attribute \src "libresoc.v:194420.14-194420.40"
   wire width 64 $1\nia[63:0]
-  attribute \src "libresoc.v:196485.3-196500.6"
+  attribute \src "libresoc.v:196493.3-196508.6"
   wire width 64 $1\pc[63:0]
-  attribute \src "libresoc.v:196138.3-196166.6"
+  attribute \src "libresoc.v:196146.3-196174.6"
   wire $1\pc_changed$next[0:0]$13700
-  attribute \src "libresoc.v:194418.7-194418.24"
+  attribute \src "libresoc.v:194426.7-194426.24"
   wire $1\pc_changed[0:0]
-  attribute \src "libresoc.v:196476.3-196484.6"
+  attribute \src "libresoc.v:196484.3-196492.6"
   wire $1\pc_ok_delay$next[0:0]$13747
-  attribute \src "libresoc.v:194428.7-194428.25"
+  attribute \src "libresoc.v:194436.7-194436.25"
   wire $1\pc_ok_delay[0:0]
-  attribute \src "libresoc.v:196109.3-196137.6"
+  attribute \src "libresoc.v:196117.3-196145.6"
   wire $1\sv_changed$next[0:0]$13694
-  attribute \src "libresoc.v:194872.7-194872.24"
+  attribute \src "libresoc.v:194880.7-194880.24"
   wire $1\sv_changed[0:0]
-  attribute \src "libresoc.v:196976.3-196994.6"
+  attribute \src "libresoc.v:196984.3-197002.6"
   wire $1\svp64_bigendian[0:0]
-  attribute \src "libresoc.v:196957.3-196975.6"
+  attribute \src "libresoc.v:196965.3-196983.6"
   wire width 32 $1\svp64_raw_opcode_in[31:0]
-  attribute \src "libresoc.v:196523.3-196538.6"
+  attribute \src "libresoc.v:196531.3-196546.6"
   wire width 64 $1\svstate[63:0]
-  attribute \src "libresoc.v:196514.3-196522.6"
+  attribute \src "libresoc.v:196522.3-196530.6"
   wire $1\svstate_ok_delay$next[0:0]$13752
-  attribute \src "libresoc.v:194890.7-194890.30"
+  attribute \src "libresoc.v:194898.7-194898.30"
   wire $1\svstate_ok_delay[0:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $2\core_asmcode$next[7:0]$13997
-  attribute \src "libresoc.v:195942.3-195974.6"
+  attribute \src "libresoc.v:195950.3-195982.6"
   wire $2\core_bigendian_i$10$next[0:0]$13670
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 64 $2\core_core_core_cia$next[63:0]$13998
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $2\core_core_core_cr_rd$next[7:0]$13999
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_core_cr_rd_ok$next[0:0]$14000
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $2\core_core_core_cr_wr$next[7:0]$14001
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_core_exc_$signal$3$next[0:0]$14002
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_core_exc_$signal$4$next[0:0]$14003
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_core_exc_$signal$5$next[0:0]$14004
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_core_exc_$signal$6$next[0:0]$14005
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_core_exc_$signal$7$next[0:0]$14006
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_core_exc_$signal$8$next[0:0]$14007
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_core_exc_$signal$9$next[0:0]$14008
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_core_exc_$signal$next[0:0]$14009
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 13 $2\core_core_core_fn_unit$next[12:0]$14010
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 2 $2\core_core_core_input_carry$next[1:0]$14011
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 32 $2\core_core_core_insn$next[31:0]$14012
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $2\core_core_core_insn_type$next[6:0]$14013
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_core_is_32bit$next[0:0]$14014
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 64 $2\core_core_core_msr$next[63:0]$14015
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_core_oe$next[0:0]$14016
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_core_oe_ok$next[0:0]$14017
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_core_rc$next[0:0]$14018
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_core_rc_ok$next[0:0]$14019
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 13 $2\core_core_core_trapaddr$next[12:0]$14020
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $2\core_core_core_traptype$next[7:0]$14021
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $2\core_core_cr_in1$next[6:0]$14022
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_cr_in1_ok$next[0:0]$14023
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $2\core_core_cr_in2$1$next[6:0]$14024
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $2\core_core_cr_in2$next[6:0]$14025
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_cr_in2_ok$2$next[0:0]$14026
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_cr_in2_ok$next[0:0]$14027
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $2\core_core_cr_out$next[6:0]$14028
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_cr_wr_ok$next[0:0]$14029
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $2\core_core_dststep$next[6:0]$13640
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $2\core_core_ea$next[6:0]$14030
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $2\core_core_fast1$next[2:0]$14031
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_fast1_ok$next[0:0]$14032
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $2\core_core_fast2$next[2:0]$14033
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_fast2_ok$next[0:0]$14034
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $2\core_core_fasto1$next[2:0]$14035
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $2\core_core_fasto2$next[2:0]$14036
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_lk$next[0:0]$14037
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $2\core_core_maxvl$next[6:0]$13641
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 64 $2\core_core_pc$next[63:0]$13642
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $2\core_core_reg1$next[6:0]$14038
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_reg1_ok$next[0:0]$14039
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $2\core_core_reg2$next[6:0]$14040
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_reg2_ok$next[0:0]$14041
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $2\core_core_reg3$next[6:0]$14042
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_reg3_ok$next[0:0]$14043
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $2\core_core_rego$next[6:0]$14044
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 10 $2\core_core_spr1$next[9:0]$14045
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_core_spr1_ok$next[0:0]$14046
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 10 $2\core_core_spro$next[9:0]$14047
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $2\core_core_srcstep$next[6:0]$13643
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 2 $2\core_core_subvl$next[1:0]$13644
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 2 $2\core_core_svstep$next[1:0]$13645
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $2\core_core_vl$next[6:0]$13646
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $2\core_core_xer_in$next[2:0]$14048
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_cr_out_ok$next[0:0]$14049
-  attribute \src "libresoc.v:196587.3-196612.6"
+  attribute \src "libresoc.v:196595.3-196620.6"
   wire width 64 $2\core_data_i[63:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 64 $2\core_dec$next[63:0]$13647
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_ea_ok$next[0:0]$14050
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire $2\core_eint$next[0:0]$13648
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_fasto1_ok$next[0:0]$14051
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_fasto2_ok$next[0:0]$14052
-  attribute \src "libresoc.v:196058.3-196073.6"
+  attribute \src "libresoc.v:196066.3-196081.6"
   wire $2\core_issue_i[0:0]
-  attribute \src "libresoc.v:196033.3-196057.6"
+  attribute \src "libresoc.v:196041.3-196065.6"
   wire $2\core_ivalid_i[0:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 64 $2\core_msr$next[63:0]$13649
-  attribute \src "libresoc.v:196613.3-196628.6"
+  attribute \src "libresoc.v:196621.3-196636.6"
   wire width 3 $2\core_msr__ren[2:0]
-  attribute \src "libresoc.v:195909.3-195941.6"
+  attribute \src "libresoc.v:195917.3-195949.6"
   wire width 32 $2\core_raw_insn_i$next[31:0]$13663
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_rego_ok$next[0:0]$14053
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_spro_ok$next[0:0]$14054
-  attribute \src "libresoc.v:197161.3-197191.6"
+  attribute \src "libresoc.v:197169.3-197199.6"
   wire $2\core_stopped_i[0:0]
-  attribute \src "libresoc.v:196561.3-196586.6"
+  attribute \src "libresoc.v:196569.3-196594.6"
   wire width 3 $2\core_wen[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $2\core_xer_out$next[0:0]$14055
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $2\cur_cur_dststep$next[6:0]$13786
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $2\cur_cur_maxvl$next[6:0]$13787
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 2 $2\cur_cur_subvl$next[1:0]$13788
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 2 $2\cur_cur_svstep$next[1:0]$13789
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $2\cur_cur_vl$next[6:0]$13790
-  attribute \src "libresoc.v:197192.3-197222.6"
+  attribute \src "libresoc.v:197200.3-197230.6"
   wire $2\dbg_core_stopped_i[0:0]
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $2\dec2_cur_cur_srcstep$next[6:0]$13791
-  attribute \src "libresoc.v:196440.3-196455.6"
+  attribute \src "libresoc.v:196448.3-196463.6"
   wire width 64 $2\dec2_cur_dec$next[63:0]$13740
-  attribute \src "libresoc.v:196936.3-196956.6"
+  attribute \src "libresoc.v:196944.3-196964.6"
   wire width 64 $2\dec2_cur_msr$next[63:0]$13825
-  attribute \src "libresoc.v:196775.3-196795.6"
+  attribute \src "libresoc.v:196783.3-196803.6"
   wire width 64 $2\dec2_cur_pc$next[63:0]$13771
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 9 $2\dec2_dec_svp64__extra$next[8:0]$13844
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 2 $2\dec_svp64__elwidth$next[1:0]$13845
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 2 $2\dec_svp64__ewsrc$next[1:0]$13846
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 3 $2\dec_svp64__mask$next[2:0]$13847
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire $2\dec_svp64__mmode$next[0:0]$13848
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 5 $2\dec_svp64__mode$next[4:0]$13849
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 2 $2\dec_svp64__subvl$next[1:0]$13850
-  attribute \src "libresoc.v:196074.3-196108.6"
+  attribute \src "libresoc.v:196082.3-196116.6"
   wire $2\exec_fsm_state$next[0:0]$13688
-  attribute \src "libresoc.v:196183.3-196198.6"
+  attribute \src "libresoc.v:196191.3-196206.6"
   wire $2\exec_pc_ready_i[0:0]
-  attribute \src "libresoc.v:195986.3-196001.6"
+  attribute \src "libresoc.v:195994.3-196009.6"
   wire $2\exec_pc_valid_o[0:0]
-  attribute \src "libresoc.v:196874.3-196935.6"
+  attribute \src "libresoc.v:196882.3-196943.6"
   wire width 2 $2\fetch_fsm_state$next[1:0]$13816
-  attribute \src "libresoc.v:197052.3-197087.6"
+  attribute \src "libresoc.v:197060.3-197095.6"
   wire width 32 $2\fetch_insn_o[31:0]
-  attribute \src "libresoc.v:196356.3-196383.6"
+  attribute \src "libresoc.v:196364.3-196391.6"
   wire width 2 $2\fsm_state$next[1:0]$13730
-  attribute \src "libresoc.v:196649.3-196684.6"
+  attribute \src "libresoc.v:196657.3-196692.6"
   wire width 48 $2\imem_a_pc_i[47:0]
-  attribute \src "libresoc.v:196685.3-196729.6"
+  attribute \src "libresoc.v:196693.3-196737.6"
   wire $2\imem_a_valid_i[0:0]
-  attribute \src "libresoc.v:196730.3-196774.6"
+  attribute \src "libresoc.v:196738.3-196782.6"
   wire $2\imem_f_valid_i[0:0]
-  attribute \src "libresoc.v:196167.3-196182.6"
+  attribute \src "libresoc.v:196175.3-196190.6"
   wire $2\insn_done[0:0]
-  attribute \src "libresoc.v:197099.3-197160.6"
+  attribute \src "libresoc.v:197107.3-197168.6"
   wire width 3 $2\issue_fsm_state$next[2:0]$13867
-  attribute \src "libresoc.v:196844.3-196873.6"
+  attribute \src "libresoc.v:196852.3-196881.6"
   wire $2\msr_read$next[0:0]$13810
-  attribute \src "libresoc.v:197033.3-197051.6"
+  attribute \src "libresoc.v:197041.3-197059.6"
   wire width 64 $2\nia$next[63:0]$13861
-  attribute \src "libresoc.v:196485.3-196500.6"
+  attribute \src "libresoc.v:196493.3-196508.6"
   wire width 64 $2\pc[63:0]
-  attribute \src "libresoc.v:196138.3-196166.6"
+  attribute \src "libresoc.v:196146.3-196174.6"
   wire $2\pc_changed$next[0:0]$13701
-  attribute \src "libresoc.v:196109.3-196137.6"
+  attribute \src "libresoc.v:196117.3-196145.6"
   wire $2\sv_changed$next[0:0]$13695
-  attribute \src "libresoc.v:196976.3-196994.6"
+  attribute \src "libresoc.v:196984.3-197002.6"
   wire $2\svp64_bigendian[0:0]
-  attribute \src "libresoc.v:196957.3-196975.6"
+  attribute \src "libresoc.v:196965.3-196983.6"
   wire width 32 $2\svp64_raw_opcode_in[31:0]
-  attribute \src "libresoc.v:196523.3-196538.6"
+  attribute \src "libresoc.v:196531.3-196546.6"
   wire width 64 $2\svstate[63:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $3\core_asmcode$next[7:0]$14056
-  attribute \src "libresoc.v:195942.3-195974.6"
+  attribute \src "libresoc.v:195950.3-195982.6"
   wire $3\core_bigendian_i$10$next[0:0]$13671
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 64 $3\core_core_core_cia$next[63:0]$14057
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $3\core_core_core_cr_rd$next[7:0]$14058
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_core_cr_rd_ok$next[0:0]$14059
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $3\core_core_core_cr_wr$next[7:0]$14060
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_core_exc_$signal$3$next[0:0]$14061
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_core_exc_$signal$4$next[0:0]$14062
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_core_exc_$signal$5$next[0:0]$14063
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_core_exc_$signal$6$next[0:0]$14064
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_core_exc_$signal$7$next[0:0]$14065
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_core_exc_$signal$8$next[0:0]$14066
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_core_exc_$signal$9$next[0:0]$14067
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_core_exc_$signal$next[0:0]$14068
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 13 $3\core_core_core_fn_unit$next[12:0]$14069
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 2 $3\core_core_core_input_carry$next[1:0]$14070
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 32 $3\core_core_core_insn$next[31:0]$14071
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $3\core_core_core_insn_type$next[6:0]$14072
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_core_is_32bit$next[0:0]$14073
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 64 $3\core_core_core_msr$next[63:0]$14074
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_core_oe$next[0:0]$14075
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_core_oe_ok$next[0:0]$14076
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_core_rc$next[0:0]$14077
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_core_rc_ok$next[0:0]$14078
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 13 $3\core_core_core_trapaddr$next[12:0]$14079
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $3\core_core_core_traptype$next[7:0]$14080
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $3\core_core_cr_in1$next[6:0]$14081
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_cr_in1_ok$next[0:0]$14082
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $3\core_core_cr_in2$1$next[6:0]$14083
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $3\core_core_cr_in2$next[6:0]$14084
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_cr_in2_ok$2$next[0:0]$14085
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_cr_in2_ok$next[0:0]$14086
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $3\core_core_cr_out$next[6:0]$14087
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_cr_wr_ok$next[0:0]$14088
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $3\core_core_dststep$next[6:0]$13650
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $3\core_core_ea$next[6:0]$14089
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $3\core_core_fast1$next[2:0]$14090
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_fast1_ok$next[0:0]$14091
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $3\core_core_fast2$next[2:0]$14092
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_fast2_ok$next[0:0]$14093
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $3\core_core_fasto1$next[2:0]$14094
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $3\core_core_fasto2$next[2:0]$14095
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_lk$next[0:0]$14096
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $3\core_core_maxvl$next[6:0]$13651
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 64 $3\core_core_pc$next[63:0]$13652
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $3\core_core_reg1$next[6:0]$14097
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_reg1_ok$next[0:0]$14098
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $3\core_core_reg2$next[6:0]$14099
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_reg2_ok$next[0:0]$14100
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $3\core_core_reg3$next[6:0]$14101
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_reg3_ok$next[0:0]$14102
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $3\core_core_rego$next[6:0]$14103
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 10 $3\core_core_spr1$next[9:0]$14104
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_core_spr1_ok$next[0:0]$14105
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 10 $3\core_core_spro$next[9:0]$14106
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $3\core_core_srcstep$next[6:0]$13653
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 2 $3\core_core_subvl$next[1:0]$13654
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 2 $3\core_core_svstep$next[1:0]$13655
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 7 $3\core_core_vl$next[6:0]$13656
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $3\core_core_xer_in$next[2:0]$14107
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_cr_out_ok$next[0:0]$14108
-  attribute \src "libresoc.v:196587.3-196612.6"
+  attribute \src "libresoc.v:196595.3-196620.6"
   wire width 64 $3\core_data_i[63:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 64 $3\core_dec$next[63:0]$13657
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_ea_ok$next[0:0]$14109
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire $3\core_eint$next[0:0]$13658
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_fasto1_ok$next[0:0]$14110
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_fasto2_ok$next[0:0]$14111
-  attribute \src "libresoc.v:196033.3-196057.6"
+  attribute \src "libresoc.v:196041.3-196065.6"
   wire $3\core_ivalid_i[0:0]
-  attribute \src "libresoc.v:195868.3-195908.6"
+  attribute \src "libresoc.v:195876.3-195916.6"
   wire width 64 $3\core_msr$next[63:0]$13659
-  attribute \src "libresoc.v:195909.3-195941.6"
+  attribute \src "libresoc.v:195917.3-195949.6"
   wire width 32 $3\core_raw_insn_i$next[31:0]$13664
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_rego_ok$next[0:0]$14112
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_spro_ok$next[0:0]$14113
-  attribute \src "libresoc.v:197161.3-197191.6"
+  attribute \src "libresoc.v:197169.3-197199.6"
   wire $3\core_stopped_i[0:0]
-  attribute \src "libresoc.v:196561.3-196586.6"
+  attribute \src "libresoc.v:196569.3-196594.6"
   wire width 3 $3\core_wen[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $3\core_xer_out$next[0:0]$14114
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $3\cur_cur_dststep$next[6:0]$13792
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $3\cur_cur_maxvl$next[6:0]$13793
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 2 $3\cur_cur_subvl$next[1:0]$13794
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 2 $3\cur_cur_svstep$next[1:0]$13795
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $3\cur_cur_vl$next[6:0]$13796
-  attribute \src "libresoc.v:197192.3-197222.6"
+  attribute \src "libresoc.v:197200.3-197230.6"
   wire $3\dbg_core_stopped_i[0:0]
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $3\dec2_cur_cur_srcstep$next[6:0]$13797
-  attribute \src "libresoc.v:196936.3-196956.6"
+  attribute \src "libresoc.v:196944.3-196964.6"
   wire width 64 $3\dec2_cur_msr$next[63:0]$13826
-  attribute \src "libresoc.v:196775.3-196795.6"
+  attribute \src "libresoc.v:196783.3-196803.6"
   wire width 64 $3\dec2_cur_pc$next[63:0]$13772
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 9 $3\dec2_dec_svp64__extra$next[8:0]$13851
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 2 $3\dec_svp64__elwidth$next[1:0]$13852
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 2 $3\dec_svp64__ewsrc$next[1:0]$13853
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 3 $3\dec_svp64__mask$next[2:0]$13854
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire $3\dec_svp64__mmode$next[0:0]$13855
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 5 $3\dec_svp64__mode$next[4:0]$13856
-  attribute \src "libresoc.v:196995.3-197032.6"
+  attribute \src "libresoc.v:197003.3-197040.6"
   wire width 2 $3\dec_svp64__subvl$next[1:0]$13857
-  attribute \src "libresoc.v:196074.3-196108.6"
+  attribute \src "libresoc.v:196082.3-196116.6"
   wire $3\exec_fsm_state$next[0:0]$13689
-  attribute \src "libresoc.v:196874.3-196935.6"
+  attribute \src "libresoc.v:196882.3-196943.6"
   wire width 2 $3\fetch_fsm_state$next[1:0]$13817
-  attribute \src "libresoc.v:197052.3-197087.6"
+  attribute \src "libresoc.v:197060.3-197095.6"
   wire width 32 $3\fetch_insn_o[31:0]
-  attribute \src "libresoc.v:196649.3-196684.6"
+  attribute \src "libresoc.v:196657.3-196692.6"
   wire width 48 $3\imem_a_pc_i[47:0]
-  attribute \src "libresoc.v:196685.3-196729.6"
+  attribute \src "libresoc.v:196693.3-196737.6"
   wire $3\imem_a_valid_i[0:0]
-  attribute \src "libresoc.v:196730.3-196774.6"
+  attribute \src "libresoc.v:196738.3-196782.6"
   wire $3\imem_f_valid_i[0:0]
-  attribute \src "libresoc.v:197099.3-197160.6"
+  attribute \src "libresoc.v:197107.3-197168.6"
   wire width 3 $3\issue_fsm_state$next[2:0]$13868
-  attribute \src "libresoc.v:196844.3-196873.6"
+  attribute \src "libresoc.v:196852.3-196881.6"
   wire $3\msr_read$next[0:0]$13811
-  attribute \src "libresoc.v:196138.3-196166.6"
+  attribute \src "libresoc.v:196146.3-196174.6"
   wire $3\pc_changed$next[0:0]$13702
-  attribute \src "libresoc.v:196109.3-196137.6"
+  attribute \src "libresoc.v:196117.3-196145.6"
   wire $3\sv_changed$next[0:0]$13696
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $4\core_asmcode$next[7:0]$14115
-  attribute \src "libresoc.v:195942.3-195974.6"
+  attribute \src "libresoc.v:195950.3-195982.6"
   wire $4\core_bigendian_i$10$next[0:0]$13672
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 64 $4\core_core_core_cia$next[63:0]$14116
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $4\core_core_core_cr_rd$next[7:0]$14117
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_core_cr_rd_ok$next[0:0]$14118
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $4\core_core_core_cr_wr$next[7:0]$14119
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_core_exc_$signal$3$next[0:0]$14120
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_core_exc_$signal$4$next[0:0]$14121
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_core_exc_$signal$5$next[0:0]$14122
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_core_exc_$signal$6$next[0:0]$14123
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_core_exc_$signal$7$next[0:0]$14124
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_core_exc_$signal$8$next[0:0]$14125
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_core_exc_$signal$9$next[0:0]$14126
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_core_exc_$signal$next[0:0]$14127
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 13 $4\core_core_core_fn_unit$next[12:0]$14128
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 2 $4\core_core_core_input_carry$next[1:0]$14129
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 32 $4\core_core_core_insn$next[31:0]$14130
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $4\core_core_core_insn_type$next[6:0]$14131
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_core_is_32bit$next[0:0]$14132
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 64 $4\core_core_core_msr$next[63:0]$14133
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_core_oe$next[0:0]$14134
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_core_oe_ok$next[0:0]$14135
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_core_rc$next[0:0]$14136
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_core_rc_ok$next[0:0]$14137
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 13 $4\core_core_core_trapaddr$next[12:0]$14138
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 8 $4\core_core_core_traptype$next[7:0]$14139
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $4\core_core_cr_in1$next[6:0]$14140
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_cr_in1_ok$next[0:0]$14141
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $4\core_core_cr_in2$1$next[6:0]$14142
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $4\core_core_cr_in2$next[6:0]$14143
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_cr_in2_ok$2$next[0:0]$14144
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_cr_in2_ok$next[0:0]$14145
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $4\core_core_cr_out$next[6:0]$14146
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_cr_wr_ok$next[0:0]$14147
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $4\core_core_ea$next[6:0]$14148
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $4\core_core_fast1$next[2:0]$14149
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_fast1_ok$next[0:0]$14150
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $4\core_core_fast2$next[2:0]$14151
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_fast2_ok$next[0:0]$14152
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $4\core_core_fasto1$next[2:0]$14153
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $4\core_core_fasto2$next[2:0]$14154
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_lk$next[0:0]$14155
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $4\core_core_reg1$next[6:0]$14156
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_reg1_ok$next[0:0]$14157
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $4\core_core_reg2$next[6:0]$14158
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_reg2_ok$next[0:0]$14159
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $4\core_core_reg3$next[6:0]$14160
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_reg3_ok$next[0:0]$14161
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 7 $4\core_core_rego$next[6:0]$14162
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 10 $4\core_core_spr1$next[9:0]$14163
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_core_spr1_ok$next[0:0]$14164
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 10 $4\core_core_spro$next[9:0]$14165
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire width 3 $4\core_core_xer_in$next[2:0]$14166
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_cr_out_ok$next[0:0]$14167
-  attribute \src "libresoc.v:196587.3-196612.6"
+  attribute \src "libresoc.v:196595.3-196620.6"
   wire width 64 $4\core_data_i[63:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_ea_ok$next[0:0]$14168
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_fasto1_ok$next[0:0]$14169
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_fasto2_ok$next[0:0]$14170
-  attribute \src "libresoc.v:195909.3-195941.6"
+  attribute \src "libresoc.v:195917.3-195949.6"
   wire width 32 $4\core_raw_insn_i$next[31:0]$13665
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_rego_ok$next[0:0]$14171
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_spro_ok$next[0:0]$14172
-  attribute \src "libresoc.v:196561.3-196586.6"
+  attribute \src "libresoc.v:196569.3-196594.6"
   wire width 3 $4\core_wen[2:0]
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $4\core_xer_out$next[0:0]$14173
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $4\cur_cur_dststep$next[6:0]$13798
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $4\cur_cur_maxvl$next[6:0]$13799
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 2 $4\cur_cur_subvl$next[1:0]$13800
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 2 $4\cur_cur_svstep$next[1:0]$13801
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $4\cur_cur_vl$next[6:0]$13802
-  attribute \src "libresoc.v:196796.3-196834.6"
+  attribute \src "libresoc.v:196804.3-196842.6"
   wire width 7 $4\dec2_cur_cur_srcstep$next[6:0]$13803
-  attribute \src "libresoc.v:196074.3-196108.6"
+  attribute \src "libresoc.v:196082.3-196116.6"
   wire $4\exec_fsm_state$next[0:0]$13690
-  attribute \src "libresoc.v:196874.3-196935.6"
+  attribute \src "libresoc.v:196882.3-196943.6"
   wire width 2 $4\fetch_fsm_state$next[1:0]$13818
-  attribute \src "libresoc.v:197052.3-197087.6"
+  attribute \src "libresoc.v:197060.3-197095.6"
   wire width 32 $4\fetch_insn_o[31:0]
-  attribute \src "libresoc.v:196649.3-196684.6"
+  attribute \src "libresoc.v:196657.3-196692.6"
   wire width 48 $4\imem_a_pc_i[47:0]
-  attribute \src "libresoc.v:196685.3-196729.6"
+  attribute \src "libresoc.v:196693.3-196737.6"
   wire $4\imem_a_valid_i[0:0]
-  attribute \src "libresoc.v:196730.3-196774.6"
+  attribute \src "libresoc.v:196738.3-196782.6"
   wire $4\imem_f_valid_i[0:0]
-  attribute \src "libresoc.v:197099.3-197160.6"
+  attribute \src "libresoc.v:197107.3-197168.6"
   wire width 3 $4\issue_fsm_state$next[2:0]$13869
-  attribute \src "libresoc.v:196844.3-196873.6"
+  attribute \src "libresoc.v:196852.3-196881.6"
   wire $4\msr_read$next[0:0]$13812
-  attribute \src "libresoc.v:196138.3-196166.6"
+  attribute \src "libresoc.v:196146.3-196174.6"
   wire $4\pc_changed$next[0:0]$13703
-  attribute \src "libresoc.v:196109.3-196137.6"
+  attribute \src "libresoc.v:196117.3-196145.6"
   wire $4\sv_changed$next[0:0]$13697
-  attribute \src "libresoc.v:195942.3-195974.6"
+  attribute \src "libresoc.v:195950.3-195982.6"
   wire $5\core_bigendian_i$10$next[0:0]$13673
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_core_cr_rd_ok$next[0:0]$14174
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_core_exc_$signal$3$next[0:0]$14175
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_core_exc_$signal$4$next[0:0]$14176
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_core_exc_$signal$5$next[0:0]$14177
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_core_exc_$signal$6$next[0:0]$14178
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_core_exc_$signal$7$next[0:0]$14179
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_core_exc_$signal$8$next[0:0]$14180
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_core_exc_$signal$9$next[0:0]$14181
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_core_exc_$signal$next[0:0]$14182
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_core_oe_ok$next[0:0]$14183
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_core_rc_ok$next[0:0]$14184
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_cr_in1_ok$next[0:0]$14185
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_cr_in2_ok$2$next[0:0]$14186
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_cr_in2_ok$next[0:0]$14187
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_cr_wr_ok$next[0:0]$14188
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_fast1_ok$next[0:0]$14189
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_fast2_ok$next[0:0]$14190
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_reg1_ok$next[0:0]$14191
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_reg2_ok$next[0:0]$14192
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_reg3_ok$next[0:0]$14193
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_core_spr1_ok$next[0:0]$14194
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_cr_out_ok$next[0:0]$14195
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_ea_ok$next[0:0]$14196
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_fasto1_ok$next[0:0]$14197
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_fasto2_ok$next[0:0]$14198
-  attribute \src "libresoc.v:195909.3-195941.6"
+  attribute \src "libresoc.v:195917.3-195949.6"
   wire width 32 $5\core_raw_insn_i$next[31:0]$13666
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_rego_ok$next[0:0]$14199
-  attribute \src "libresoc.v:197245.3-197363.6"
+  attribute \src "libresoc.v:197253.3-197371.6"
   wire $5\core_spro_ok$next[0:0]$14200
-  attribute \src "libresoc.v:196074.3-196108.6"
+  attribute \src "libresoc.v:196082.3-196116.6"
   wire $5\exec_fsm_state$next[0:0]$13691
-  attribute \src "libresoc.v:196874.3-196935.6"
+  attribute \src "libresoc.v:196882.3-196943.6"
   wire width 2 $5\fetch_fsm_state$next[1:0]$13819
-  attribute \src "libresoc.v:196685.3-196729.6"
+  attribute \src "libresoc.v:196693.3-196737.6"
   wire $5\imem_a_valid_i[0:0]
-  attribute \src "libresoc.v:196730.3-196774.6"
+  attribute \src "libresoc.v:196738.3-196782.6"
   wire $5\imem_f_valid_i[0:0]
-  attribute \src "libresoc.v:197099.3-197160.6"
+  attribute \src "libresoc.v:197107.3-197168.6"
   wire width 3 $5\issue_fsm_state$next[2:0]$13870
-  attribute \src "libresoc.v:196874.3-196935.6"
+  attribute \src "libresoc.v:196882.3-196943.6"
   wire width 2 $6\fetch_fsm_state$next[1:0]$13820
-  attribute \src "libresoc.v:197099.3-197160.6"
+  attribute \src "libresoc.v:197107.3-197168.6"
   wire width 3 $6\issue_fsm_state$next[2:0]$13871
-  attribute \src "libresoc.v:196874.3-196935.6"
+  attribute \src "libresoc.v:196882.3-196943.6"
   wire width 2 $7\fetch_fsm_state$next[1:0]$13821
-  attribute \src "libresoc.v:197099.3-197160.6"
+  attribute \src "libresoc.v:197107.3-197168.6"
   wire width 3 $7\issue_fsm_state$next[2:0]$13872
-  attribute \src "libresoc.v:197099.3-197160.6"
+  attribute \src "libresoc.v:197107.3-197168.6"
   wire width 3 $8\issue_fsm_state$next[2:0]$13873
+  attribute \src "libresoc.v:194952.19-194952.115"
+  wire width 65 $add$libresoc.v:194952$13448_Y
+  attribute \src "libresoc.v:194972.18-194972.107"
+  wire width 65 $add$libresoc.v:194972$13469_Y
+  attribute \src "libresoc.v:194981.18-194981.107"
+  wire width 65 $add$libresoc.v:194981$13478_Y
+  attribute \src "libresoc.v:194985.18-194985.107"
+  wire width 65 $add$libresoc.v:194985$13482_Y
+  attribute \src "libresoc.v:194916.19-194916.102"
+  wire $and$libresoc.v:194916$13410_Y
+  attribute \src "libresoc.v:194919.19-194919.104"
+  wire $and$libresoc.v:194919$13413_Y
+  attribute \src "libresoc.v:194922.19-194922.104"
+  wire $and$libresoc.v:194922$13416_Y
+  attribute \src "libresoc.v:194925.19-194925.104"
+  wire $and$libresoc.v:194925$13419_Y
+  attribute \src "libresoc.v:194928.19-194928.104"
+  wire $and$libresoc.v:194928$13422_Y
+  attribute \src "libresoc.v:194931.19-194931.104"
+  wire $and$libresoc.v:194931$13425_Y
+  attribute \src "libresoc.v:194937.19-194937.104"
+  wire $and$libresoc.v:194937$13431_Y
+  attribute \src "libresoc.v:194941.19-194941.115"
+  wire width 3 $and$libresoc.v:194941$13435_Y
   attribute \src "libresoc.v:194944.19-194944.115"
-  wire width 65 $add$libresoc.v:194944$13448_Y
-  attribute \src "libresoc.v:194964.18-194964.107"
-  wire width 65 $add$libresoc.v:194964$13469_Y
-  attribute \src "libresoc.v:194973.18-194973.107"
-  wire width 65 $add$libresoc.v:194973$13478_Y
-  attribute \src "libresoc.v:194977.18-194977.107"
-  wire width 65 $add$libresoc.v:194977$13482_Y
-  attribute \src "libresoc.v:194908.19-194908.102"
-  wire $and$libresoc.v:194908$13410_Y
-  attribute \src "libresoc.v:194911.19-194911.104"
-  wire $and$libresoc.v:194911$13413_Y
-  attribute \src "libresoc.v:194914.19-194914.104"
-  wire $and$libresoc.v:194914$13416_Y
-  attribute \src "libresoc.v:194917.19-194917.104"
-  wire $and$libresoc.v:194917$13419_Y
-  attribute \src "libresoc.v:194920.19-194920.104"
-  wire $and$libresoc.v:194920$13422_Y
-  attribute \src "libresoc.v:194923.19-194923.104"
-  wire $and$libresoc.v:194923$13425_Y
-  attribute \src "libresoc.v:194929.19-194929.104"
-  wire $and$libresoc.v:194929$13431_Y
-  attribute \src "libresoc.v:194933.19-194933.115"
-  wire width 3 $and$libresoc.v:194933$13435_Y
-  attribute \src "libresoc.v:194936.19-194936.115"
-  wire width 3 $and$libresoc.v:194936$13438_Y
-  attribute \src "libresoc.v:194951.18-194951.109"
-  wire $and$libresoc.v:194951$13455_Y
-  attribute \src "libresoc.v:194957.18-194957.101"
-  wire $and$libresoc.v:194957$13462_Y
-  attribute \src "libresoc.v:194961.18-194961.101"
-  wire $and$libresoc.v:194961$13466_Y
-  attribute \src "libresoc.v:194941.19-194941.114"
-  wire width 64 $extend$libresoc.v:194941$13443_Y
-  attribute \src "libresoc.v:194942.19-194942.113"
-  wire width 64 $extend$libresoc.v:194942$13445_Y
-  attribute \src "libresoc.v:194954.18-194954.109"
-  wire width 64 $extend$libresoc.v:194954$13458_Y
-  attribute \src "libresoc.v:194970.18-194970.110"
-  wire width 7 $mul$libresoc.v:194970$13475_Y
-  attribute \src "libresoc.v:194975.18-194975.110"
-  wire width 7 $mul$libresoc.v:194975$13480_Y
-  attribute \src "libresoc.v:194978.18-194978.104"
-  wire width 7 $mul$libresoc.v:194978$13483_Y
-  attribute \src "libresoc.v:194931.19-194931.123"
-  wire $ne$libresoc.v:194931$13433_Y
-  attribute \src "libresoc.v:194945.18-194945.102"
-  wire $ne$libresoc.v:194945$13449_Y
-  attribute \src "libresoc.v:194949.18-194949.102"
-  wire $ne$libresoc.v:194949$13453_Y
-  attribute \src "libresoc.v:194907.18-194907.108"
-  wire $not$libresoc.v:194907$13409_Y
-  attribute \src "libresoc.v:194909.19-194909.107"
-  wire $not$libresoc.v:194909$13411_Y
-  attribute \src "libresoc.v:194910.19-194910.109"
-  wire $not$libresoc.v:194910$13412_Y
-  attribute \src "libresoc.v:194912.19-194912.107"
-  wire $not$libresoc.v:194912$13414_Y
-  attribute \src "libresoc.v:194913.19-194913.109"
-  wire $not$libresoc.v:194913$13415_Y
-  attribute \src "libresoc.v:194915.19-194915.107"
-  wire $not$libresoc.v:194915$13417_Y
-  attribute \src "libresoc.v:194916.19-194916.109"
-  wire $not$libresoc.v:194916$13418_Y
-  attribute \src "libresoc.v:194918.19-194918.107"
-  wire $not$libresoc.v:194918$13420_Y
-  attribute \src "libresoc.v:194919.19-194919.109"
-  wire $not$libresoc.v:194919$13421_Y
-  attribute \src "libresoc.v:194921.19-194921.107"
-  wire $not$libresoc.v:194921$13423_Y
-  attribute \src "libresoc.v:194922.19-194922.109"
-  wire $not$libresoc.v:194922$13424_Y
-  attribute \src "libresoc.v:194924.19-194924.107"
-  wire $not$libresoc.v:194924$13426_Y
-  attribute \src "libresoc.v:194925.19-194925.107"
-  wire $not$libresoc.v:194925$13427_Y
+  wire width 3 $and$libresoc.v:194944$13438_Y
+  attribute \src "libresoc.v:194959.18-194959.109"
+  wire $and$libresoc.v:194959$13455_Y
+  attribute \src "libresoc.v:194965.18-194965.101"
+  wire $and$libresoc.v:194965$13462_Y
+  attribute \src "libresoc.v:194969.18-194969.101"
+  wire $and$libresoc.v:194969$13466_Y
+  attribute \src "libresoc.v:194949.19-194949.114"
+  wire width 64 $extend$libresoc.v:194949$13443_Y
+  attribute \src "libresoc.v:194950.19-194950.113"
+  wire width 64 $extend$libresoc.v:194950$13445_Y
+  attribute \src "libresoc.v:194962.18-194962.109"
+  wire width 64 $extend$libresoc.v:194962$13458_Y
+  attribute \src "libresoc.v:194978.18-194978.110"
+  wire width 7 $mul$libresoc.v:194978$13475_Y
+  attribute \src "libresoc.v:194983.18-194983.110"
+  wire width 7 $mul$libresoc.v:194983$13480_Y
+  attribute \src "libresoc.v:194986.18-194986.104"
+  wire width 7 $mul$libresoc.v:194986$13483_Y
+  attribute \src "libresoc.v:194939.19-194939.123"
+  wire $ne$libresoc.v:194939$13433_Y
+  attribute \src "libresoc.v:194953.18-194953.102"
+  wire $ne$libresoc.v:194953$13449_Y
+  attribute \src "libresoc.v:194957.18-194957.102"
+  wire $ne$libresoc.v:194957$13453_Y
+  attribute \src "libresoc.v:194915.18-194915.108"
+  wire $not$libresoc.v:194915$13409_Y
+  attribute \src "libresoc.v:194917.19-194917.107"
+  wire $not$libresoc.v:194917$13411_Y
+  attribute \src "libresoc.v:194918.19-194918.109"
+  wire $not$libresoc.v:194918$13412_Y
+  attribute \src "libresoc.v:194920.19-194920.107"
+  wire $not$libresoc.v:194920$13414_Y
+  attribute \src "libresoc.v:194921.19-194921.109"
+  wire $not$libresoc.v:194921$13415_Y
+  attribute \src "libresoc.v:194923.19-194923.107"
+  wire $not$libresoc.v:194923$13417_Y
+  attribute \src "libresoc.v:194924.19-194924.109"
+  wire $not$libresoc.v:194924$13418_Y
   attribute \src "libresoc.v:194926.19-194926.107"
-  wire $not$libresoc.v:194926$13428_Y
-  attribute \src "libresoc.v:194927.19-194927.107"
-  wire $not$libresoc.v:194927$13429_Y
-  attribute \src "libresoc.v:194928.19-194928.109"
-  wire $not$libresoc.v:194928$13430_Y
+  wire $not$libresoc.v:194926$13420_Y
+  attribute \src "libresoc.v:194927.19-194927.109"
+  wire $not$libresoc.v:194927$13421_Y
+  attribute \src "libresoc.v:194929.19-194929.107"
+  wire $not$libresoc.v:194929$13423_Y
+  attribute \src "libresoc.v:194930.19-194930.109"
+  wire $not$libresoc.v:194930$13424_Y
   attribute \src "libresoc.v:194932.19-194932.107"
-  wire $not$libresoc.v:194932$13434_Y
+  wire $not$libresoc.v:194932$13426_Y
+  attribute \src "libresoc.v:194933.19-194933.107"
+  wire $not$libresoc.v:194933$13427_Y
+  attribute \src "libresoc.v:194934.19-194934.107"
+  wire $not$libresoc.v:194934$13428_Y
   attribute \src "libresoc.v:194935.19-194935.107"
-  wire $not$libresoc.v:194935$13437_Y
-  attribute \src "libresoc.v:194938.19-194938.107"
-  wire $not$libresoc.v:194938$13440_Y
-  attribute \src "libresoc.v:194939.19-194939.107"
-  wire $not$libresoc.v:194939$13441_Y
+  wire $not$libresoc.v:194935$13429_Y
+  attribute \src "libresoc.v:194936.19-194936.109"
+  wire $not$libresoc.v:194936$13430_Y
   attribute \src "libresoc.v:194940.19-194940.107"
-  wire $not$libresoc.v:194940$13442_Y
-  attribute \src "libresoc.v:194950.18-194950.103"
-  wire $not$libresoc.v:194950$13454_Y
-  attribute \src "libresoc.v:194952.18-194952.98"
-  wire $not$libresoc.v:194952$13456_Y
-  attribute \src "libresoc.v:194953.18-194953.103"
-  wire $not$libresoc.v:194953$13457_Y
-  attribute \src "libresoc.v:194955.18-194955.106"
-  wire $not$libresoc.v:194955$13460_Y
-  attribute \src "libresoc.v:194956.18-194956.108"
-  wire $not$libresoc.v:194956$13461_Y
-  attribute \src "libresoc.v:194958.18-194958.101"
-  wire $not$libresoc.v:194958$13463_Y
-  attribute \src "libresoc.v:194959.18-194959.106"
-  wire $not$libresoc.v:194959$13464_Y
-  attribute \src "libresoc.v:194960.18-194960.108"
-  wire $not$libresoc.v:194960$13465_Y
-  attribute \src "libresoc.v:194962.18-194962.101"
-  wire $not$libresoc.v:194962$13467_Y
-  attribute \src "libresoc.v:194963.18-194963.110"
-  wire $not$libresoc.v:194963$13468_Y
-  attribute \src "libresoc.v:194965.18-194965.110"
-  wire $not$libresoc.v:194965$13470_Y
-  attribute \src "libresoc.v:194966.18-194966.110"
-  wire $not$libresoc.v:194966$13471_Y
-  attribute \src "libresoc.v:194967.18-194967.99"
-  wire $not$libresoc.v:194967$13472_Y
-  attribute \src "libresoc.v:194968.18-194968.110"
-  wire $not$libresoc.v:194968$13473_Y
-  attribute \src "libresoc.v:194969.18-194969.99"
-  wire $not$libresoc.v:194969$13474_Y
+  wire $not$libresoc.v:194940$13434_Y
+  attribute \src "libresoc.v:194943.19-194943.107"
+  wire $not$libresoc.v:194943$13437_Y
+  attribute \src "libresoc.v:194946.19-194946.107"
+  wire $not$libresoc.v:194946$13440_Y
+  attribute \src "libresoc.v:194947.19-194947.107"
+  wire $not$libresoc.v:194947$13441_Y
+  attribute \src "libresoc.v:194948.19-194948.107"
+  wire $not$libresoc.v:194948$13442_Y
+  attribute \src "libresoc.v:194958.18-194958.103"
+  wire $not$libresoc.v:194958$13454_Y
+  attribute \src "libresoc.v:194960.18-194960.98"
+  wire $not$libresoc.v:194960$13456_Y
+  attribute \src "libresoc.v:194961.18-194961.103"
+  wire $not$libresoc.v:194961$13457_Y
+  attribute \src "libresoc.v:194963.18-194963.106"
+  wire $not$libresoc.v:194963$13460_Y
+  attribute \src "libresoc.v:194964.18-194964.108"
+  wire $not$libresoc.v:194964$13461_Y
+  attribute \src "libresoc.v:194966.18-194966.101"
+  wire $not$libresoc.v:194966$13463_Y
+  attribute \src "libresoc.v:194967.18-194967.106"
+  wire $not$libresoc.v:194967$13464_Y
+  attribute \src "libresoc.v:194968.18-194968.108"
+  wire $not$libresoc.v:194968$13465_Y
+  attribute \src "libresoc.v:194970.18-194970.101"
+  wire $not$libresoc.v:194970$13467_Y
+  attribute \src "libresoc.v:194971.18-194971.110"
+  wire $not$libresoc.v:194971$13468_Y
+  attribute \src "libresoc.v:194973.18-194973.110"
+  wire $not$libresoc.v:194973$13470_Y
   attribute \src "libresoc.v:194974.18-194974.110"
-  wire $not$libresoc.v:194974$13479_Y
-  attribute \src "libresoc.v:194980.18-194980.106"
-  wire $not$libresoc.v:194980$13485_Y
-  attribute \src "libresoc.v:194947.18-194947.110"
-  wire $or$libresoc.v:194947$13451_Y
-  attribute \src "libresoc.v:194948.18-194948.100"
-  wire $or$libresoc.v:194948$13452_Y
-  attribute \src "libresoc.v:194930.19-194930.211"
-  wire width 64 $pos$libresoc.v:194930$13432_Y
-  attribute \src "libresoc.v:194941.19-194941.114"
-  wire width 64 $pos$libresoc.v:194941$13444_Y
-  attribute \src "libresoc.v:194942.19-194942.113"
-  wire width 64 $pos$libresoc.v:194942$13446_Y
-  attribute \src "libresoc.v:194954.18-194954.109"
-  wire width 64 $pos$libresoc.v:194954$13459_Y
-  attribute \src "libresoc.v:194934.19-194934.93"
-  wire $reduce_or$libresoc.v:194934$13436_Y
-  attribute \src "libresoc.v:194937.19-194937.93"
-  wire $reduce_or$libresoc.v:194937$13439_Y
-  attribute \src "libresoc.v:194971.18-194971.40"
-  wire width 64 $shr$libresoc.v:194971$13476_Y
-  attribute \src "libresoc.v:194976.18-194976.40"
-  wire width 64 $shr$libresoc.v:194976$13481_Y
+  wire $not$libresoc.v:194974$13471_Y
+  attribute \src "libresoc.v:194975.18-194975.99"
+  wire $not$libresoc.v:194975$13472_Y
+  attribute \src "libresoc.v:194976.18-194976.110"
+  wire $not$libresoc.v:194976$13473_Y
+  attribute \src "libresoc.v:194977.18-194977.99"
+  wire $not$libresoc.v:194977$13474_Y
+  attribute \src "libresoc.v:194982.18-194982.110"
+  wire $not$libresoc.v:194982$13479_Y
+  attribute \src "libresoc.v:194988.18-194988.106"
+  wire $not$libresoc.v:194988$13485_Y
+  attribute \src "libresoc.v:194955.18-194955.110"
+  wire $or$libresoc.v:194955$13451_Y
+  attribute \src "libresoc.v:194956.18-194956.100"
+  wire $or$libresoc.v:194956$13452_Y
+  attribute \src "libresoc.v:194938.19-194938.211"
+  wire width 64 $pos$libresoc.v:194938$13432_Y
+  attribute \src "libresoc.v:194949.19-194949.114"
+  wire width 64 $pos$libresoc.v:194949$13444_Y
+  attribute \src "libresoc.v:194950.19-194950.113"
+  wire width 64 $pos$libresoc.v:194950$13446_Y
+  attribute \src "libresoc.v:194962.18-194962.109"
+  wire width 64 $pos$libresoc.v:194962$13459_Y
+  attribute \src "libresoc.v:194942.19-194942.93"
+  wire $reduce_or$libresoc.v:194942$13436_Y
+  attribute \src "libresoc.v:194945.19-194945.93"
+  wire $reduce_or$libresoc.v:194945$13439_Y
   attribute \src "libresoc.v:194979.18-194979.40"
-  wire width 64 $shr$libresoc.v:194979$13484_Y
-  attribute \src "libresoc.v:194943.19-194943.115"
-  wire width 65 $sub$libresoc.v:194943$13447_Y
-  attribute \src "libresoc.v:194946.18-194946.101"
-  wire width 3 $sub$libresoc.v:194946$13450_Y
-  attribute \src "libresoc.v:194972.18-194972.122"
-  wire width 4 $ternary$libresoc.v:194972$13477_Y
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+  wire width 64 $shr$libresoc.v:194979$13476_Y
+  attribute \src "libresoc.v:194984.18-194984.40"
+  wire width 64 $shr$libresoc.v:194984$13481_Y
+  attribute \src "libresoc.v:194987.18-194987.40"
+  wire width 64 $shr$libresoc.v:194987$13484_Y
+  attribute \src "libresoc.v:194951.19-194951.115"
+  wire width 65 $sub$libresoc.v:194951$13447_Y
+  attribute \src "libresoc.v:194954.18-194954.101"
+  wire width 3 $sub$libresoc.v:194954$13450_Y
+  attribute \src "libresoc.v:194980.18-194980.122"
+  wire width 4 $ternary$libresoc.v:194980$13477_Y
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
   wire \$101
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
   wire \$109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
   wire \$111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
   wire \$113
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$115
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$117
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$119
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
   wire \$121
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
   wire \$123
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
   wire \$125
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$127
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$129
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$131
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
   wire \$133
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
   wire \$135
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
   wire \$137
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$139
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$141
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$143
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 64 \$145
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:379"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380"
   wire \$147
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
   wire \$149
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
   wire \$151
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:382"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:383"
   wire width 3 \$152
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
   wire \$155
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
   wire \$157
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:384"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385"
   wire width 3 \$158
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
   wire \$161
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
   wire \$163
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
   wire \$165
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 64 \$167
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 64 \$169
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:638"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
   wire width 65 \$171
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:638"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
   wire width 65 \$172
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655"
   wire width 65 \$174
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655"
   wire width 65 \$175
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:452"
-  wire \$23
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:453"
+  wire \$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454"
   wire width 3 \$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:453"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454"
   wire width 3 \$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:459"
   wire \$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:459"
   wire \$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:459"
   wire \$32
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
   wire \$34
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
   wire \$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:481"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482"
   wire \$38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:495"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:496"
   wire \$40
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 64 \$42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:329"
   wire \$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
   wire \$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:329"
   wire \$58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
   wire \$60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222"
   wire width 65 \$62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222"
   wire width 65 \$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
   wire \$65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
   wire \$67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
   wire \$69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
   wire \$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
   wire \$73
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53"
   wire width 32 \$75
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
   wire width 7 \$76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:213"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
   wire width 65 \$79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:212"
-  wire width 4 \$80
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:213"
-  wire width 65 \$82
+  wire width 4 \$80
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
+  wire width 65 \$82
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
   wire \$84
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53"
   wire width 32 \$86
@@ -403908,15 +403916,15 @@ module \ti
   wire width 7 \$87
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53"
   wire width 32 \$90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:234"
   wire width 65 \$91
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:234"
   wire width 65 \$92
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
   wire width 7 \$94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
   wire \$97
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
   wire \$99
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
   wire input 342 \TAP_bus__tck
@@ -403926,15 +403934,15 @@ module \ti
   wire output 333 \TAP_bus__tdo
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
   wire input 343 \TAP_bus__tms
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:128"
   wire output 3 \busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 392 \clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
   wire width 8 \core_asmcode
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
   wire width 8 \core_asmcode$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:127"
   wire input 4 \core_bigendian_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:90"
   wire \core_bigendian_i$10
@@ -404500,7 +404508,7 @@ module \ti
   wire width 3 \core_core_xer_in$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:95"
   wire \core_corebusy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire \core_coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire \core_cr_out_ok
@@ -404618,7 +404626,7 @@ module \ti
   wire \core_xer_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
   wire \core_xer_out$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 2 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60"
   wire \cu_st__rel_o_dly
@@ -404646,17 +404654,17 @@ module \ti
   wire width 7 \cur_cur_vl
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30"
   wire width 7 \cur_cur_vl$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:588"
   wire \d_cr_delay
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:588"
   wire \d_cr_delay$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578"
   wire \d_reg_delay
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578"
   wire \d_reg_delay$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598"
   wire \d_xer_delay
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598"
   wire \d_xer_delay$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17"
   wire width 64 \dbg_core_dbg_msr
@@ -405220,9 +405228,9 @@ module \ti
   wire width 2 \dec_svp64__subvl
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30"
   wire width 2 \dec_svp64__subvl$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:452"
   wire width 2 \delay
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:452"
   wire width 2 \delay$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire output 179 \eint_0__core__i
@@ -405236,35 +405244,35 @@ module \ti
   wire output 181 \eint_2__core__i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire input 26 \eint_2__pad__i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
   wire \exec_fsm_state
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
   wire \exec_fsm_state$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:537"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:538"
   wire \exec_insn_ready_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:536"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:537"
   wire \exec_insn_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:541"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
   wire \exec_pc_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:540"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:541"
   wire \exec_pc_valid_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
   wire width 2 \fetch_fsm_state
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
   wire width 2 \fetch_fsm_state$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:165"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:166"
   wire width 32 \fetch_insn_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:533"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534"
   wire \fetch_insn_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:532"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:533"
   wire \fetch_insn_valid_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:529"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:530"
   wire \fetch_pc_ready_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:528"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:529"
   wire \fetch_pc_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
   wire width 2 \fsm_state
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
   wire width 2 \fsm_state$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire output 188 \gpio_e10__core__i
@@ -405514,15 +405522,15 @@ module \ti
   wire \imem_f_valid_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93"
   wire \imem_wb_icache_en
-  attribute \src "libresoc.v:192544.7-192544.15"
+  attribute \src "libresoc.v:192552.7-192552.15"
   wire \initial
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:476"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:477"
   wire \insn_done
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
   wire width 16 input 385 \int_level_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
   wire width 3 \issue_fsm_state
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
   wire width 3 \issue_fsm_state$next
   attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
   wire \jtag_dmi0__ack_o
@@ -405590,9 +405598,9 @@ module \ti
   wire input 81 \mspi1_mosi__core__o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire output 236 \mspi1_mosi__pad__o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:170"
   wire \msr_read
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:170"
   wire \msr_read$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire input 86 \mtwi_scl__core__o
@@ -405610,7 +405618,7 @@ module \ti
   wire output 239 \mtwi_sda__pad__o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire output 240 \mtwi_sda__pad__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637"
   wire width 64 \new_dec
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28"
   wire width 7 \new_svstate_dststep
@@ -405624,29 +405632,29 @@ module \ti
   wire width 2 \new_svstate_svstep
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30"
   wire width 7 \new_svstate_vl
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654"
   wire width 64 \new_tb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:516"
   wire width 64 \nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:516"
   wire width 64 \nia$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:479"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480"
   wire width 64 \pc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:474"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:475"
   wire \pc_changed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:474"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:475"
   wire \pc_changed$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 64 input 7 \pc_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire input 6 \pc_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:124"
   wire width 64 output 5 \pc_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:481"
   wire \pc_ok_delay
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:481"
   wire \pc_ok_delay$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:445"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
   wire \por_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire input 87 \pwm_0__core__o
@@ -405656,7 +405664,7 @@ module \ti
   wire input 88 \pwm_1__core__o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire output 243 \pwm_1__pad__o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 1 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
   wire input 92 \sd0_clk__core__o
@@ -406086,9 +406094,9 @@ module \ti
   wire input 369 \sram4k_3_wb__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25"
   wire input 374 \sram4k_3_wb__we
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:475"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:476"
   wire \sv_changed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:475"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:476"
   wire \sv_changed$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:21"
   wire \svp64_bigendian
@@ -406098,19 +406106,19 @@ module \ti
   wire width 32 \svp64_raw_opcode_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:20"
   wire width 24 \svp64_svp64_rm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:493"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:494"
   wire width 64 \svstate
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire width 32 \svstate_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire \svstate_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:494"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:495"
   wire \svstate_ok_delay
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:494"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:495"
   wire \svstate_ok_delay$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:450"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451"
   wire \ti_rst
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:269"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:270"
   wire \update_svstate
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
   wire \xics_icp_core_irq_o
@@ -406122,8 +406130,8 @@ module \ti
   wire width 8 \xics_ics_icp_o_pri
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
   wire width 4 \xics_ics_icp_o_src
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654"
-  cell $add $add$libresoc.v:194944$13448
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655"
+  cell $add $add$libresoc.v:194952$13448
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -406131,10 +406139,10 @@ module \ti
     parameter \Y_WIDTH 65
     connect \A \core_issue__data_o
     connect \B 1'1
-    connect \Y $add$libresoc.v:194944$13448_Y
+    connect \Y $add$libresoc.v:194952$13448_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221"
-  cell $add $add$libresoc.v:194964$13469
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222"
+  cell $add $add$libresoc.v:194972$13469
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -406142,10 +406150,10 @@ module \ti
     parameter \Y_WIDTH 65
     connect \A \dec2_cur_pc
     connect \B 3'100
-    connect \Y $add$libresoc.v:194964$13469_Y
+    connect \Y $add$libresoc.v:194972$13469_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:213"
-  cell $add $add$libresoc.v:194973$13478
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
+  cell $add $add$libresoc.v:194981$13478
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -406153,10 +406161,10 @@ module \ti
     parameter \Y_WIDTH 65
     connect \A \dec2_cur_pc
     connect \B \$80
-    connect \Y $add$libresoc.v:194973$13478_Y
+    connect \Y $add$libresoc.v:194981$13478_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233"
-  cell $add $add$libresoc.v:194977$13482
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:234"
+  cell $add $add$libresoc.v:194985$13482
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -406164,10 +406172,10 @@ module \ti
     parameter \Y_WIDTH 65
     connect \A \dec2_cur_pc
     connect \B 3'100
-    connect \Y $add$libresoc.v:194977$13482_Y
+    connect \Y $add$libresoc.v:194985$13482_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
-  cell $and $and$libresoc.v:194908$13410
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+  cell $and $and$libresoc.v:194916$13410
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406175,10 +406183,10 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A \$97
     connect \B \$99
-    connect \Y $and$libresoc.v:194908$13410_Y
+    connect \Y $and$libresoc.v:194916$13410_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $and $and$libresoc.v:194911$13413
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $and $and$libresoc.v:194919$13413
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406186,10 +406194,10 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A \$103
     connect \B \$105
-    connect \Y $and$libresoc.v:194911$13413_Y
+    connect \Y $and$libresoc.v:194919$13413_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
-  cell $and $and$libresoc.v:194914$13416
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+  cell $and $and$libresoc.v:194922$13416
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406197,10 +406205,10 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A \$109
     connect \B \$111
-    connect \Y $and$libresoc.v:194914$13416_Y
+    connect \Y $and$libresoc.v:194922$13416_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $and $and$libresoc.v:194917$13419
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $and $and$libresoc.v:194925$13419
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406208,10 +406216,10 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A \$115
     connect \B \$117
-    connect \Y $and$libresoc.v:194917$13419_Y
+    connect \Y $and$libresoc.v:194925$13419_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
-  cell $and $and$libresoc.v:194920$13422
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+  cell $and $and$libresoc.v:194928$13422
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406219,10 +406227,10 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A \$121
     connect \B \$123
-    connect \Y $and$libresoc.v:194920$13422_Y
+    connect \Y $and$libresoc.v:194928$13422_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $and $and$libresoc.v:194923$13425
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $and $and$libresoc.v:194931$13425
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406230,10 +406238,10 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A \$127
     connect \B \$129
-    connect \Y $and$libresoc.v:194923$13425_Y
+    connect \Y $and$libresoc.v:194931$13425_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $and $and$libresoc.v:194929$13431
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $and $and$libresoc.v:194937$13431
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406241,10 +406249,10 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A \$139
     connect \B \$141
-    connect \Y $and$libresoc.v:194929$13431_Y
+    connect \Y $and$libresoc.v:194937$13431_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:382"
-  cell $and $and$libresoc.v:194933$13435
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:383"
+  cell $and $and$libresoc.v:194941$13435
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -406252,10 +406260,10 @@ module \ti
     parameter \Y_WIDTH 3
     connect \A \core_state_nia_wen
     connect \B 3'100
-    connect \Y $and$libresoc.v:194933$13435_Y
+    connect \Y $and$libresoc.v:194941$13435_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:384"
-  cell $and $and$libresoc.v:194936$13438
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385"
+  cell $and $and$libresoc.v:194944$13438
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -406263,10 +406271,10 @@ module \ti
     parameter \Y_WIDTH 3
     connect \A \core_state_nia_wen
     connect \B 1'1
-    connect \Y $and$libresoc.v:194936$13438_Y
+    connect \Y $and$libresoc.v:194944$13438_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
-  cell $and $and$libresoc.v:194951$13455
+  cell $and $and$libresoc.v:194959$13455
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406274,10 +406282,10 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A \core_cu_st__rel_o
     connect \B \$34
-    connect \Y $and$libresoc.v:194951$13455_Y
+    connect \Y $and$libresoc.v:194959$13455_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $and $and$libresoc.v:194957$13462
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $and $and$libresoc.v:194965$13462
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406285,10 +406293,10 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A \$44
     connect \B \$46
-    connect \Y $and$libresoc.v:194957$13462_Y
+    connect \Y $and$libresoc.v:194965$13462_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $and $and$libresoc.v:194961$13466
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $and $and$libresoc.v:194969$13466
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406296,34 +406304,34 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A \$52
     connect \B \$54
-    connect \Y $and$libresoc.v:194961$13466_Y
+    connect \Y $and$libresoc.v:194969$13466_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
-  cell $pos $extend$libresoc.v:194941$13443
+  cell $pos $extend$libresoc.v:194949$13443
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \Y_WIDTH 64
     connect \A \core_full_rd2__data_o
-    connect \Y $extend$libresoc.v:194941$13443_Y
+    connect \Y $extend$libresoc.v:194949$13443_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
-  cell $pos $extend$libresoc.v:194942$13445
+  cell $pos $extend$libresoc.v:194950$13445
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 64
     connect \A \core_full_rd__data_o
-    connect \Y $extend$libresoc.v:194942$13445_Y
+    connect \Y $extend$libresoc.v:194950$13445_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
-  cell $pos $extend$libresoc.v:194954$13458
+  cell $pos $extend$libresoc.v:194962$13458
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
     parameter \Y_WIDTH 64
     connect \A \svstate_i
-    connect \Y $extend$libresoc.v:194954$13458_Y
+    connect \Y $extend$libresoc.v:194962$13458_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
-  cell $mul $mul$libresoc.v:194970$13475
+  cell $mul $mul$libresoc.v:194978$13475
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406331,10 +406339,10 @@ module \ti
     parameter \Y_WIDTH 7
     connect \A \dec2_cur_pc [2]
     connect \B 6'100000
-    connect \Y $mul$libresoc.v:194970$13475_Y
+    connect \Y $mul$libresoc.v:194978$13475_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
-  cell $mul $mul$libresoc.v:194975$13480
+  cell $mul $mul$libresoc.v:194983$13480
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406342,10 +406350,10 @@ module \ti
     parameter \Y_WIDTH 7
     connect \A \dec2_cur_pc [2]
     connect \B 6'100000
-    connect \Y $mul$libresoc.v:194975$13480_Y
+    connect \Y $mul$libresoc.v:194983$13480_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
-  cell $mul $mul$libresoc.v:194978$13483
+  cell $mul $mul$libresoc.v:194986$13483
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406353,10 +406361,10 @@ module \ti
     parameter \Y_WIDTH 7
     connect \A \$91 [2]
     connect \B 6'100000
-    connect \Y $mul$libresoc.v:194978$13483_Y
+    connect \Y $mul$libresoc.v:194986$13483_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:379"
-  cell $ne $ne$libresoc.v:194931$13433
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380"
+  cell $ne $ne$libresoc.v:194939$13433
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -406364,10 +406372,10 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A \core_core_core_insn_type
     connect \B 7'0000001
-    connect \Y $ne$libresoc.v:194931$13433_Y
+    connect \Y $ne$libresoc.v:194939$13433_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:452"
-  cell $ne $ne$libresoc.v:194945$13449
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:453"
+  cell $ne $ne$libresoc.v:194953$13449
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -406375,10 +406383,10 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A \delay
     connect \B 1'0
-    connect \Y $ne$libresoc.v:194945$13449_Y
+    connect \Y $ne$libresoc.v:194953$13449_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458"
-  cell $ne $ne$libresoc.v:194949$13453
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:459"
+  cell $ne $ne$libresoc.v:194957$13453
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -406386,314 +406394,314 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A \delay
     connect \B \$30
-    connect \Y $ne$libresoc.v:194949$13453_Y
+    connect \Y $ne$libresoc.v:194957$13453_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
-  cell $not $not$libresoc.v:194907$13409
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+  cell $not $not$libresoc.v:194915$13409
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_coresync_rst
-    connect \Y $not$libresoc.v:194907$13409_Y
+    connect \Y $not$libresoc.v:194915$13409_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $not $not$libresoc.v:194909$13411
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $not $not$libresoc.v:194917$13411
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbg_core_stop_o
-    connect \Y $not$libresoc.v:194909$13411_Y
+    connect \Y $not$libresoc.v:194917$13411_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $not $not$libresoc.v:194910$13412
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $not $not$libresoc.v:194918$13412
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_coresync_rst
-    connect \Y $not$libresoc.v:194910$13412_Y
+    connect \Y $not$libresoc.v:194918$13412_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
-  cell $not $not$libresoc.v:194912$13414
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+  cell $not $not$libresoc.v:194920$13414
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbg_core_stop_o
-    connect \Y $not$libresoc.v:194912$13414_Y
+    connect \Y $not$libresoc.v:194920$13414_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
-  cell $not $not$libresoc.v:194913$13415
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+  cell $not $not$libresoc.v:194921$13415
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_coresync_rst
-    connect \Y $not$libresoc.v:194913$13415_Y
+    connect \Y $not$libresoc.v:194921$13415_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $not $not$libresoc.v:194915$13417
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $not $not$libresoc.v:194923$13417
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbg_core_stop_o
-    connect \Y $not$libresoc.v:194915$13417_Y
+    connect \Y $not$libresoc.v:194923$13417_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $not $not$libresoc.v:194916$13418
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $not $not$libresoc.v:194924$13418
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_coresync_rst
-    connect \Y $not$libresoc.v:194916$13418_Y
+    connect \Y $not$libresoc.v:194924$13418_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
-  cell $not $not$libresoc.v:194918$13420
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+  cell $not $not$libresoc.v:194926$13420
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbg_core_stop_o
-    connect \Y $not$libresoc.v:194918$13420_Y
+    connect \Y $not$libresoc.v:194926$13420_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
-  cell $not $not$libresoc.v:194919$13421
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+  cell $not $not$libresoc.v:194927$13421
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_coresync_rst
-    connect \Y $not$libresoc.v:194919$13421_Y
+    connect \Y $not$libresoc.v:194927$13421_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $not $not$libresoc.v:194921$13423
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $not $not$libresoc.v:194929$13423
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbg_core_stop_o
-    connect \Y $not$libresoc.v:194921$13423_Y
+    connect \Y $not$libresoc.v:194929$13423_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $not $not$libresoc.v:194922$13424
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $not $not$libresoc.v:194930$13424
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_coresync_rst
-    connect \Y $not$libresoc.v:194922$13424_Y
+    connect \Y $not$libresoc.v:194930$13424_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
-  cell $not $not$libresoc.v:194924$13426
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
+  cell $not $not$libresoc.v:194932$13426
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $not$libresoc.v:194924$13426_Y
+    connect \Y $not$libresoc.v:194932$13426_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
-  cell $not $not$libresoc.v:194925$13427
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
+  cell $not $not$libresoc.v:194933$13427
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $not$libresoc.v:194925$13427_Y
+    connect \Y $not$libresoc.v:194933$13427_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
-  cell $not $not$libresoc.v:194926$13428
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
+  cell $not $not$libresoc.v:194934$13428
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $not$libresoc.v:194926$13428_Y
+    connect \Y $not$libresoc.v:194934$13428_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $not $not$libresoc.v:194927$13429
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $not $not$libresoc.v:194935$13429
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbg_core_stop_o
-    connect \Y $not$libresoc.v:194927$13429_Y
+    connect \Y $not$libresoc.v:194935$13429_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $not $not$libresoc.v:194928$13430
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $not $not$libresoc.v:194936$13430
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_coresync_rst
-    connect \Y $not$libresoc.v:194928$13430_Y
+    connect \Y $not$libresoc.v:194936$13430_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
-  cell $not $not$libresoc.v:194932$13434
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
+  cell $not $not$libresoc.v:194940$13434
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $not$libresoc.v:194932$13434_Y
+    connect \Y $not$libresoc.v:194940$13434_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
-  cell $not $not$libresoc.v:194935$13437
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
+  cell $not $not$libresoc.v:194943$13437
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $not$libresoc.v:194935$13437_Y
+    connect \Y $not$libresoc.v:194943$13437_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
-  cell $not $not$libresoc.v:194938$13440
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
+  cell $not $not$libresoc.v:194946$13440
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $not$libresoc.v:194938$13440_Y
+    connect \Y $not$libresoc.v:194946$13440_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
-  cell $not $not$libresoc.v:194939$13441
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
+  cell $not $not$libresoc.v:194947$13441
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $not$libresoc.v:194939$13441_Y
+    connect \Y $not$libresoc.v:194947$13441_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
-  cell $not $not$libresoc.v:194940$13442
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
+  cell $not $not$libresoc.v:194948$13442
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $not$libresoc.v:194940$13442_Y
+    connect \Y $not$libresoc.v:194948$13442_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
-  cell $not $not$libresoc.v:194950$13454
+  cell $not $not$libresoc.v:194958$13454
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \cu_st__rel_o_dly
-    connect \Y $not$libresoc.v:194950$13454_Y
+    connect \Y $not$libresoc.v:194958$13454_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:481"
-  cell $not $not$libresoc.v:194952$13456
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482"
+  cell $not $not$libresoc.v:194960$13456
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \pc_i_ok
-    connect \Y $not$libresoc.v:194952$13456_Y
+    connect \Y $not$libresoc.v:194960$13456_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:495"
-  cell $not $not$libresoc.v:194953$13457
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:496"
+  cell $not $not$libresoc.v:194961$13457
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \svstate_i_ok
-    connect \Y $not$libresoc.v:194953$13457_Y
+    connect \Y $not$libresoc.v:194961$13457_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $not $not$libresoc.v:194955$13460
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $not $not$libresoc.v:194963$13460
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbg_core_stop_o
-    connect \Y $not$libresoc.v:194955$13460_Y
+    connect \Y $not$libresoc.v:194963$13460_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $not $not$libresoc.v:194956$13461
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $not $not$libresoc.v:194964$13461
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_coresync_rst
-    connect \Y $not$libresoc.v:194956$13461_Y
+    connect \Y $not$libresoc.v:194964$13461_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:328"
-  cell $not $not$libresoc.v:194958$13463
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:329"
+  cell $not $not$libresoc.v:194966$13463
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \pc_changed
-    connect \Y $not$libresoc.v:194958$13463_Y
+    connect \Y $not$libresoc.v:194966$13463_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $not $not$libresoc.v:194959$13464
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $not $not$libresoc.v:194967$13464
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbg_core_stop_o
-    connect \Y $not$libresoc.v:194959$13464_Y
+    connect \Y $not$libresoc.v:194967$13464_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
-  cell $not $not$libresoc.v:194960$13465
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
+  cell $not $not$libresoc.v:194968$13465
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_coresync_rst
-    connect \Y $not$libresoc.v:194960$13465_Y
+    connect \Y $not$libresoc.v:194968$13465_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:328"
-  cell $not $not$libresoc.v:194962$13467
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:329"
+  cell $not $not$libresoc.v:194970$13467
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \pc_changed
-    connect \Y $not$libresoc.v:194962$13467_Y
+    connect \Y $not$libresoc.v:194970$13467_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
-  cell $not $not$libresoc.v:194963$13468
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
+  cell $not $not$libresoc.v:194971$13468
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \svp64_is_svp64_mode
-    connect \Y $not$libresoc.v:194963$13468_Y
+    connect \Y $not$libresoc.v:194971$13468_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
-  cell $not $not$libresoc.v:194965$13470
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
+  cell $not $not$libresoc.v:194973$13470
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \svp64_is_svp64_mode
-    connect \Y $not$libresoc.v:194965$13470_Y
+    connect \Y $not$libresoc.v:194973$13470_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
-  cell $not $not$libresoc.v:194966$13471
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
+  cell $not $not$libresoc.v:194974$13471
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \svp64_is_svp64_mode
-    connect \Y $not$libresoc.v:194966$13471_Y
+    connect \Y $not$libresoc.v:194974$13471_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196"
-  cell $not $not$libresoc.v:194967$13472
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
+  cell $not $not$libresoc.v:194975$13472
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \msr_read
-    connect \Y $not$libresoc.v:194967$13472_Y
+    connect \Y $not$libresoc.v:194975$13472_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
-  cell $not $not$libresoc.v:194968$13473
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
+  cell $not $not$libresoc.v:194976$13473
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \svp64_is_svp64_mode
-    connect \Y $not$libresoc.v:194968$13473_Y
+    connect \Y $not$libresoc.v:194976$13473_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196"
-  cell $not $not$libresoc.v:194969$13474
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
+  cell $not $not$libresoc.v:194977$13474
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \msr_read
-    connect \Y $not$libresoc.v:194969$13474_Y
+    connect \Y $not$libresoc.v:194977$13474_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
-  cell $not $not$libresoc.v:194974$13479
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
+  cell $not $not$libresoc.v:194982$13479
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \svp64_is_svp64_mode
-    connect \Y $not$libresoc.v:194974$13479_Y
+    connect \Y $not$libresoc.v:194982$13479_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
-  cell $not $not$libresoc.v:194980$13485
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+  cell $not $not$libresoc.v:194988$13485
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbg_core_stop_o
-    connect \Y $not$libresoc.v:194980$13485_Y
+    connect \Y $not$libresoc.v:194988$13485_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458"
-  cell $or $or$libresoc.v:194947$13451
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:459"
+  cell $or $or$libresoc.v:194955$13451
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406701,10 +406709,10 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A 1'0
     connect \B \dbg_core_rst_o
-    connect \Y $or$libresoc.v:194947$13451_Y
+    connect \Y $or$libresoc.v:194955$13451_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458"
-  cell $or $or$libresoc.v:194948$13452
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:459"
+  cell $or $or$libresoc.v:194956$13452
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -406712,58 +406720,58 @@ module \ti
     parameter \Y_WIDTH 1
     connect \A \$28
     connect \B \rst
-    connect \Y $or$libresoc.v:194948$13452_Y
+    connect \Y $or$libresoc.v:194956$13452_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
-  cell $pos $pos$libresoc.v:194930$13432
+  cell $pos $pos$libresoc.v:194938$13432
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \Y_WIDTH 64
     connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep }
-    connect \Y $pos$libresoc.v:194930$13432_Y
+    connect \Y $pos$libresoc.v:194938$13432_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
-  cell $pos $pos$libresoc.v:194941$13444
+  cell $pos $pos$libresoc.v:194949$13444
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $extend$libresoc.v:194941$13443_Y
-    connect \Y $pos$libresoc.v:194941$13444_Y
+    connect \A $extend$libresoc.v:194949$13443_Y
+    connect \Y $pos$libresoc.v:194949$13444_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
-  cell $pos $pos$libresoc.v:194942$13446
+  cell $pos $pos$libresoc.v:194950$13446
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $extend$libresoc.v:194942$13445_Y
-    connect \Y $pos$libresoc.v:194942$13446_Y
+    connect \A $extend$libresoc.v:194950$13445_Y
+    connect \Y $pos$libresoc.v:194950$13446_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
-  cell $pos $pos$libresoc.v:194954$13459
+  cell $pos $pos$libresoc.v:194962$13459
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $extend$libresoc.v:194954$13458_Y
-    connect \Y $pos$libresoc.v:194954$13459_Y
+    connect \A $extend$libresoc.v:194962$13458_Y
+    connect \Y $pos$libresoc.v:194962$13459_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  cell $reduce_or $reduce_or$libresoc.v:194934$13436
+  cell $reduce_or $reduce_or$libresoc.v:194942$13436
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
     connect \A \$152
-    connect \Y $reduce_or$libresoc.v:194934$13436_Y
+    connect \Y $reduce_or$libresoc.v:194942$13436_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  cell $reduce_or $reduce_or$libresoc.v:194937$13439
+  cell $reduce_or $reduce_or$libresoc.v:194945$13439
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
     connect \A \$158
-    connect \Y $reduce_or$libresoc.v:194937$13439_Y
+    connect \Y $reduce_or$libresoc.v:194945$13439_Y
   end
-  attribute \src "libresoc.v:194971.18-194971.40"
-  cell $shr $shr$libresoc.v:194971$13476
+  attribute \src "libresoc.v:194979.18-194979.40"
+  cell $shr $shr$libresoc.v:194979$13476
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -406771,10 +406779,10 @@ module \ti
     parameter \Y_WIDTH 64
     connect \A \imem_f_instr_o
     connect \B \$76
-    connect \Y $shr$libresoc.v:194971$13476_Y
+    connect \Y $shr$libresoc.v:194979$13476_Y
   end
-  attribute \src "libresoc.v:194976.18-194976.40"
-  cell $shr $shr$libresoc.v:194976$13481
+  attribute \src "libresoc.v:194984.18-194984.40"
+  cell $shr $shr$libresoc.v:194984$13481
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -406782,10 +406790,10 @@ module \ti
     parameter \Y_WIDTH 64
     connect \A \imem_f_instr_o
     connect \B \$87
-    connect \Y $shr$libresoc.v:194976$13481_Y
+    connect \Y $shr$libresoc.v:194984$13481_Y
   end
-  attribute \src "libresoc.v:194979.18-194979.40"
-  cell $shr $shr$libresoc.v:194979$13484
+  attribute \src "libresoc.v:194987.18-194987.40"
+  cell $shr $shr$libresoc.v:194987$13484
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -406793,10 +406801,10 @@ module \ti
     parameter \Y_WIDTH 64
     connect \A \imem_f_instr_o
     connect \B \$94
-    connect \Y $shr$libresoc.v:194979$13484_Y
+    connect \Y $shr$libresoc.v:194987$13484_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:638"
-  cell $sub $sub$libresoc.v:194943$13447
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
+  cell $sub $sub$libresoc.v:194951$13447
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -406804,10 +406812,10 @@ module \ti
     parameter \Y_WIDTH 65
     connect \A \core_issue__data_o
     connect \B 1'1
-    connect \Y $sub$libresoc.v:194943$13447_Y
+    connect \Y $sub$libresoc.v:194951$13447_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:453"
-  cell $sub $sub$libresoc.v:194946$13450
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454"
+  cell $sub $sub$libresoc.v:194954$13450
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -406815,18 +406823,18 @@ module \ti
     parameter \Y_WIDTH 3
     connect \A \delay
     connect \B 1'1
-    connect \Y $sub$libresoc.v:194946$13450_Y
+    connect \Y $sub$libresoc.v:194954$13450_Y
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:212"
-  cell $mux $ternary$libresoc.v:194972$13477
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:213"
+  cell $mux $ternary$libresoc.v:194980$13477
     parameter \WIDTH 4
     connect \A 4'0100
     connect \B 4'1000
     connect \S \svp64_is_svp64_mode
-    connect \Y $ternary$libresoc.v:194972$13477_Y
+    connect \Y $ternary$libresoc.v:194980$13477_Y
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:195201.8-195298.4"
+  attribute \src "libresoc.v:195209.8-195306.4"
   cell \core \core
     connect \bigendian_i \core_bigendian_i$10
     connect \cia__data_o \core_cia__data_o
@@ -406926,7 +406934,7 @@ module \ti
     connect \wen$10 \core_wen$11
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:195299.7-195324.4"
+  attribute \src "libresoc.v:195307.7-195332.4"
   cell \dbg \dbg
     connect \clk \clk
     connect \core_dbg_msr \dbg_core_dbg_msr
@@ -406954,7 +406962,7 @@ module \ti
     connect \terminate_i \dbg_terminate_i
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:195325.8-195393.4"
+  attribute \src "libresoc.v:195333.8-195401.4"
   cell \dec2 \dec2
     connect \asmcode \dec2_asmcode
     connect \bigendian \dec2_bigendian
@@ -407025,7 +407033,7 @@ module \ti
     connect \xer_out \dec2_xer_out
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:195394.8-195410.4"
+  attribute \src "libresoc.v:195402.8-195418.4"
   cell \imem \imem
     connect \a_pc_i \imem_a_pc_i
     connect \a_valid_i \imem_a_valid_i
@@ -407044,7 +407052,7 @@ module \ti
     connect \wb_icache_en \imem_wb_icache_en
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:195411.8-195743.4"
+  attribute \src "libresoc.v:195419.8-195751.4"
   cell \jtag \jtag
     connect \TAP_bus__tck \TAP_bus__tck
     connect \TAP_bus__tdi \TAP_bus__tdi
@@ -407379,7 +407387,7 @@ module \ti
     connect \wb_sram_en \jtag_wb_sram_en
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:195744.12-195756.4"
+  attribute \src "libresoc.v:195752.12-195764.4"
   cell \sram4k_0 \sram4k_0
     connect \clk \clk
     connect \enable \sram4k_0_enable
@@ -407394,7 +407402,7 @@ module \ti
     connect \sram4k_0_wb__we \sram4k_0_wb__we
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:195757.12-195769.4"
+  attribute \src "libresoc.v:195765.12-195777.4"
   cell \sram4k_1 \sram4k_1
     connect \clk \clk
     connect \enable \sram4k_1_enable
@@ -407409,7 +407417,7 @@ module \ti
     connect \sram4k_1_wb__we \sram4k_1_wb__we
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:195770.12-195782.4"
+  attribute \src "libresoc.v:195778.12-195790.4"
   cell \sram4k_2 \sram4k_2
     connect \clk \clk
     connect \enable \sram4k_2_enable
@@ -407424,7 +407432,7 @@ module \ti
     connect \sram4k_2_wb__we \sram4k_2_wb__we
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:195783.12-195795.4"
+  attribute \src "libresoc.v:195791.12-195803.4"
   cell \sram4k_3 \sram4k_3
     connect \clk \clk
     connect \enable \sram4k_3_enable
@@ -407439,7 +407447,7 @@ module \ti
     connect \sram4k_3_wb__we \sram4k_3_wb__we
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:195796.9-195801.4"
+  attribute \src "libresoc.v:195804.9-195809.4"
   cell \svp64 \svp64
     connect \bigendian \svp64_bigendian
     connect \is_svp64_mode \svp64_is_svp64_mode
@@ -407447,7 +407455,7 @@ module \ti
     connect \svp64_rm \svp64_svp64_rm
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:195802.12-195816.4"
+  attribute \src "libresoc.v:195810.12-195824.4"
   cell \xics_icp \xics_icp
     connect \clk \clk
     connect \core_irq_o \xics_icp_core_irq_o
@@ -407464,7 +407472,7 @@ module \ti
     connect \rst \rst
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:195817.12-195830.4"
+  attribute \src "libresoc.v:195825.12-195838.4"
   cell \xics_ics \xics_ics
     connect \clk \clk
     connect \icp_o_pri \xics_ics_icp_o_pri
@@ -407479,1672 +407487,1672 @@ module \ti
     connect \int_level_i \int_level_i
     connect \rst \rst
   end
-  attribute \src "libresoc.v:192544.7-192544.20"
-  process $proc$libresoc.v:192544$14201
+  attribute \src "libresoc.v:192552.7-192552.20"
+  process $proc$libresoc.v:192552$14201
     assign { } { }
     assign $0\initial[0:0] 1'0
     sync always
       update \initial $0\initial[0:0]
     sync init
   end
-  attribute \src "libresoc.v:192718.13-192718.33"
-  process $proc$libresoc.v:192718$14202
+  attribute \src "libresoc.v:192726.13-192726.33"
+  process $proc$libresoc.v:192726$14202
     assign { } { }
     assign $1\core_asmcode[7:0] 8'00000000
     sync always
     sync init
       update \core_asmcode $1\core_asmcode[7:0]
   end
-  attribute \src "libresoc.v:192724.7-192724.35"
-  process $proc$libresoc.v:192724$14203
+  attribute \src "libresoc.v:192732.7-192732.35"
+  process $proc$libresoc.v:192732$14203
     assign { } { }
     assign $0\core_bigendian_i$10[0:0]$14204 1'0
     sync always
     sync init
       update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14204
   end
-  attribute \src "libresoc.v:192732.14-192732.55"
-  process $proc$libresoc.v:192732$14205
+  attribute \src "libresoc.v:192740.14-192740.55"
+  process $proc$libresoc.v:192740$14205
     assign { } { }
     assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \core_core_core_cia $1\core_core_core_cia[63:0]
   end
-  attribute \src "libresoc.v:192736.13-192736.41"
-  process $proc$libresoc.v:192736$14206
+  attribute \src "libresoc.v:192744.13-192744.41"
+  process $proc$libresoc.v:192744$14206
     assign { } { }
     assign $1\core_core_core_cr_rd[7:0] 8'00000000
     sync always
     sync init
       update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0]
   end
-  attribute \src "libresoc.v:192740.7-192740.37"
-  process $proc$libresoc.v:192740$14207
+  attribute \src "libresoc.v:192748.7-192748.37"
+  process $proc$libresoc.v:192748$14207
     assign { } { }
     assign $1\core_core_core_cr_rd_ok[0:0] 1'0
     sync always
     sync init
       update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0]
   end
-  attribute \src "libresoc.v:192744.13-192744.41"
-  process $proc$libresoc.v:192744$14208
+  attribute \src "libresoc.v:192752.13-192752.41"
+  process $proc$libresoc.v:192752$14208
     assign { } { }
     assign $1\core_core_core_cr_wr[7:0] 8'00000000
     sync always
     sync init
       update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0]
   end
-  attribute \src "libresoc.v:192748.7-192748.42"
-  process $proc$libresoc.v:192748$14209
+  attribute \src "libresoc.v:192756.7-192756.42"
+  process $proc$libresoc.v:192756$14209
     assign { } { }
     assign $0\core_core_core_exc_$signal[0:0]$14210 1'0
     sync always
     sync init
       update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14210
   end
-  attribute \src "libresoc.v:192750.7-192750.44"
-  process $proc$libresoc.v:192750$14211
+  attribute \src "libresoc.v:192758.7-192758.44"
+  process $proc$libresoc.v:192758$14211
     assign { } { }
     assign $0\core_core_core_exc_$signal$3[0:0]$14212 1'0
     sync always
     sync init
       update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14212
   end
-  attribute \src "libresoc.v:192754.7-192754.44"
-  process $proc$libresoc.v:192754$14213
+  attribute \src "libresoc.v:192762.7-192762.44"
+  process $proc$libresoc.v:192762$14213
     assign { } { }
     assign $0\core_core_core_exc_$signal$4[0:0]$14214 1'0
     sync always
     sync init
       update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14214
   end
-  attribute \src "libresoc.v:192758.7-192758.44"
-  process $proc$libresoc.v:192758$14215
+  attribute \src "libresoc.v:192766.7-192766.44"
+  process $proc$libresoc.v:192766$14215
     assign { } { }
     assign $0\core_core_core_exc_$signal$5[0:0]$14216 1'0
     sync always
     sync init
       update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14216
   end
-  attribute \src "libresoc.v:192762.7-192762.44"
-  process $proc$libresoc.v:192762$14217
+  attribute \src "libresoc.v:192770.7-192770.44"
+  process $proc$libresoc.v:192770$14217
     assign { } { }
     assign $0\core_core_core_exc_$signal$6[0:0]$14218 1'0
     sync always
     sync init
       update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14218
   end
-  attribute \src "libresoc.v:192766.7-192766.44"
-  process $proc$libresoc.v:192766$14219
+  attribute \src "libresoc.v:192774.7-192774.44"
+  process $proc$libresoc.v:192774$14219
     assign { } { }
     assign $0\core_core_core_exc_$signal$7[0:0]$14220 1'0
     sync always
     sync init
       update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14220
   end
-  attribute \src "libresoc.v:192770.7-192770.44"
-  process $proc$libresoc.v:192770$14221
+  attribute \src "libresoc.v:192778.7-192778.44"
+  process $proc$libresoc.v:192778$14221
     assign { } { }
     assign $0\core_core_core_exc_$signal$8[0:0]$14222 1'0
     sync always
     sync init
       update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14222
   end
-  attribute \src "libresoc.v:192774.7-192774.44"
-  process $proc$libresoc.v:192774$14223
+  attribute \src "libresoc.v:192782.7-192782.44"
+  process $proc$libresoc.v:192782$14223
     assign { } { }
     assign $0\core_core_core_exc_$signal$9[0:0]$14224 1'0
     sync always
     sync init
       update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14224
   end
-  attribute \src "libresoc.v:192794.14-192794.47"
-  process $proc$libresoc.v:192794$14225
+  attribute \src "libresoc.v:192802.14-192802.47"
+  process $proc$libresoc.v:192802$14225
     assign { } { }
     assign $1\core_core_core_fn_unit[12:0] 13'0000000000000
     sync always
     sync init
       update \core_core_core_fn_unit $1\core_core_core_fn_unit[12:0]
   end
-  attribute \src "libresoc.v:192802.13-192802.46"
-  process $proc$libresoc.v:192802$14226
+  attribute \src "libresoc.v:192810.13-192810.46"
+  process $proc$libresoc.v:192810$14226
     assign { } { }
     assign $1\core_core_core_input_carry[1:0] 2'00
     sync always
     sync init
       update \core_core_core_input_carry $1\core_core_core_input_carry[1:0]
   end
-  attribute \src "libresoc.v:192806.14-192806.41"
-  process $proc$libresoc.v:192806$14227
+  attribute \src "libresoc.v:192814.14-192814.41"
+  process $proc$libresoc.v:192814$14227
     assign { } { }
     assign $1\core_core_core_insn[31:0] 0
     sync always
     sync init
       update \core_core_core_insn $1\core_core_core_insn[31:0]
   end
-  attribute \src "libresoc.v:192884.13-192884.45"
-  process $proc$libresoc.v:192884$14228
+  attribute \src "libresoc.v:192892.13-192892.45"
+  process $proc$libresoc.v:192892$14228
     assign { } { }
     assign $1\core_core_core_insn_type[6:0] 7'0000000
     sync always
     sync init
       update \core_core_core_insn_type $1\core_core_core_insn_type[6:0]
   end
-  attribute \src "libresoc.v:192888.7-192888.37"
-  process $proc$libresoc.v:192888$14229
+  attribute \src "libresoc.v:192896.7-192896.37"
+  process $proc$libresoc.v:192896$14229
     assign { } { }
     assign $1\core_core_core_is_32bit[0:0] 1'0
     sync always
     sync init
       update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0]
   end
-  attribute \src "libresoc.v:192892.14-192892.55"
-  process $proc$libresoc.v:192892$14230
+  attribute \src "libresoc.v:192900.14-192900.55"
+  process $proc$libresoc.v:192900$14230
     assign { } { }
     assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \core_core_core_msr $1\core_core_core_msr[63:0]
   end
-  attribute \src "libresoc.v:192896.7-192896.31"
-  process $proc$libresoc.v:192896$14231
+  attribute \src "libresoc.v:192904.7-192904.31"
+  process $proc$libresoc.v:192904$14231
     assign { } { }
     assign $1\core_core_core_oe[0:0] 1'0
     sync always
     sync init
       update \core_core_core_oe $1\core_core_core_oe[0:0]
   end
-  attribute \src "libresoc.v:192900.7-192900.34"
-  process $proc$libresoc.v:192900$14232
+  attribute \src "libresoc.v:192908.7-192908.34"
+  process $proc$libresoc.v:192908$14232
     assign { } { }
     assign $1\core_core_core_oe_ok[0:0] 1'0
     sync always
     sync init
       update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0]
   end
-  attribute \src "libresoc.v:192904.7-192904.31"
-  process $proc$libresoc.v:192904$14233
+  attribute \src "libresoc.v:192912.7-192912.31"
+  process $proc$libresoc.v:192912$14233
     assign { } { }
     assign $1\core_core_core_rc[0:0] 1'0
     sync always
     sync init
       update \core_core_core_rc $1\core_core_core_rc[0:0]
   end
-  attribute \src "libresoc.v:192908.7-192908.34"
-  process $proc$libresoc.v:192908$14234
+  attribute \src "libresoc.v:192916.7-192916.34"
+  process $proc$libresoc.v:192916$14234
     assign { } { }
     assign $1\core_core_core_rc_ok[0:0] 1'0
     sync always
     sync init
       update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0]
   end
-  attribute \src "libresoc.v:192912.14-192912.48"
-  process $proc$libresoc.v:192912$14235
+  attribute \src "libresoc.v:192920.14-192920.48"
+  process $proc$libresoc.v:192920$14235
     assign { } { }
     assign $1\core_core_core_trapaddr[12:0] 13'0000000000000
     sync always
     sync init
       update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0]
   end
-  attribute \src "libresoc.v:192916.13-192916.44"
-  process $proc$libresoc.v:192916$14236
+  attribute \src "libresoc.v:192924.13-192924.44"
+  process $proc$libresoc.v:192924$14236
     assign { } { }
     assign $1\core_core_core_traptype[7:0] 8'00000000
     sync always
     sync init
       update \core_core_core_traptype $1\core_core_core_traptype[7:0]
   end
-  attribute \src "libresoc.v:192920.13-192920.37"
-  process $proc$libresoc.v:192920$14237
+  attribute \src "libresoc.v:192928.13-192928.37"
+  process $proc$libresoc.v:192928$14237
     assign { } { }
     assign $1\core_core_cr_in1[6:0] 7'0000000
     sync always
     sync init
       update \core_core_cr_in1 $1\core_core_cr_in1[6:0]
   end
-  attribute \src "libresoc.v:192924.7-192924.33"
-  process $proc$libresoc.v:192924$14238
+  attribute \src "libresoc.v:192932.7-192932.33"
+  process $proc$libresoc.v:192932$14238
     assign { } { }
     assign $1\core_core_cr_in1_ok[0:0] 1'0
     sync always
     sync init
       update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0]
   end
-  attribute \src "libresoc.v:192928.13-192928.37"
-  process $proc$libresoc.v:192928$14239
+  attribute \src "libresoc.v:192936.13-192936.37"
+  process $proc$libresoc.v:192936$14239
     assign { } { }
     assign $1\core_core_cr_in2[6:0] 7'0000000
     sync always
     sync init
       update \core_core_cr_in2 $1\core_core_cr_in2[6:0]
   end
-  attribute \src "libresoc.v:192930.13-192930.41"
-  process $proc$libresoc.v:192930$14240
+  attribute \src "libresoc.v:192938.13-192938.41"
+  process $proc$libresoc.v:192938$14240
     assign { } { }
     assign $0\core_core_cr_in2$1[6:0]$14241 7'0000000
     sync always
     sync init
       update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14241
   end
-  attribute \src "libresoc.v:192936.7-192936.33"
-  process $proc$libresoc.v:192936$14242
+  attribute \src "libresoc.v:192944.7-192944.33"
+  process $proc$libresoc.v:192944$14242
     assign { } { }
     assign $1\core_core_cr_in2_ok[0:0] 1'0
     sync always
     sync init
       update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0]
   end
-  attribute \src "libresoc.v:192938.7-192938.37"
-  process $proc$libresoc.v:192938$14243
+  attribute \src "libresoc.v:192946.7-192946.37"
+  process $proc$libresoc.v:192946$14243
     assign { } { }
     assign $0\core_core_cr_in2_ok$2[0:0]$14244 1'0
     sync always
     sync init
       update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14244
   end
-  attribute \src "libresoc.v:192944.13-192944.37"
-  process $proc$libresoc.v:192944$14245
+  attribute \src "libresoc.v:192952.13-192952.37"
+  process $proc$libresoc.v:192952$14245
     assign { } { }
     assign $1\core_core_cr_out[6:0] 7'0000000
     sync always
     sync init
       update \core_core_cr_out $1\core_core_cr_out[6:0]
   end
-  attribute \src "libresoc.v:192948.7-192948.32"
-  process $proc$libresoc.v:192948$14246
+  attribute \src "libresoc.v:192956.7-192956.32"
+  process $proc$libresoc.v:192956$14246
     assign { } { }
     assign $1\core_core_cr_wr_ok[0:0] 1'0
     sync always
     sync init
       update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0]
   end
-  attribute \src "libresoc.v:192952.13-192952.38"
-  process $proc$libresoc.v:192952$14247
+  attribute \src "libresoc.v:192960.13-192960.38"
+  process $proc$libresoc.v:192960$14247
     assign { } { }
     assign $1\core_core_dststep[6:0] 7'0000000
     sync always
     sync init
       update \core_core_dststep $1\core_core_dststep[6:0]
   end
-  attribute \src "libresoc.v:192956.13-192956.33"
-  process $proc$libresoc.v:192956$14248
+  attribute \src "libresoc.v:192964.13-192964.33"
+  process $proc$libresoc.v:192964$14248
     assign { } { }
     assign $1\core_core_ea[6:0] 7'0000000
     sync always
     sync init
       update \core_core_ea $1\core_core_ea[6:0]
   end
-  attribute \src "libresoc.v:192960.13-192960.35"
-  process $proc$libresoc.v:192960$14249
+  attribute \src "libresoc.v:192968.13-192968.35"
+  process $proc$libresoc.v:192968$14249
     assign { } { }
     assign $1\core_core_fast1[2:0] 3'000
     sync always
     sync init
       update \core_core_fast1 $1\core_core_fast1[2:0]
   end
-  attribute \src "libresoc.v:192964.7-192964.32"
-  process $proc$libresoc.v:192964$14250
+  attribute \src "libresoc.v:192972.7-192972.32"
+  process $proc$libresoc.v:192972$14250
     assign { } { }
     assign $1\core_core_fast1_ok[0:0] 1'0
     sync always
     sync init
       update \core_core_fast1_ok $1\core_core_fast1_ok[0:0]
   end
-  attribute \src "libresoc.v:192968.13-192968.35"
-  process $proc$libresoc.v:192968$14251
+  attribute \src "libresoc.v:192976.13-192976.35"
+  process $proc$libresoc.v:192976$14251
     assign { } { }
     assign $1\core_core_fast2[2:0] 3'000
     sync always
     sync init
       update \core_core_fast2 $1\core_core_fast2[2:0]
   end
-  attribute \src "libresoc.v:192972.7-192972.32"
-  process $proc$libresoc.v:192972$14252
+  attribute \src "libresoc.v:192980.7-192980.32"
+  process $proc$libresoc.v:192980$14252
     assign { } { }
     assign $1\core_core_fast2_ok[0:0] 1'0
     sync always
     sync init
       update \core_core_fast2_ok $1\core_core_fast2_ok[0:0]
   end
-  attribute \src "libresoc.v:192976.13-192976.36"
-  process $proc$libresoc.v:192976$14253
+  attribute \src "libresoc.v:192984.13-192984.36"
+  process $proc$libresoc.v:192984$14253
     assign { } { }
     assign $1\core_core_fasto1[2:0] 3'000
     sync always
     sync init
       update \core_core_fasto1 $1\core_core_fasto1[2:0]
   end
-  attribute \src "libresoc.v:192980.13-192980.36"
-  process $proc$libresoc.v:192980$14254
+  attribute \src "libresoc.v:192988.13-192988.36"
+  process $proc$libresoc.v:192988$14254
     assign { } { }
     assign $1\core_core_fasto2[2:0] 3'000
     sync always
     sync init
       update \core_core_fasto2 $1\core_core_fasto2[2:0]
   end
-  attribute \src "libresoc.v:192984.7-192984.26"
-  process $proc$libresoc.v:192984$14255
+  attribute \src "libresoc.v:192992.7-192992.26"
+  process $proc$libresoc.v:192992$14255
     assign { } { }
     assign $1\core_core_lk[0:0] 1'0
     sync always
     sync init
       update \core_core_lk $1\core_core_lk[0:0]
   end
-  attribute \src "libresoc.v:192988.13-192988.36"
-  process $proc$libresoc.v:192988$14256
+  attribute \src "libresoc.v:192996.13-192996.36"
+  process $proc$libresoc.v:192996$14256
     assign { } { }
     assign $1\core_core_maxvl[6:0] 7'0000000
     sync always
     sync init
       update \core_core_maxvl $1\core_core_maxvl[6:0]
   end
-  attribute \src "libresoc.v:192992.14-192992.49"
-  process $proc$libresoc.v:192992$14257
+  attribute \src "libresoc.v:193000.14-193000.49"
+  process $proc$libresoc.v:193000$14257
     assign { } { }
     assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \core_core_pc $1\core_core_pc[63:0]
   end
-  attribute \src "libresoc.v:192996.13-192996.35"
-  process $proc$libresoc.v:192996$14258
+  attribute \src "libresoc.v:193004.13-193004.35"
+  process $proc$libresoc.v:193004$14258
     assign { } { }
     assign $1\core_core_reg1[6:0] 7'0000000
     sync always
     sync init
       update \core_core_reg1 $1\core_core_reg1[6:0]
   end
-  attribute \src "libresoc.v:193000.7-193000.31"
-  process $proc$libresoc.v:193000$14259
+  attribute \src "libresoc.v:193008.7-193008.31"
+  process $proc$libresoc.v:193008$14259
     assign { } { }
     assign $1\core_core_reg1_ok[0:0] 1'0
     sync always
     sync init
       update \core_core_reg1_ok $1\core_core_reg1_ok[0:0]
   end
-  attribute \src "libresoc.v:193004.13-193004.35"
-  process $proc$libresoc.v:193004$14260
+  attribute \src "libresoc.v:193012.13-193012.35"
+  process $proc$libresoc.v:193012$14260
     assign { } { }
     assign $1\core_core_reg2[6:0] 7'0000000
     sync always
     sync init
       update \core_core_reg2 $1\core_core_reg2[6:0]
   end
-  attribute \src "libresoc.v:193008.7-193008.31"
-  process $proc$libresoc.v:193008$14261
+  attribute \src "libresoc.v:193016.7-193016.31"
+  process $proc$libresoc.v:193016$14261
     assign { } { }
     assign $1\core_core_reg2_ok[0:0] 1'0
     sync always
     sync init
       update \core_core_reg2_ok $1\core_core_reg2_ok[0:0]
   end
-  attribute \src "libresoc.v:193012.13-193012.35"
-  process $proc$libresoc.v:193012$14262
+  attribute \src "libresoc.v:193020.13-193020.35"
+  process $proc$libresoc.v:193020$14262
     assign { } { }
     assign $1\core_core_reg3[6:0] 7'0000000
     sync always
     sync init
       update \core_core_reg3 $1\core_core_reg3[6:0]
   end
-  attribute \src "libresoc.v:193016.7-193016.31"
-  process $proc$libresoc.v:193016$14263
+  attribute \src "libresoc.v:193024.7-193024.31"
+  process $proc$libresoc.v:193024$14263
     assign { } { }
     assign $1\core_core_reg3_ok[0:0] 1'0
     sync always
     sync init
       update \core_core_reg3_ok $1\core_core_reg3_ok[0:0]
   end
-  attribute \src "libresoc.v:193020.13-193020.35"
-  process $proc$libresoc.v:193020$14264
+  attribute \src "libresoc.v:193028.13-193028.35"
+  process $proc$libresoc.v:193028$14264
     assign { } { }
     assign $1\core_core_rego[6:0] 7'0000000
     sync always
     sync init
       update \core_core_rego $1\core_core_rego[6:0]
   end
-  attribute \src "libresoc.v:193138.13-193138.37"
-  process $proc$libresoc.v:193138$14265
+  attribute \src "libresoc.v:193146.13-193146.37"
+  process $proc$libresoc.v:193146$14265
     assign { } { }
     assign $1\core_core_spr1[9:0] 10'0000000000
     sync always
     sync init
       update \core_core_spr1 $1\core_core_spr1[9:0]
   end
-  attribute \src "libresoc.v:193142.7-193142.31"
-  process $proc$libresoc.v:193142$14266
+  attribute \src "libresoc.v:193150.7-193150.31"
+  process $proc$libresoc.v:193150$14266
     assign { } { }
     assign $1\core_core_spr1_ok[0:0] 1'0
     sync always
     sync init
       update \core_core_spr1_ok $1\core_core_spr1_ok[0:0]
   end
-  attribute \src "libresoc.v:193260.13-193260.37"
-  process $proc$libresoc.v:193260$14267
+  attribute \src "libresoc.v:193268.13-193268.37"
+  process $proc$libresoc.v:193268$14267
     assign { } { }
     assign $1\core_core_spro[9:0] 10'0000000000
     sync always
     sync init
       update \core_core_spro $1\core_core_spro[9:0]
   end
-  attribute \src "libresoc.v:193264.13-193264.38"
-  process $proc$libresoc.v:193264$14268
+  attribute \src "libresoc.v:193272.13-193272.38"
+  process $proc$libresoc.v:193272$14268
     assign { } { }
     assign $1\core_core_srcstep[6:0] 7'0000000
     sync always
     sync init
       update \core_core_srcstep $1\core_core_srcstep[6:0]
   end
-  attribute \src "libresoc.v:193268.13-193268.35"
-  process $proc$libresoc.v:193268$14269
+  attribute \src "libresoc.v:193276.13-193276.35"
+  process $proc$libresoc.v:193276$14269
     assign { } { }
     assign $1\core_core_subvl[1:0] 2'00
     sync always
     sync init
       update \core_core_subvl $1\core_core_subvl[1:0]
   end
-  attribute \src "libresoc.v:193272.13-193272.36"
-  process $proc$libresoc.v:193272$14270
+  attribute \src "libresoc.v:193280.13-193280.36"
+  process $proc$libresoc.v:193280$14270
     assign { } { }
     assign $1\core_core_svstep[1:0] 2'00
     sync always
     sync init
       update \core_core_svstep $1\core_core_svstep[1:0]
   end
-  attribute \src "libresoc.v:193278.13-193278.33"
-  process $proc$libresoc.v:193278$14271
+  attribute \src "libresoc.v:193286.13-193286.33"
+  process $proc$libresoc.v:193286$14271
     assign { } { }
     assign $1\core_core_vl[6:0] 7'0000000
     sync always
     sync init
       update \core_core_vl $1\core_core_vl[6:0]
   end
-  attribute \src "libresoc.v:193282.13-193282.36"
-  process $proc$libresoc.v:193282$14272
+  attribute \src "libresoc.v:193290.13-193290.36"
+  process $proc$libresoc.v:193290$14272
     assign { } { }
     assign $1\core_core_xer_in[2:0] 3'000
     sync always
     sync init
       update \core_core_xer_in $1\core_core_xer_in[2:0]
   end
-  attribute \src "libresoc.v:193290.7-193290.28"
-  process $proc$libresoc.v:193290$14273
+  attribute \src "libresoc.v:193298.7-193298.28"
+  process $proc$libresoc.v:193298$14273
     assign { } { }
     assign $1\core_cr_out_ok[0:0] 1'0
     sync always
     sync init
       update \core_cr_out_ok $1\core_cr_out_ok[0:0]
   end
-  attribute \src "libresoc.v:193318.14-193318.45"
-  process $proc$libresoc.v:193318$14274
+  attribute \src "libresoc.v:193326.14-193326.45"
+  process $proc$libresoc.v:193326$14274
     assign { } { }
     assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \core_dec $1\core_dec[63:0]
   end
-  attribute \src "libresoc.v:193328.7-193328.24"
-  process $proc$libresoc.v:193328$14275
+  attribute \src "libresoc.v:193336.7-193336.24"
+  process $proc$libresoc.v:193336$14275
     assign { } { }
     assign $1\core_ea_ok[0:0] 1'0
     sync always
     sync init
       update \core_ea_ok $1\core_ea_ok[0:0]
   end
-  attribute \src "libresoc.v:193332.7-193332.23"
-  process $proc$libresoc.v:193332$14276
+  attribute \src "libresoc.v:193340.7-193340.23"
+  process $proc$libresoc.v:193340$14276
     assign { } { }
     assign $1\core_eint[0:0] 1'0
     sync always
     sync init
       update \core_eint $1\core_eint[0:0]
   end
-  attribute \src "libresoc.v:193336.7-193336.28"
-  process $proc$libresoc.v:193336$14277
+  attribute \src "libresoc.v:193344.7-193344.28"
+  process $proc$libresoc.v:193344$14277
     assign { } { }
     assign $1\core_fasto1_ok[0:0] 1'0
     sync always
     sync init
       update \core_fasto1_ok $1\core_fasto1_ok[0:0]
   end
-  attribute \src "libresoc.v:193340.7-193340.28"
-  process $proc$libresoc.v:193340$14278
+  attribute \src "libresoc.v:193348.7-193348.28"
+  process $proc$libresoc.v:193348$14278
     assign { } { }
     assign $1\core_fasto2_ok[0:0] 1'0
     sync always
     sync init
       update \core_fasto2_ok $1\core_fasto2_ok[0:0]
   end
-  attribute \src "libresoc.v:193368.14-193368.45"
-  process $proc$libresoc.v:193368$14279
+  attribute \src "libresoc.v:193376.14-193376.45"
+  process $proc$libresoc.v:193376$14279
     assign { } { }
     assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \core_msr $1\core_msr[63:0]
   end
-  attribute \src "libresoc.v:193376.14-193376.37"
-  process $proc$libresoc.v:193376$14280
+  attribute \src "libresoc.v:193384.14-193384.37"
+  process $proc$libresoc.v:193384$14280
     assign { } { }
     assign $1\core_raw_insn_i[31:0] 0
     sync always
     sync init
       update \core_raw_insn_i $1\core_raw_insn_i[31:0]
   end
-  attribute \src "libresoc.v:193380.7-193380.26"
-  process $proc$libresoc.v:193380$14281
+  attribute \src "libresoc.v:193388.7-193388.26"
+  process $proc$libresoc.v:193388$14281
     assign { } { }
     assign $1\core_rego_ok[0:0] 1'0
     sync always
     sync init
       update \core_rego_ok $1\core_rego_ok[0:0]
   end
-  attribute \src "libresoc.v:193384.7-193384.26"
-  process $proc$libresoc.v:193384$14282
+  attribute \src "libresoc.v:193392.7-193392.26"
+  process $proc$libresoc.v:193392$14282
     assign { } { }
     assign $1\core_spro_ok[0:0] 1'0
     sync always
     sync init
       update \core_spro_ok $1\core_spro_ok[0:0]
   end
-  attribute \src "libresoc.v:193402.7-193402.26"
-  process $proc$libresoc.v:193402$14283
+  attribute \src "libresoc.v:193410.7-193410.26"
+  process $proc$libresoc.v:193410$14283
     assign { } { }
     assign $1\core_xer_out[0:0] 1'0
     sync always
     sync init
       update \core_xer_out $1\core_xer_out[0:0]
   end
-  attribute \src "libresoc.v:193408.7-193408.30"
-  process $proc$libresoc.v:193408$14284
+  attribute \src "libresoc.v:193416.7-193416.30"
+  process $proc$libresoc.v:193416$14284
     assign { } { }
     assign $1\cu_st__rel_o_dly[0:0] 1'0
     sync always
     sync init
       update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0]
   end
-  attribute \src "libresoc.v:193414.13-193414.36"
-  process $proc$libresoc.v:193414$14285
+  attribute \src "libresoc.v:193422.13-193422.36"
+  process $proc$libresoc.v:193422$14285
     assign { } { }
     assign $1\cur_cur_dststep[6:0] 7'0000000
     sync always
     sync init
       update \cur_cur_dststep $1\cur_cur_dststep[6:0]
   end
-  attribute \src "libresoc.v:193418.13-193418.34"
-  process $proc$libresoc.v:193418$14286
+  attribute \src "libresoc.v:193426.13-193426.34"
+  process $proc$libresoc.v:193426$14286
     assign { } { }
     assign $1\cur_cur_maxvl[6:0] 7'0000000
     sync always
     sync init
       update \cur_cur_maxvl $1\cur_cur_maxvl[6:0]
   end
-  attribute \src "libresoc.v:193422.13-193422.33"
-  process $proc$libresoc.v:193422$14287
+  attribute \src "libresoc.v:193430.13-193430.33"
+  process $proc$libresoc.v:193430$14287
     assign { } { }
     assign $1\cur_cur_subvl[1:0] 2'00
     sync always
     sync init
       update \cur_cur_subvl $1\cur_cur_subvl[1:0]
   end
-  attribute \src "libresoc.v:193426.13-193426.34"
-  process $proc$libresoc.v:193426$14288
+  attribute \src "libresoc.v:193434.13-193434.34"
+  process $proc$libresoc.v:193434$14288
     assign { } { }
     assign $1\cur_cur_svstep[1:0] 2'00
     sync always
     sync init
       update \cur_cur_svstep $1\cur_cur_svstep[1:0]
   end
-  attribute \src "libresoc.v:193430.13-193430.31"
-  process $proc$libresoc.v:193430$14289
+  attribute \src "libresoc.v:193438.13-193438.31"
+  process $proc$libresoc.v:193438$14289
     assign { } { }
     assign $1\cur_cur_vl[6:0] 7'0000000
     sync always
     sync init
       update \cur_cur_vl $1\cur_cur_vl[6:0]
   end
-  attribute \src "libresoc.v:193434.7-193434.24"
-  process $proc$libresoc.v:193434$14290
+  attribute \src "libresoc.v:193442.7-193442.24"
+  process $proc$libresoc.v:193442$14290
     assign { } { }
     assign $1\d_cr_delay[0:0] 1'0
     sync always
     sync init
       update \d_cr_delay $1\d_cr_delay[0:0]
   end
-  attribute \src "libresoc.v:193438.7-193438.25"
-  process $proc$libresoc.v:193438$14291
+  attribute \src "libresoc.v:193446.7-193446.25"
+  process $proc$libresoc.v:193446$14291
     assign { } { }
     assign $1\d_reg_delay[0:0] 1'0
     sync always
     sync init
       update \d_reg_delay $1\d_reg_delay[0:0]
   end
-  attribute \src "libresoc.v:193442.7-193442.25"
-  process $proc$libresoc.v:193442$14292
+  attribute \src "libresoc.v:193450.7-193450.25"
+  process $proc$libresoc.v:193450$14292
     assign { } { }
     assign $1\d_xer_delay[0:0] 1'0
     sync always
     sync init
       update \d_xer_delay $1\d_xer_delay[0:0]
   end
-  attribute \src "libresoc.v:193478.13-193478.34"
-  process $proc$libresoc.v:193478$14293
+  attribute \src "libresoc.v:193486.13-193486.34"
+  process $proc$libresoc.v:193486$14293
     assign { } { }
     assign $1\dbg_dmi_addr_i[3:0] 4'0000
     sync always
     sync init
       update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0]
   end
-  attribute \src "libresoc.v:193482.14-193482.48"
-  process $proc$libresoc.v:193482$14294
+  attribute \src "libresoc.v:193490.14-193490.48"
+  process $proc$libresoc.v:193490$14294
     assign { } { }
     assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \dbg_dmi_din $1\dbg_dmi_din[63:0]
   end
-  attribute \src "libresoc.v:193488.7-193488.27"
-  process $proc$libresoc.v:193488$14295
+  attribute \src "libresoc.v:193496.7-193496.27"
+  process $proc$libresoc.v:193496$14295
     assign { } { }
     assign $1\dbg_dmi_req_i[0:0] 1'0
     sync always
     sync init
       update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0]
   end
-  attribute \src "libresoc.v:193492.7-193492.26"
-  process $proc$libresoc.v:193492$14296
+  attribute \src "libresoc.v:193500.7-193500.26"
+  process $proc$libresoc.v:193500$14296
     assign { } { }
     assign $1\dbg_dmi_we_i[0:0] 1'0
     sync always
     sync init
       update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0]
   end
-  attribute \src "libresoc.v:193546.13-193546.41"
-  process $proc$libresoc.v:193546$14297
+  attribute \src "libresoc.v:193554.13-193554.41"
+  process $proc$libresoc.v:193554$14297
     assign { } { }
     assign $1\dec2_cur_cur_srcstep[6:0] 7'0000000
     sync always
     sync init
       update \dec2_cur_cur_srcstep $1\dec2_cur_cur_srcstep[6:0]
   end
-  attribute \src "libresoc.v:193550.14-193550.49"
-  process $proc$libresoc.v:193550$14298
+  attribute \src "libresoc.v:193558.14-193558.49"
+  process $proc$libresoc.v:193558$14298
     assign { } { }
     assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \dec2_cur_dec $1\dec2_cur_dec[63:0]
   end
-  attribute \src "libresoc.v:193554.7-193554.27"
-  process $proc$libresoc.v:193554$14299
+  attribute \src "libresoc.v:193562.7-193562.27"
+  process $proc$libresoc.v:193562$14299
     assign { } { }
     assign $1\dec2_cur_eint[0:0] 1'0
     sync always
     sync init
       update \dec2_cur_eint $1\dec2_cur_eint[0:0]
   end
-  attribute \src "libresoc.v:193558.14-193558.49"
-  process $proc$libresoc.v:193558$14300
+  attribute \src "libresoc.v:193566.14-193566.49"
+  process $proc$libresoc.v:193566$14300
     assign { } { }
     assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \dec2_cur_msr $1\dec2_cur_msr[63:0]
   end
-  attribute \src "libresoc.v:193562.14-193562.48"
-  process $proc$libresoc.v:193562$14301
+  attribute \src "libresoc.v:193570.14-193570.48"
+  process $proc$libresoc.v:193570$14301
     assign { } { }
     assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \dec2_cur_pc $1\dec2_cur_pc[63:0]
   end
-  attribute \src "libresoc.v:193566.13-193566.43"
-  process $proc$libresoc.v:193566$14302
+  attribute \src "libresoc.v:193574.13-193574.43"
+  process $proc$libresoc.v:193574$14302
     assign { } { }
     assign $1\dec2_dec_svp64__extra[8:0] 9'000000000
     sync always
     sync init
       update \dec2_dec_svp64__extra $1\dec2_dec_svp64__extra[8:0]
   end
-  attribute \src "libresoc.v:193716.14-193716.40"
-  process $proc$libresoc.v:193716$14303
+  attribute \src "libresoc.v:193724.14-193724.40"
+  process $proc$libresoc.v:193724$14303
     assign { } { }
     assign $1\dec2_raw_opcode_in[31:0] 0
     sync always
     sync init
       update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0]
   end
-  attribute \src "libresoc.v:193984.13-193984.38"
-  process $proc$libresoc.v:193984$14304
+  attribute \src "libresoc.v:193992.13-193992.38"
+  process $proc$libresoc.v:193992$14304
     assign { } { }
     assign $1\dec_svp64__elwidth[1:0] 2'00
     sync always
     sync init
       update \dec_svp64__elwidth $1\dec_svp64__elwidth[1:0]
   end
-  attribute \src "libresoc.v:193988.13-193988.36"
-  process $proc$libresoc.v:193988$14305
+  attribute \src "libresoc.v:193996.13-193996.36"
+  process $proc$libresoc.v:193996$14305
     assign { } { }
     assign $1\dec_svp64__ewsrc[1:0] 2'00
     sync always
     sync init
       update \dec_svp64__ewsrc $1\dec_svp64__ewsrc[1:0]
   end
-  attribute \src "libresoc.v:193992.13-193992.35"
-  process $proc$libresoc.v:193992$14306
+  attribute \src "libresoc.v:194000.13-194000.35"
+  process $proc$libresoc.v:194000$14306
     assign { } { }
     assign $1\dec_svp64__mask[2:0] 3'000
     sync always
     sync init
       update \dec_svp64__mask $1\dec_svp64__mask[2:0]
   end
-  attribute \src "libresoc.v:193996.7-193996.30"
-  process $proc$libresoc.v:193996$14307
+  attribute \src "libresoc.v:194004.7-194004.30"
+  process $proc$libresoc.v:194004$14307
     assign { } { }
     assign $1\dec_svp64__mmode[0:0] 1'0
     sync always
     sync init
       update \dec_svp64__mmode $1\dec_svp64__mmode[0:0]
   end
-  attribute \src "libresoc.v:194000.13-194000.36"
-  process $proc$libresoc.v:194000$14308
+  attribute \src "libresoc.v:194008.13-194008.36"
+  process $proc$libresoc.v:194008$14308
     assign { } { }
     assign $1\dec_svp64__mode[4:0] 5'00000
     sync always
     sync init
       update \dec_svp64__mode $1\dec_svp64__mode[4:0]
   end
-  attribute \src "libresoc.v:194004.13-194004.36"
-  process $proc$libresoc.v:194004$14309
+  attribute \src "libresoc.v:194012.13-194012.36"
+  process $proc$libresoc.v:194012$14309
     assign { } { }
     assign $1\dec_svp64__subvl[1:0] 2'00
     sync always
     sync init
       update \dec_svp64__subvl $1\dec_svp64__subvl[1:0]
   end
-  attribute \src "libresoc.v:194008.13-194008.25"
-  process $proc$libresoc.v:194008$14310
+  attribute \src "libresoc.v:194016.13-194016.25"
+  process $proc$libresoc.v:194016$14310
     assign { } { }
     assign $1\delay[1:0] 2'11
     sync always
     sync init
       update \delay $1\delay[1:0]
   end
-  attribute \src "libresoc.v:194024.7-194024.28"
-  process $proc$libresoc.v:194024$14311
+  attribute \src "libresoc.v:194032.7-194032.28"
+  process $proc$libresoc.v:194032$14311
     assign { } { }
     assign $1\exec_fsm_state[0:0] 1'0
     sync always
     sync init
       update \exec_fsm_state $1\exec_fsm_state[0:0]
   end
-  attribute \src "libresoc.v:194036.13-194036.35"
-  process $proc$libresoc.v:194036$14312
+  attribute \src "libresoc.v:194044.13-194044.35"
+  process $proc$libresoc.v:194044$14312
     assign { } { }
     assign $1\fetch_fsm_state[1:0] 2'00
     sync always
     sync init
       update \fetch_fsm_state $1\fetch_fsm_state[1:0]
   end
-  attribute \src "libresoc.v:194050.13-194050.29"
-  process $proc$libresoc.v:194050$14313
+  attribute \src "libresoc.v:194058.13-194058.29"
+  process $proc$libresoc.v:194058$14313
     assign { } { }
     assign $1\fsm_state[1:0] 2'00
     sync always
     sync init
       update \fsm_state $1\fsm_state[1:0]
   end
-  attribute \src "libresoc.v:194306.13-194306.35"
-  process $proc$libresoc.v:194306$14314
+  attribute \src "libresoc.v:194314.13-194314.35"
+  process $proc$libresoc.v:194314$14314
     assign { } { }
     assign $1\issue_fsm_state[2:0] 3'000
     sync always
     sync init
       update \issue_fsm_state $1\issue_fsm_state[2:0]
   end
-  attribute \src "libresoc.v:194310.7-194310.30"
-  process $proc$libresoc.v:194310$14315
+  attribute \src "libresoc.v:194318.7-194318.30"
+  process $proc$libresoc.v:194318$14315
     assign { } { }
     assign $1\jtag_dmi0__ack_o[0:0] 1'0
     sync always
     sync init
       update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0]
   end
-  attribute \src "libresoc.v:194318.14-194318.52"
-  process $proc$libresoc.v:194318$14316
+  attribute \src "libresoc.v:194326.14-194326.52"
+  process $proc$libresoc.v:194326$14316
     assign { } { }
     assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0]
   end
-  attribute \src "libresoc.v:194376.7-194376.22"
-  process $proc$libresoc.v:194376$14317
+  attribute \src "libresoc.v:194384.7-194384.22"
+  process $proc$libresoc.v:194384$14317
     assign { } { }
     assign $1\msr_read[0:0] 1'1
     sync always
     sync init
       update \msr_read $1\msr_read[0:0]
   end
-  attribute \src "libresoc.v:194412.14-194412.40"
-  process $proc$libresoc.v:194412$14318
+  attribute \src "libresoc.v:194420.14-194420.40"
+  process $proc$libresoc.v:194420$14318
     assign { } { }
     assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \nia $1\nia[63:0]
   end
-  attribute \src "libresoc.v:194418.7-194418.24"
-  process $proc$libresoc.v:194418$14319
+  attribute \src "libresoc.v:194426.7-194426.24"
+  process $proc$libresoc.v:194426$14319
     assign { } { }
     assign $1\pc_changed[0:0] 1'0
     sync always
     sync init
       update \pc_changed $1\pc_changed[0:0]
   end
-  attribute \src "libresoc.v:194428.7-194428.25"
-  process $proc$libresoc.v:194428$14320
+  attribute \src "libresoc.v:194436.7-194436.25"
+  process $proc$libresoc.v:194436$14320
     assign { } { }
     assign $1\pc_ok_delay[0:0] 1'0
     sync always
     sync init
       update \pc_ok_delay $1\pc_ok_delay[0:0]
   end
-  attribute \src "libresoc.v:194872.7-194872.24"
-  process $proc$libresoc.v:194872$14321
+  attribute \src "libresoc.v:194880.7-194880.24"
+  process $proc$libresoc.v:194880$14321
     assign { } { }
     assign $1\sv_changed[0:0] 1'0
     sync always
     sync init
       update \sv_changed $1\sv_changed[0:0]
   end
-  attribute \src "libresoc.v:194890.7-194890.30"
-  process $proc$libresoc.v:194890$14322
+  attribute \src "libresoc.v:194898.7-194898.30"
+  process $proc$libresoc.v:194898$14322
     assign { } { }
     assign $1\svstate_ok_delay[0:0] 1'0
     sync always
     sync init
       update \svstate_ok_delay $1\svstate_ok_delay[0:0]
   end
-  attribute \src "libresoc.v:194981.3-194982.41"
-  process $proc$libresoc.v:194981$13486
+  attribute \src "libresoc.v:194989.3-194990.41"
+  process $proc$libresoc.v:194989$13486
     assign { } { }
     assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next
     sync posedge \clk
       update \dec2_cur_dec $0\dec2_cur_dec[63:0]
   end
-  attribute \src "libresoc.v:194983.3-194984.47"
-  process $proc$libresoc.v:194983$13487
+  attribute \src "libresoc.v:194991.3-194992.47"
+  process $proc$libresoc.v:194991$13487
     assign { } { }
     assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next
     sync posedge \clk
       update \core_raw_insn_i $0\core_raw_insn_i[31:0]
   end
-  attribute \src "libresoc.v:194985.3-194986.49"
-  process $proc$libresoc.v:194985$13488
+  attribute \src "libresoc.v:194993.3-194994.49"
+  process $proc$libresoc.v:194993$13488
     assign { } { }
     assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next
     sync posedge \clk
       update \svstate_ok_delay $0\svstate_ok_delay[0:0]
   end
-  attribute \src "libresoc.v:194987.3-194988.39"
-  process $proc$libresoc.v:194987$13489
+  attribute \src "libresoc.v:194995.3-194996.39"
+  process $proc$libresoc.v:194995$13489
     assign { } { }
     assign $0\pc_ok_delay[0:0] \pc_ok_delay$next
     sync posedge \clk
       update \pc_ok_delay $0\pc_ok_delay[0:0]
   end
-  attribute \src "libresoc.v:194989.3-194990.43"
-  process $proc$libresoc.v:194989$13490
+  attribute \src "libresoc.v:194997.3-194998.43"
+  process $proc$libresoc.v:194997$13490
     assign { } { }
     assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o
     sync posedge \clk
       update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0]
   end
-  attribute \src "libresoc.v:194991.3-194992.27"
-  process $proc$libresoc.v:194991$13491
+  attribute \src "libresoc.v:194999.3-195000.27"
+  process $proc$libresoc.v:194999$13491
     assign { } { }
     assign $0\delay[1:0] \delay$next
     sync posedge \por_clk
       update \delay $0\delay[1:0]
   end
-  attribute \src "libresoc.v:194993.3-194994.43"
-  process $proc$libresoc.v:194993$13492
+  attribute \src "libresoc.v:195001.3-195002.43"
+  process $proc$libresoc.v:195001$13492
     assign { } { }
     assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next
     sync posedge \clk
       update \dec2_cur_eint $0\dec2_cur_eint[0:0]
   end
-  attribute \src "libresoc.v:194995.3-194996.47"
-  process $proc$libresoc.v:194995$13493
+  attribute \src "libresoc.v:195003.3-195004.47"
+  process $proc$libresoc.v:195003$13493
     assign { } { }
     assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next
     sync posedge \clk
       update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0]
   end
-  attribute \src "libresoc.v:194997.3-194998.49"
-  process $proc$libresoc.v:194997$13494
+  attribute \src "libresoc.v:195005.3-195006.49"
+  process $proc$libresoc.v:195005$13494
     assign { } { }
     assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next
     sync posedge \clk
       update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0]
   end
-  attribute \src "libresoc.v:194999.3-195000.39"
-  process $proc$libresoc.v:194999$13495
+  attribute \src "libresoc.v:195007.3-195008.39"
+  process $proc$libresoc.v:195007$13495
     assign { } { }
     assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next
     sync posedge \clk
       update \dbg_dmi_din $0\dbg_dmi_din[63:0]
   end
-  attribute \src "libresoc.v:195001.3-195002.41"
-  process $proc$libresoc.v:195001$13496
+  attribute \src "libresoc.v:195009.3-195010.41"
+  process $proc$libresoc.v:195009$13496
     assign { } { }
     assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next
     sync posedge \clk
       update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0]
   end
-  attribute \src "libresoc.v:195003.3-195004.43"
-  process $proc$libresoc.v:195003$13497
+  attribute \src "libresoc.v:195011.3-195012.43"
+  process $proc$libresoc.v:195011$13497
     assign { } { }
     assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next
     sync posedge \clk
       update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0]
   end
-  attribute \src "libresoc.v:195005.3-195006.41"
-  process $proc$libresoc.v:195005$13498
+  attribute \src "libresoc.v:195013.3-195014.41"
+  process $proc$libresoc.v:195013$13498
     assign { } { }
     assign $0\core_core_pc[63:0] \core_core_pc$next
     sync posedge \clk
       update \core_core_pc $0\core_core_pc[63:0]
   end
-  attribute \src "libresoc.v:195007.3-195008.45"
-  process $proc$libresoc.v:195007$13499
+  attribute \src "libresoc.v:195015.3-195016.45"
+  process $proc$libresoc.v:195015$13499
     assign { } { }
     assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next
     sync posedge \clk
       update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0]
   end
-  attribute \src "libresoc.v:195009.3-195010.33"
-  process $proc$libresoc.v:195009$13500
+  attribute \src "libresoc.v:195017.3-195018.33"
+  process $proc$libresoc.v:195017$13500
     assign { } { }
     assign $0\core_msr[63:0] \core_msr$next
     sync posedge \clk
       update \core_msr $0\core_msr[63:0]
   end
-  attribute \src "libresoc.v:195011.3-195012.35"
-  process $proc$libresoc.v:195011$13501
+  attribute \src "libresoc.v:195019.3-195020.35"
+  process $proc$libresoc.v:195019$13501
     assign { } { }
     assign $0\core_eint[0:0] \core_eint$next
     sync posedge \clk
       update \core_eint $0\core_eint[0:0]
   end
-  attribute \src "libresoc.v:195013.3-195014.33"
-  process $proc$libresoc.v:195013$13502
+  attribute \src "libresoc.v:195021.3-195022.33"
+  process $proc$libresoc.v:195021$13502
     assign { } { }
     assign $0\core_dec[63:0] \core_dec$next
     sync posedge \clk
       update \core_dec $0\core_dec[63:0]
   end
-  attribute \src "libresoc.v:195015.3-195016.49"
-  process $proc$libresoc.v:195015$13503
+  attribute \src "libresoc.v:195023.3-195024.49"
+  process $proc$libresoc.v:195023$13503
     assign { } { }
     assign $0\core_core_svstep[1:0] \core_core_svstep$next
     sync posedge \clk
       update \core_core_svstep $0\core_core_svstep[1:0]
   end
-  attribute \src "libresoc.v:195017.3-195018.47"
-  process $proc$libresoc.v:195017$13504
+  attribute \src "libresoc.v:195025.3-195026.47"
+  process $proc$libresoc.v:195025$13504
     assign { } { }
     assign $0\core_core_subvl[1:0] \core_core_subvl$next
     sync posedge \clk
       update \core_core_subvl $0\core_core_subvl[1:0]
   end
-  attribute \src "libresoc.v:195019.3-195020.51"
-  process $proc$libresoc.v:195019$13505
+  attribute \src "libresoc.v:195027.3-195028.51"
+  process $proc$libresoc.v:195027$13505
     assign { } { }
     assign $0\core_core_dststep[6:0] \core_core_dststep$next
     sync posedge \clk
       update \core_core_dststep $0\core_core_dststep[6:0]
   end
-  attribute \src "libresoc.v:195021.3-195022.51"
-  process $proc$libresoc.v:195021$13506
+  attribute \src "libresoc.v:195029.3-195030.51"
+  process $proc$libresoc.v:195029$13506
     assign { } { }
     assign $0\core_core_srcstep[6:0] \core_core_srcstep$next
     sync posedge \clk
       update \core_core_srcstep $0\core_core_srcstep[6:0]
   end
-  attribute \src "libresoc.v:195023.3-195024.41"
-  process $proc$libresoc.v:195023$13507
+  attribute \src "libresoc.v:195031.3-195032.41"
+  process $proc$libresoc.v:195031$13507
     assign { } { }
     assign $0\core_core_vl[6:0] \core_core_vl$next
     sync posedge \clk
       update \core_core_vl $0\core_core_vl[6:0]
   end
-  attribute \src "libresoc.v:195025.3-195026.35"
-  process $proc$libresoc.v:195025$13508
+  attribute \src "libresoc.v:195033.3-195034.35"
+  process $proc$libresoc.v:195033$13508
     assign { } { }
     assign $0\fsm_state[1:0] \fsm_state$next
     sync posedge \clk
       update \fsm_state $0\fsm_state[1:0]
   end
-  attribute \src "libresoc.v:195027.3-195028.47"
-  process $proc$libresoc.v:195027$13509
+  attribute \src "libresoc.v:195035.3-195036.47"
+  process $proc$libresoc.v:195035$13509
     assign { } { }
     assign $0\core_core_maxvl[6:0] \core_core_maxvl$next
     sync posedge \clk
       update \core_core_maxvl $0\core_core_maxvl[6:0]
   end
-  attribute \src "libresoc.v:195029.3-195030.41"
-  process $proc$libresoc.v:195029$13510
+  attribute \src "libresoc.v:195037.3-195038.41"
+  process $proc$libresoc.v:195037$13510
     assign { } { }
     assign $0\core_asmcode[7:0] \core_asmcode$next
     sync posedge \clk
       update \core_asmcode $0\core_asmcode[7:0]
   end
-  attribute \src "libresoc.v:195031.3-195032.45"
-  process $proc$libresoc.v:195031$13511
+  attribute \src "libresoc.v:195039.3-195040.45"
+  process $proc$libresoc.v:195039$13511
     assign { } { }
     assign $0\core_core_rego[6:0] \core_core_rego$next
     sync posedge \clk
       update \core_core_rego $0\core_core_rego[6:0]
   end
-  attribute \src "libresoc.v:195033.3-195034.41"
-  process $proc$libresoc.v:195033$13512
+  attribute \src "libresoc.v:195041.3-195042.41"
+  process $proc$libresoc.v:195041$13512
     assign { } { }
     assign $0\core_rego_ok[0:0] \core_rego_ok$next
     sync posedge \clk
       update \core_rego_ok $0\core_rego_ok[0:0]
   end
-  attribute \src "libresoc.v:195035.3-195036.41"
-  process $proc$libresoc.v:195035$13513
+  attribute \src "libresoc.v:195043.3-195044.41"
+  process $proc$libresoc.v:195043$13513
     assign { } { }
     assign $0\core_core_ea[6:0] \core_core_ea$next
     sync posedge \clk
       update \core_core_ea $0\core_core_ea[6:0]
   end
-  attribute \src "libresoc.v:195037.3-195038.37"
-  process $proc$libresoc.v:195037$13514
+  attribute \src "libresoc.v:195045.3-195046.37"
+  process $proc$libresoc.v:195045$13514
     assign { } { }
     assign $0\core_ea_ok[0:0] \core_ea_ok$next
     sync posedge \clk
       update \core_ea_ok $0\core_ea_ok[0:0]
   end
-  attribute \src "libresoc.v:195039.3-195040.45"
-  process $proc$libresoc.v:195039$13515
+  attribute \src "libresoc.v:195047.3-195048.45"
+  process $proc$libresoc.v:195047$13515
     assign { } { }
     assign $0\core_core_reg1[6:0] \core_core_reg1$next
     sync posedge \clk
       update \core_core_reg1 $0\core_core_reg1[6:0]
   end
-  attribute \src "libresoc.v:195041.3-195042.51"
-  process $proc$libresoc.v:195041$13516
+  attribute \src "libresoc.v:195049.3-195050.51"
+  process $proc$libresoc.v:195049$13516
     assign { } { }
     assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next
     sync posedge \clk
       update \core_core_reg1_ok $0\core_core_reg1_ok[0:0]
   end
-  attribute \src "libresoc.v:195043.3-195044.45"
-  process $proc$libresoc.v:195043$13517
+  attribute \src "libresoc.v:195051.3-195052.45"
+  process $proc$libresoc.v:195051$13517
     assign { } { }
     assign $0\core_core_reg2[6:0] \core_core_reg2$next
     sync posedge \clk
       update \core_core_reg2 $0\core_core_reg2[6:0]
   end
-  attribute \src "libresoc.v:195045.3-195046.51"
-  process $proc$libresoc.v:195045$13518
+  attribute \src "libresoc.v:195053.3-195054.51"
+  process $proc$libresoc.v:195053$13518
     assign { } { }
     assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next
     sync posedge \clk
       update \core_core_reg2_ok $0\core_core_reg2_ok[0:0]
   end
-  attribute \src "libresoc.v:195047.3-195048.39"
-  process $proc$libresoc.v:195047$13519
+  attribute \src "libresoc.v:195055.3-195056.39"
+  process $proc$libresoc.v:195055$13519
     assign { } { }
     assign $0\d_xer_delay[0:0] \d_xer_delay$next
     sync posedge \clk
       update \d_xer_delay $0\d_xer_delay[0:0]
   end
-  attribute \src "libresoc.v:195049.3-195050.45"
-  process $proc$libresoc.v:195049$13520
+  attribute \src "libresoc.v:195057.3-195058.45"
+  process $proc$libresoc.v:195057$13520
     assign { } { }
     assign $0\core_core_reg3[6:0] \core_core_reg3$next
     sync posedge \clk
       update \core_core_reg3 $0\core_core_reg3[6:0]
   end
-  attribute \src "libresoc.v:195051.3-195052.51"
-  process $proc$libresoc.v:195051$13521
+  attribute \src "libresoc.v:195059.3-195060.51"
+  process $proc$libresoc.v:195059$13521
     assign { } { }
     assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next
     sync posedge \clk
       update \core_core_reg3_ok $0\core_core_reg3_ok[0:0]
   end
-  attribute \src "libresoc.v:195053.3-195054.45"
-  process $proc$libresoc.v:195053$13522
+  attribute \src "libresoc.v:195061.3-195062.45"
+  process $proc$libresoc.v:195061$13522
     assign { } { }
     assign $0\core_core_spro[9:0] \core_core_spro$next
     sync posedge \clk
       update \core_core_spro $0\core_core_spro[9:0]
   end
-  attribute \src "libresoc.v:195055.3-195056.41"
-  process $proc$libresoc.v:195055$13523
+  attribute \src "libresoc.v:195063.3-195064.41"
+  process $proc$libresoc.v:195063$13523
     assign { } { }
     assign $0\core_spro_ok[0:0] \core_spro_ok$next
     sync posedge \clk
       update \core_spro_ok $0\core_spro_ok[0:0]
   end
-  attribute \src "libresoc.v:195057.3-195058.45"
-  process $proc$libresoc.v:195057$13524
+  attribute \src "libresoc.v:195065.3-195066.45"
+  process $proc$libresoc.v:195065$13524
     assign { } { }
     assign $0\core_core_spr1[9:0] \core_core_spr1$next
     sync posedge \clk
       update \core_core_spr1 $0\core_core_spr1[9:0]
   end
-  attribute \src "libresoc.v:195059.3-195060.51"
-  process $proc$libresoc.v:195059$13525
+  attribute \src "libresoc.v:195067.3-195068.51"
+  process $proc$libresoc.v:195067$13525
     assign { } { }
     assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next
     sync posedge \clk
       update \core_core_spr1_ok $0\core_core_spr1_ok[0:0]
   end
-  attribute \src "libresoc.v:195061.3-195062.49"
-  process $proc$libresoc.v:195061$13526
+  attribute \src "libresoc.v:195069.3-195070.49"
+  process $proc$libresoc.v:195069$13526
     assign { } { }
     assign $0\core_core_xer_in[2:0] \core_core_xer_in$next
     sync posedge \clk
       update \core_core_xer_in $0\core_core_xer_in[2:0]
   end
-  attribute \src "libresoc.v:195063.3-195064.41"
-  process $proc$libresoc.v:195063$13527
+  attribute \src "libresoc.v:195071.3-195072.41"
+  process $proc$libresoc.v:195071$13527
     assign { } { }
     assign $0\core_xer_out[0:0] \core_xer_out$next
     sync posedge \clk
       update \core_xer_out $0\core_xer_out[0:0]
   end
-  attribute \src "libresoc.v:195065.3-195066.47"
-  process $proc$libresoc.v:195065$13528
+  attribute \src "libresoc.v:195073.3-195074.47"
+  process $proc$libresoc.v:195073$13528
     assign { } { }
     assign $0\core_core_fast1[2:0] \core_core_fast1$next
     sync posedge \clk
       update \core_core_fast1 $0\core_core_fast1[2:0]
   end
-  attribute \src "libresoc.v:195067.3-195068.53"
-  process $proc$libresoc.v:195067$13529
+  attribute \src "libresoc.v:195075.3-195076.53"
+  process $proc$libresoc.v:195075$13529
     assign { } { }
     assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next
     sync posedge \clk
       update \core_core_fast1_ok $0\core_core_fast1_ok[0:0]
   end
-  attribute \src "libresoc.v:195069.3-195070.37"
-  process $proc$libresoc.v:195069$13530
+  attribute \src "libresoc.v:195077.3-195078.37"
+  process $proc$libresoc.v:195077$13530
     assign { } { }
     assign $0\d_cr_delay[0:0] \d_cr_delay$next
     sync posedge \clk
       update \d_cr_delay $0\d_cr_delay[0:0]
   end
-  attribute \src "libresoc.v:195071.3-195072.47"
-  process $proc$libresoc.v:195071$13531
+  attribute \src "libresoc.v:195079.3-195080.47"
+  process $proc$libresoc.v:195079$13531
     assign { } { }
     assign $0\core_core_fast2[2:0] \core_core_fast2$next
     sync posedge \clk
       update \core_core_fast2 $0\core_core_fast2[2:0]
   end
-  attribute \src "libresoc.v:195073.3-195074.53"
-  process $proc$libresoc.v:195073$13532
+  attribute \src "libresoc.v:195081.3-195082.53"
+  process $proc$libresoc.v:195081$13532
     assign { } { }
     assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next
     sync posedge \clk
       update \core_core_fast2_ok $0\core_core_fast2_ok[0:0]
   end
-  attribute \src "libresoc.v:195075.3-195076.49"
-  process $proc$libresoc.v:195075$13533
+  attribute \src "libresoc.v:195083.3-195084.49"
+  process $proc$libresoc.v:195083$13533
     assign { } { }
     assign $0\core_core_fasto1[2:0] \core_core_fasto1$next
     sync posedge \clk
       update \core_core_fasto1 $0\core_core_fasto1[2:0]
   end
-  attribute \src "libresoc.v:195077.3-195078.45"
-  process $proc$libresoc.v:195077$13534
+  attribute \src "libresoc.v:195085.3-195086.45"
+  process $proc$libresoc.v:195085$13534
     assign { } { }
     assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next
     sync posedge \clk
       update \core_fasto1_ok $0\core_fasto1_ok[0:0]
   end
-  attribute \src "libresoc.v:195079.3-195080.49"
-  process $proc$libresoc.v:195079$13535
+  attribute \src "libresoc.v:195087.3-195088.49"
+  process $proc$libresoc.v:195087$13535
     assign { } { }
     assign $0\core_core_fasto2[2:0] \core_core_fasto2$next
     sync posedge \clk
       update \core_core_fasto2 $0\core_core_fasto2[2:0]
   end
-  attribute \src "libresoc.v:195081.3-195082.45"
-  process $proc$libresoc.v:195081$13536
+  attribute \src "libresoc.v:195089.3-195090.45"
+  process $proc$libresoc.v:195089$13536
     assign { } { }
     assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next
     sync posedge \clk
       update \core_fasto2_ok $0\core_fasto2_ok[0:0]
   end
-  attribute \src "libresoc.v:195083.3-195084.49"
-  process $proc$libresoc.v:195083$13537
+  attribute \src "libresoc.v:195091.3-195092.49"
+  process $proc$libresoc.v:195091$13537
     assign { } { }
     assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next
     sync posedge \clk
       update \core_core_cr_in1 $0\core_core_cr_in1[6:0]
   end
-  attribute \src "libresoc.v:195085.3-195086.55"
-  process $proc$libresoc.v:195085$13538
+  attribute \src "libresoc.v:195093.3-195094.55"
+  process $proc$libresoc.v:195093$13538
     assign { } { }
     assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next
     sync posedge \clk
       update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0]
   end
-  attribute \src "libresoc.v:195087.3-195088.49"
-  process $proc$libresoc.v:195087$13539
+  attribute \src "libresoc.v:195095.3-195096.49"
+  process $proc$libresoc.v:195095$13539
     assign { } { }
     assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next
     sync posedge \clk
       update \core_core_cr_in2 $0\core_core_cr_in2[6:0]
   end
-  attribute \src "libresoc.v:195089.3-195090.55"
-  process $proc$libresoc.v:195089$13540
+  attribute \src "libresoc.v:195097.3-195098.55"
+  process $proc$libresoc.v:195097$13540
     assign { } { }
     assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next
     sync posedge \clk
       update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0]
   end
-  attribute \src "libresoc.v:195091.3-195092.39"
-  process $proc$libresoc.v:195091$13541
+  attribute \src "libresoc.v:195099.3-195100.39"
+  process $proc$libresoc.v:195099$13541
     assign { } { }
     assign $0\d_reg_delay[0:0] \d_reg_delay$next
     sync posedge \clk
       update \d_reg_delay $0\d_reg_delay[0:0]
   end
-  attribute \src "libresoc.v:195093.3-195094.55"
-  process $proc$libresoc.v:195093$13542
+  attribute \src "libresoc.v:195101.3-195102.55"
+  process $proc$libresoc.v:195101$13542
     assign { } { }
     assign $0\core_core_cr_in2$1[6:0]$13543 \core_core_cr_in2$1$next
     sync posedge \clk
       update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13543
   end
-  attribute \src "libresoc.v:195095.3-195096.61"
-  process $proc$libresoc.v:195095$13544
+  attribute \src "libresoc.v:195103.3-195104.61"
+  process $proc$libresoc.v:195103$13544
     assign { } { }
     assign $0\core_core_cr_in2_ok$2[0:0]$13545 \core_core_cr_in2_ok$2$next
     sync posedge \clk
       update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13545
   end
-  attribute \src "libresoc.v:195097.3-195098.49"
-  process $proc$libresoc.v:195097$13546
+  attribute \src "libresoc.v:195105.3-195106.49"
+  process $proc$libresoc.v:195105$13546
     assign { } { }
     assign $0\core_core_cr_out[6:0] \core_core_cr_out$next
     sync posedge \clk
       update \core_core_cr_out $0\core_core_cr_out[6:0]
   end
-  attribute \src "libresoc.v:195099.3-195100.45"
-  process $proc$libresoc.v:195099$13547
+  attribute \src "libresoc.v:195107.3-195108.45"
+  process $proc$libresoc.v:195107$13547
     assign { } { }
     assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next
     sync posedge \clk
       update \core_cr_out_ok $0\core_cr_out_ok[0:0]
   end
-  attribute \src "libresoc.v:195101.3-195102.53"
-  process $proc$libresoc.v:195101$13548
+  attribute \src "libresoc.v:195109.3-195110.53"
+  process $proc$libresoc.v:195109$13548
     assign { } { }
     assign $0\core_core_core_msr[63:0] \core_core_core_msr$next
     sync posedge \clk
       update \core_core_core_msr $0\core_core_core_msr[63:0]
   end
-  attribute \src "libresoc.v:195103.3-195104.53"
-  process $proc$libresoc.v:195103$13549
+  attribute \src "libresoc.v:195111.3-195112.53"
+  process $proc$libresoc.v:195111$13549
     assign { } { }
     assign $0\core_core_core_cia[63:0] \core_core_core_cia$next
     sync posedge \clk
       update \core_core_core_cia $0\core_core_core_cia[63:0]
   end
-  attribute \src "libresoc.v:195105.3-195106.55"
-  process $proc$libresoc.v:195105$13550
+  attribute \src "libresoc.v:195113.3-195114.55"
+  process $proc$libresoc.v:195113$13550
     assign { } { }
     assign $0\core_core_core_insn[31:0] \core_core_core_insn$next
     sync posedge \clk
       update \core_core_core_insn $0\core_core_core_insn[31:0]
   end
-  attribute \src "libresoc.v:195107.3-195108.65"
-  process $proc$libresoc.v:195107$13551
+  attribute \src "libresoc.v:195115.3-195116.65"
+  process $proc$libresoc.v:195115$13551
     assign { } { }
     assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next
     sync posedge \clk
       update \core_core_core_insn_type $0\core_core_core_insn_type[6:0]
   end
-  attribute \src "libresoc.v:195109.3-195110.61"
-  process $proc$libresoc.v:195109$13552
+  attribute \src "libresoc.v:195117.3-195118.61"
+  process $proc$libresoc.v:195117$13552
     assign { } { }
     assign $0\core_core_core_fn_unit[12:0] \core_core_core_fn_unit$next
     sync posedge \clk
       update \core_core_core_fn_unit $0\core_core_core_fn_unit[12:0]
   end
-  attribute \src "libresoc.v:195111.3-195112.41"
-  process $proc$libresoc.v:195111$13553
+  attribute \src "libresoc.v:195119.3-195120.41"
+  process $proc$libresoc.v:195119$13553
     assign { } { }
     assign $0\core_core_lk[0:0] \core_core_lk$next
     sync posedge \clk
       update \core_core_lk $0\core_core_lk[0:0]
   end
-  attribute \src "libresoc.v:195113.3-195114.37"
-  process $proc$libresoc.v:195113$13554
+  attribute \src "libresoc.v:195121.3-195122.37"
+  process $proc$libresoc.v:195121$13554
     assign { } { }
     assign $0\pc_changed[0:0] \pc_changed$next
     sync posedge \clk
       update \pc_changed $0\pc_changed[0:0]
   end
-  attribute \src "libresoc.v:195115.3-195116.51"
-  process $proc$libresoc.v:195115$13555
+  attribute \src "libresoc.v:195123.3-195124.51"
+  process $proc$libresoc.v:195123$13555
     assign { } { }
     assign $0\core_core_core_rc[0:0] \core_core_core_rc$next
     sync posedge \clk
       update \core_core_core_rc $0\core_core_core_rc[0:0]
   end
-  attribute \src "libresoc.v:195117.3-195118.57"
-  process $proc$libresoc.v:195117$13556
+  attribute \src "libresoc.v:195125.3-195126.57"
+  process $proc$libresoc.v:195125$13556
     assign { } { }
     assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next
     sync posedge \clk
       update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0]
   end
-  attribute \src "libresoc.v:195119.3-195120.51"
-  process $proc$libresoc.v:195119$13557
+  attribute \src "libresoc.v:195127.3-195128.51"
+  process $proc$libresoc.v:195127$13557
     assign { } { }
     assign $0\core_core_core_oe[0:0] \core_core_core_oe$next
     sync posedge \clk
       update \core_core_core_oe $0\core_core_core_oe[0:0]
   end
-  attribute \src "libresoc.v:195121.3-195122.57"
-  process $proc$libresoc.v:195121$13558
+  attribute \src "libresoc.v:195129.3-195130.57"
+  process $proc$libresoc.v:195129$13558
     assign { } { }
     assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next
     sync posedge \clk
       update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0]
   end
-  attribute \src "libresoc.v:195123.3-195124.69"
-  process $proc$libresoc.v:195123$13559
+  attribute \src "libresoc.v:195131.3-195132.69"
+  process $proc$libresoc.v:195131$13559
     assign { } { }
     assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next
     sync posedge \clk
       update \core_core_core_input_carry $0\core_core_core_input_carry[1:0]
   end
-  attribute \src "libresoc.v:195125.3-195126.63"
-  process $proc$libresoc.v:195125$13560
+  attribute \src "libresoc.v:195133.3-195134.63"
+  process $proc$libresoc.v:195133$13560
     assign { } { }
     assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next
     sync posedge \clk
       update \core_core_core_traptype $0\core_core_core_traptype[7:0]
   end
-  attribute \src "libresoc.v:195127.3-195128.71"
-  process $proc$libresoc.v:195127$13561
+  attribute \src "libresoc.v:195135.3-195136.71"
+  process $proc$libresoc.v:195135$13561
     assign { } { }
     assign $0\core_core_core_exc_$signal[0:0]$13562 \core_core_core_exc_$signal$next
     sync posedge \clk
       update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13562
   end
-  attribute \src "libresoc.v:195129.3-195130.75"
-  process $proc$libresoc.v:195129$13563
+  attribute \src "libresoc.v:195137.3-195138.75"
+  process $proc$libresoc.v:195137$13563
     assign { } { }
     assign $0\core_core_core_exc_$signal$3[0:0]$13564 \core_core_core_exc_$signal$3$next
     sync posedge \clk
       update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13564
   end
-  attribute \src "libresoc.v:195131.3-195132.75"
-  process $proc$libresoc.v:195131$13565
+  attribute \src "libresoc.v:195139.3-195140.75"
+  process $proc$libresoc.v:195139$13565
     assign { } { }
     assign $0\core_core_core_exc_$signal$4[0:0]$13566 \core_core_core_exc_$signal$4$next
     sync posedge \clk
       update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13566
   end
-  attribute \src "libresoc.v:195133.3-195134.75"
-  process $proc$libresoc.v:195133$13567
+  attribute \src "libresoc.v:195141.3-195142.75"
+  process $proc$libresoc.v:195141$13567
     assign { } { }
     assign $0\core_core_core_exc_$signal$5[0:0]$13568 \core_core_core_exc_$signal$5$next
     sync posedge \clk
       update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13568
   end
-  attribute \src "libresoc.v:195135.3-195136.37"
-  process $proc$libresoc.v:195135$13569
+  attribute \src "libresoc.v:195143.3-195144.37"
+  process $proc$libresoc.v:195143$13569
     assign { } { }
     assign $0\sv_changed[0:0] \sv_changed$next
     sync posedge \clk
       update \sv_changed $0\sv_changed[0:0]
   end
-  attribute \src "libresoc.v:195137.3-195138.75"
-  process $proc$libresoc.v:195137$13570
+  attribute \src "libresoc.v:195145.3-195146.75"
+  process $proc$libresoc.v:195145$13570
     assign { } { }
     assign $0\core_core_core_exc_$signal$6[0:0]$13571 \core_core_core_exc_$signal$6$next
     sync posedge \clk
       update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13571
   end
-  attribute \src "libresoc.v:195139.3-195140.75"
-  process $proc$libresoc.v:195139$13572
+  attribute \src "libresoc.v:195147.3-195148.75"
+  process $proc$libresoc.v:195147$13572
     assign { } { }
     assign $0\core_core_core_exc_$signal$7[0:0]$13573 \core_core_core_exc_$signal$7$next
     sync posedge \clk
       update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13573
   end
-  attribute \src "libresoc.v:195141.3-195142.75"
-  process $proc$libresoc.v:195141$13574
+  attribute \src "libresoc.v:195149.3-195150.75"
+  process $proc$libresoc.v:195149$13574
     assign { } { }
     assign $0\core_core_core_exc_$signal$8[0:0]$13575 \core_core_core_exc_$signal$8$next
     sync posedge \clk
       update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13575
   end
-  attribute \src "libresoc.v:195143.3-195144.75"
-  process $proc$libresoc.v:195143$13576
+  attribute \src "libresoc.v:195151.3-195152.75"
+  process $proc$libresoc.v:195151$13576
     assign { } { }
     assign $0\core_core_core_exc_$signal$9[0:0]$13577 \core_core_core_exc_$signal$9$next
     sync posedge \clk
       update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13577
   end
-  attribute \src "libresoc.v:195145.3-195146.63"
-  process $proc$libresoc.v:195145$13578
+  attribute \src "libresoc.v:195153.3-195154.63"
+  process $proc$libresoc.v:195153$13578
     assign { } { }
     assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next
     sync posedge \clk
       update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0]
   end
-  attribute \src "libresoc.v:195147.3-195148.57"
-  process $proc$libresoc.v:195147$13579
+  attribute \src "libresoc.v:195155.3-195156.57"
+  process $proc$libresoc.v:195155$13579
     assign { } { }
     assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next
     sync posedge \clk
       update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0]
   end
-  attribute \src "libresoc.v:195149.3-195150.63"
-  process $proc$libresoc.v:195149$13580
+  attribute \src "libresoc.v:195157.3-195158.63"
+  process $proc$libresoc.v:195157$13580
     assign { } { }
     assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next
     sync posedge \clk
       update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0]
   end
-  attribute \src "libresoc.v:195151.3-195152.57"
-  process $proc$libresoc.v:195151$13581
+  attribute \src "libresoc.v:195159.3-195160.57"
+  process $proc$libresoc.v:195159$13581
     assign { } { }
     assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next
     sync posedge \clk
       update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0]
   end
-  attribute \src "libresoc.v:195153.3-195154.53"
-  process $proc$libresoc.v:195153$13582
+  attribute \src "libresoc.v:195161.3-195162.53"
+  process $proc$libresoc.v:195161$13582
     assign { } { }
     assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next
     sync posedge \clk
       update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0]
   end
-  attribute \src "libresoc.v:195155.3-195156.63"
-  process $proc$libresoc.v:195155$13583
+  attribute \src "libresoc.v:195163.3-195164.63"
+  process $proc$libresoc.v:195163$13583
     assign { } { }
     assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next
     sync posedge \clk
       update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0]
   end
-  attribute \src "libresoc.v:195157.3-195158.45"
-  process $proc$libresoc.v:195157$13584
+  attribute \src "libresoc.v:195165.3-195166.45"
+  process $proc$libresoc.v:195165$13584
     assign { } { }
     assign $0\exec_fsm_state[0:0] \exec_fsm_state$next
     sync posedge \clk
       update \exec_fsm_state $0\exec_fsm_state[0:0]
   end
-  attribute \src "libresoc.v:195159.3-195160.47"
-  process $proc$libresoc.v:195159$13585
+  attribute \src "libresoc.v:195167.3-195168.47"
+  process $proc$libresoc.v:195167$13585
     assign { } { }
     assign $0\issue_fsm_state[2:0] \issue_fsm_state$next
     sync posedge \clk
       update \issue_fsm_state $0\issue_fsm_state[2:0]
   end
-  attribute \src "libresoc.v:195161.3-195162.23"
-  process $proc$libresoc.v:195161$13586
+  attribute \src "libresoc.v:195169.3-195170.23"
+  process $proc$libresoc.v:195169$13586
     assign { } { }
     assign $0\nia[63:0] \nia$next
     sync posedge \clk
       update \nia $0\nia[63:0]
   end
-  attribute \src "libresoc.v:195163.3-195164.47"
-  process $proc$libresoc.v:195163$13587
+  attribute \src "libresoc.v:195171.3-195172.47"
+  process $proc$libresoc.v:195171$13587
     assign { } { }
     assign $0\dec_svp64__mode[4:0] \dec_svp64__mode$next
     sync posedge \clk
       update \dec_svp64__mode $0\dec_svp64__mode[4:0]
   end
-  attribute \src "libresoc.v:195165.3-195166.59"
-  process $proc$libresoc.v:195165$13588
+  attribute \src "libresoc.v:195173.3-195174.59"
+  process $proc$libresoc.v:195173$13588
     assign { } { }
     assign $0\dec2_dec_svp64__extra[8:0] \dec2_dec_svp64__extra$next
     sync posedge \clk
       update \dec2_dec_svp64__extra $0\dec2_dec_svp64__extra[8:0]
   end
-  attribute \src "libresoc.v:195167.3-195168.49"
-  process $proc$libresoc.v:195167$13589
+  attribute \src "libresoc.v:195175.3-195176.49"
+  process $proc$libresoc.v:195175$13589
     assign { } { }
     assign $0\dec_svp64__subvl[1:0] \dec_svp64__subvl$next
     sync posedge \clk
       update \dec_svp64__subvl $0\dec_svp64__subvl[1:0]
   end
-  attribute \src "libresoc.v:195169.3-195170.49"
-  process $proc$libresoc.v:195169$13590
+  attribute \src "libresoc.v:195177.3-195178.49"
+  process $proc$libresoc.v:195177$13590
     assign { } { }
     assign $0\dec_svp64__ewsrc[1:0] \dec_svp64__ewsrc$next
     sync posedge \clk
       update \dec_svp64__ewsrc $0\dec_svp64__ewsrc[1:0]
   end
-  attribute \src "libresoc.v:195171.3-195172.53"
-  process $proc$libresoc.v:195171$13591
+  attribute \src "libresoc.v:195179.3-195180.53"
+  process $proc$libresoc.v:195179$13591
     assign { } { }
     assign $0\dec_svp64__elwidth[1:0] \dec_svp64__elwidth$next
     sync posedge \clk
       update \dec_svp64__elwidth $0\dec_svp64__elwidth[1:0]
   end
-  attribute \src "libresoc.v:195173.3-195174.47"
-  process $proc$libresoc.v:195173$13592
+  attribute \src "libresoc.v:195181.3-195182.47"
+  process $proc$libresoc.v:195181$13592
     assign { } { }
     assign $0\dec_svp64__mask[2:0] \dec_svp64__mask$next
     sync posedge \clk
       update \dec_svp64__mask $0\dec_svp64__mask[2:0]
   end
-  attribute \src "libresoc.v:195175.3-195176.49"
-  process $proc$libresoc.v:195175$13593
+  attribute \src "libresoc.v:195183.3-195184.49"
+  process $proc$libresoc.v:195183$13593
     assign { } { }
     assign $0\dec_svp64__mmode[0:0] \dec_svp64__mmode$next
     sync posedge \clk
       update \dec_svp64__mmode $0\dec_svp64__mmode[0:0]
   end
-  attribute \src "libresoc.v:195177.3-195178.41"
-  process $proc$libresoc.v:195177$13594
+  attribute \src "libresoc.v:195185.3-195186.41"
+  process $proc$libresoc.v:195185$13594
     assign { } { }
     assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next
     sync posedge \clk
       update \dec2_cur_msr $0\dec2_cur_msr[63:0]
   end
-  attribute \src "libresoc.v:195179.3-195180.57"
-  process $proc$libresoc.v:195179$13595
+  attribute \src "libresoc.v:195187.3-195188.57"
+  process $proc$libresoc.v:195187$13595
     assign { } { }
     assign $0\core_bigendian_i$10[0:0]$13596 \core_bigendian_i$10$next
     sync posedge \clk
       update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13596
   end
-  attribute \src "libresoc.v:195181.3-195182.47"
-  process $proc$libresoc.v:195181$13597
+  attribute \src "libresoc.v:195189.3-195190.47"
+  process $proc$libresoc.v:195189$13597
     assign { } { }
     assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next
     sync posedge \clk
       update \fetch_fsm_state $0\fetch_fsm_state[1:0]
   end
-  attribute \src "libresoc.v:195183.3-195184.33"
-  process $proc$libresoc.v:195183$13598
+  attribute \src "libresoc.v:195191.3-195192.33"
+  process $proc$libresoc.v:195191$13598
     assign { } { }
     assign $0\msr_read[0:0] \msr_read$next
     sync posedge \clk
       update \msr_read $0\msr_read[0:0]
   end
-  attribute \src "libresoc.v:195185.3-195186.45"
-  process $proc$libresoc.v:195185$13599
+  attribute \src "libresoc.v:195193.3-195194.45"
+  process $proc$libresoc.v:195193$13599
     assign { } { }
     assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next
     sync posedge \clk
       update \cur_cur_svstep $0\cur_cur_svstep[1:0]
   end
-  attribute \src "libresoc.v:195187.3-195188.43"
-  process $proc$libresoc.v:195187$13600
+  attribute \src "libresoc.v:195195.3-195196.43"
+  process $proc$libresoc.v:195195$13600
     assign { } { }
     assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next
     sync posedge \clk
       update \cur_cur_subvl $0\cur_cur_subvl[1:0]
   end
-  attribute \src "libresoc.v:195189.3-195190.47"
-  process $proc$libresoc.v:195189$13601
+  attribute \src "libresoc.v:195197.3-195198.47"
+  process $proc$libresoc.v:195197$13601
     assign { } { }
     assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next
     sync posedge \clk
       update \cur_cur_dststep $0\cur_cur_dststep[6:0]
   end
-  attribute \src "libresoc.v:195191.3-195192.57"
-  process $proc$libresoc.v:195191$13602
+  attribute \src "libresoc.v:195199.3-195200.57"
+  process $proc$libresoc.v:195199$13602
     assign { } { }
     assign $0\dec2_cur_cur_srcstep[6:0] \dec2_cur_cur_srcstep$next
     sync posedge \clk
       update \dec2_cur_cur_srcstep $0\dec2_cur_cur_srcstep[6:0]
   end
-  attribute \src "libresoc.v:195193.3-195194.37"
-  process $proc$libresoc.v:195193$13603
+  attribute \src "libresoc.v:195201.3-195202.37"
+  process $proc$libresoc.v:195201$13603
     assign { } { }
     assign $0\cur_cur_vl[6:0] \cur_cur_vl$next
     sync posedge \clk
       update \cur_cur_vl $0\cur_cur_vl[6:0]
   end
-  attribute \src "libresoc.v:195195.3-195196.43"
-  process $proc$libresoc.v:195195$13604
+  attribute \src "libresoc.v:195203.3-195204.43"
+  process $proc$libresoc.v:195203$13604
     assign { } { }
     assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next
     sync posedge \clk
       update \cur_cur_maxvl $0\cur_cur_maxvl[6:0]
   end
-  attribute \src "libresoc.v:195197.3-195198.39"
-  process $proc$libresoc.v:195197$13605
+  attribute \src "libresoc.v:195205.3-195206.39"
+  process $proc$libresoc.v:195205$13605
     assign { } { }
     assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next
     sync posedge \clk
       update \dec2_cur_pc $0\dec2_cur_pc[63:0]
   end
-  attribute \src "libresoc.v:195199.3-195200.40"
-  process $proc$libresoc.v:195199$13606
+  attribute \src "libresoc.v:195207.3-195208.40"
+  process $proc$libresoc.v:195207$13606
     assign { } { }
     assign $0\dec2_raw_opcode_in[31:0] \fetch_insn_o
     sync posedge \clk
       update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0]
   end
-  attribute \src "libresoc.v:195831.3-195839.6"
-  process $proc$libresoc.v:195831$13607
+  attribute \src "libresoc.v:195839.3-195847.6"
+  process $proc$libresoc.v:195839$13607
     assign { } { }
     assign { } { }
     assign $0\dbg_dmi_addr_i$next[3:0]$13608 $1\dbg_dmi_addr_i$next[3:0]$13609
-    attribute \src "libresoc.v:195832.5-195832.29"
+    attribute \src "libresoc.v:195840.5-195840.29"
     switch \initial
-      attribute \src "libresoc.v:195832.9-195832.17"
+      attribute \src "libresoc.v:195840.9-195840.17"
       case 1'1
       case 
     end
@@ -409160,14 +409168,14 @@ module \ti
     sync always
       update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13608
   end
-  attribute \src "libresoc.v:195840.3-195848.6"
-  process $proc$libresoc.v:195840$13610
+  attribute \src "libresoc.v:195848.3-195856.6"
+  process $proc$libresoc.v:195848$13610
     assign { } { }
     assign { } { }
     assign $0\dbg_dmi_req_i$next[0:0]$13611 $1\dbg_dmi_req_i$next[0:0]$13612
-    attribute \src "libresoc.v:195841.5-195841.29"
+    attribute \src "libresoc.v:195849.5-195849.29"
     switch \initial
-      attribute \src "libresoc.v:195841.9-195841.17"
+      attribute \src "libresoc.v:195849.9-195849.17"
       case 1'1
       case 
     end
@@ -409183,14 +409191,14 @@ module \ti
     sync always
       update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13611
   end
-  attribute \src "libresoc.v:195849.3-195857.6"
-  process $proc$libresoc.v:195849$13613
+  attribute \src "libresoc.v:195857.3-195865.6"
+  process $proc$libresoc.v:195857$13613
     assign { } { }
     assign { } { }
     assign $0\dec2_cur_eint$next[0:0]$13614 $1\dec2_cur_eint$next[0:0]$13615
-    attribute \src "libresoc.v:195850.5-195850.29"
+    attribute \src "libresoc.v:195858.5-195858.29"
     switch \initial
-      attribute \src "libresoc.v:195850.9-195850.17"
+      attribute \src "libresoc.v:195858.9-195858.17"
       case 1'1
       case 
     end
@@ -409206,18 +409214,18 @@ module \ti
     sync always
       update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13614
   end
-  attribute \src "libresoc.v:195858.3-195867.6"
-  process $proc$libresoc.v:195858$13616
+  attribute \src "libresoc.v:195866.3-195875.6"
+  process $proc$libresoc.v:195866$13616
     assign { } { }
     assign { } { }
     assign $0\delay$next[1:0]$13617 $1\delay$next[1:0]$13618
-    attribute \src "libresoc.v:195859.5-195859.29"
+    attribute \src "libresoc.v:195867.5-195867.29"
     switch \initial
-      attribute \src "libresoc.v:195859.9-195859.17"
+      attribute \src "libresoc.v:195867.9-195867.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:452"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:453"
     switch \$23
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -409229,8 +409237,8 @@ module \ti
     sync always
       update \delay$next $0\delay$next[1:0]$13617
   end
-  attribute \src "libresoc.v:195868.3-195908.6"
-  process $proc$libresoc.v:195868$13619
+  attribute \src "libresoc.v:195876.3-195916.6"
+  process $proc$libresoc.v:195876$13619
     assign { } { }
     assign { } { }
     assign { } { }
@@ -409271,13 +409279,13 @@ module \ti
     assign $0\core_dec$next[63:0]$13627 $3\core_dec$next[63:0]$13657
     assign $0\core_eint$next[0:0]$13628 $3\core_eint$next[0:0]$13658
     assign $0\core_msr$next[63:0]$13629 $3\core_msr$next[63:0]$13659
-    attribute \src "libresoc.v:195869.5-195869.29"
+    attribute \src "libresoc.v:195877.5-195877.29"
     switch \initial
-      attribute \src "libresoc.v:195869.9-195869.17"
+      attribute \src "libresoc.v:195877.9-195877.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
     switch \issue_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 3'010
@@ -409301,7 +409309,7 @@ module \ti
         assign $1\core_dec$next[63:0]$13637 $2\core_dec$next[63:0]$13647
         assign $1\core_eint$next[0:0]$13638 $2\core_eint$next[0:0]$13648
         assign $1\core_msr$next[63:0]$13639 $2\core_msr$next[63:0]$13649
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296"
         switch \fetch_insn_valid_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409388,26 +409396,26 @@ module \ti
       update \core_eint$next $0\core_eint$next[0:0]$13628
       update \core_msr$next $0\core_msr$next[63:0]$13629
   end
-  attribute \src "libresoc.v:195909.3-195941.6"
-  process $proc$libresoc.v:195909$13660
+  attribute \src "libresoc.v:195917.3-195949.6"
+  process $proc$libresoc.v:195917$13660
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\core_raw_insn_i$next[31:0]$13661 $5\core_raw_insn_i$next[31:0]$13666
-    attribute \src "libresoc.v:195910.5-195910.29"
+    attribute \src "libresoc.v:195918.5-195918.29"
     switch \initial
-      attribute \src "libresoc.v:195910.9-195910.17"
+      attribute \src "libresoc.v:195918.9-195918.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
     switch \issue_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 3'010
         assign { } { }
         assign $1\core_raw_insn_i$next[31:0]$13662 $2\core_raw_insn_i$next[31:0]$13663
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296"
         switch \fetch_insn_valid_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409419,13 +409427,13 @@ module \ti
       case 
         assign $1\core_raw_insn_i$next[31:0]$13662 \core_raw_insn_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
     switch \exec_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
         assign { } { }
         assign $3\core_raw_insn_i$next[31:0]$13664 $4\core_raw_insn_i$next[31:0]$13665
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
         switch \$135
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409449,26 +409457,26 @@ module \ti
     sync always
       update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13661
   end
-  attribute \src "libresoc.v:195942.3-195974.6"
-  process $proc$libresoc.v:195942$13667
+  attribute \src "libresoc.v:195950.3-195982.6"
+  process $proc$libresoc.v:195950$13667
     assign { } { }
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\core_bigendian_i$10$next[0:0]$13668 $5\core_bigendian_i$10$next[0:0]$13673
-    attribute \src "libresoc.v:195943.5-195943.29"
+    attribute \src "libresoc.v:195951.5-195951.29"
     switch \initial
-      attribute \src "libresoc.v:195943.9-195943.17"
+      attribute \src "libresoc.v:195951.9-195951.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
     switch \issue_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 3'010
         assign { } { }
         assign $1\core_bigendian_i$10$next[0:0]$13669 $2\core_bigendian_i$10$next[0:0]$13670
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296"
         switch \fetch_insn_valid_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409480,13 +409488,13 @@ module \ti
       case 
         assign $1\core_bigendian_i$10$next[0:0]$13669 \core_bigendian_i$10
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
     switch \exec_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
         assign { } { }
         assign $3\core_bigendian_i$10$next[0:0]$13671 $4\core_bigendian_i$10$next[0:0]$13672
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
         switch \$137
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409510,18 +409518,18 @@ module \ti
     sync always
       update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13668
   end
-  attribute \src "libresoc.v:195975.3-195985.6"
-  process $proc$libresoc.v:195975$13674
+  attribute \src "libresoc.v:195983.3-195993.6"
+  process $proc$libresoc.v:195983$13674
     assign { } { }
     assign { } { }
     assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0]
-    attribute \src "libresoc.v:195976.5-195976.29"
+    attribute \src "libresoc.v:195984.5-195984.29"
     switch \initial
-      attribute \src "libresoc.v:195976.9-195976.17"
+      attribute \src "libresoc.v:195984.9-195984.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
     switch \issue_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 3'011
@@ -409533,24 +409541,24 @@ module \ti
     sync always
       update \exec_insn_valid_i $0\exec_insn_valid_i[0:0]
   end
-  attribute \src "libresoc.v:195986.3-196001.6"
-  process $proc$libresoc.v:195986$13675
+  attribute \src "libresoc.v:195994.3-196009.6"
+  process $proc$libresoc.v:195994$13675
     assign { } { }
     assign { } { }
     assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0]
-    attribute \src "libresoc.v:195987.5-195987.29"
+    attribute \src "libresoc.v:195995.5-195995.29"
     switch \initial
-      attribute \src "libresoc.v:195987.9-195987.17"
+      attribute \src "libresoc.v:195995.9-195995.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
     switch \issue_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 3'100
         assign { } { }
         assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
         switch \$143
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409565,18 +409573,18 @@ module \ti
     sync always
       update \exec_pc_valid_o $0\exec_pc_valid_o[0:0]
   end
-  attribute \src "libresoc.v:196002.3-196011.6"
-  process $proc$libresoc.v:196002$13676
+  attribute \src "libresoc.v:196010.3-196019.6"
+  process $proc$libresoc.v:196010$13676
     assign { } { }
     assign { } { }
     assign $0\core_wen$11[2:0]$13677 $1\core_wen$11[2:0]$13678
-    attribute \src "libresoc.v:196003.5-196003.29"
+    attribute \src "libresoc.v:196011.5-196011.29"
     switch \initial
-      attribute \src "libresoc.v:196003.9-196003.17"
+      attribute \src "libresoc.v:196011.9-196011.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341"
     switch \update_svstate
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -409588,18 +409596,18 @@ module \ti
     sync always
       update \core_wen$11 $0\core_wen$11[2:0]$13677
   end
-  attribute \src "libresoc.v:196012.3-196021.6"
-  process $proc$libresoc.v:196012$13679
+  attribute \src "libresoc.v:196020.3-196029.6"
+  process $proc$libresoc.v:196020$13679
     assign { } { }
     assign { } { }
     assign $0\core_data_i$12[63:0]$13680 $1\core_data_i$12[63:0]$13681
-    attribute \src "libresoc.v:196013.5-196013.29"
+    attribute \src "libresoc.v:196021.5-196021.29"
     switch \initial
-      attribute \src "libresoc.v:196013.9-196013.17"
+      attribute \src "libresoc.v:196021.9-196021.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341"
     switch \update_svstate
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -409611,18 +409619,18 @@ module \ti
     sync always
       update \core_data_i$12 $0\core_data_i$12[63:0]$13680
   end
-  attribute \src "libresoc.v:196022.3-196032.6"
-  process $proc$libresoc.v:196022$13682
+  attribute \src "libresoc.v:196030.3-196040.6"
+  process $proc$libresoc.v:196030$13682
     assign { } { }
     assign { } { }
     assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0]
-    attribute \src "libresoc.v:196023.5-196023.29"
+    attribute \src "libresoc.v:196031.5-196031.29"
     switch \initial
-      attribute \src "libresoc.v:196023.9-196023.17"
+      attribute \src "libresoc.v:196031.9-196031.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
     switch \exec_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 1'0
@@ -409634,24 +409642,24 @@ module \ti
     sync always
       update \exec_insn_ready_o $0\exec_insn_ready_o[0:0]
   end
-  attribute \src "libresoc.v:196033.3-196057.6"
-  process $proc$libresoc.v:196033$13683
+  attribute \src "libresoc.v:196041.3-196065.6"
+  process $proc$libresoc.v:196041$13683
     assign { } { }
     assign { } { }
     assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0]
-    attribute \src "libresoc.v:196034.5-196034.29"
+    attribute \src "libresoc.v:196042.5-196042.29"
     switch \initial
-      attribute \src "libresoc.v:196034.9-196034.17"
+      attribute \src "libresoc.v:196042.9-196042.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
     switch \exec_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 1'0
         assign { } { }
         assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:372"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373"
         switch \exec_insn_valid_i
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409664,7 +409672,7 @@ module \ti
       case 1'1
         assign { } { }
         assign $1\core_ivalid_i[0:0] $3\core_ivalid_i[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:379"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380"
         switch \$147
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409679,24 +409687,24 @@ module \ti
     sync always
       update \core_ivalid_i $0\core_ivalid_i[0:0]
   end
-  attribute \src "libresoc.v:196058.3-196073.6"
-  process $proc$libresoc.v:196058$13684
+  attribute \src "libresoc.v:196066.3-196081.6"
+  process $proc$libresoc.v:196066$13684
     assign { } { }
     assign { } { }
     assign $0\core_issue_i[0:0] $1\core_issue_i[0:0]
-    attribute \src "libresoc.v:196059.5-196059.29"
+    attribute \src "libresoc.v:196067.5-196067.29"
     switch \initial
-      attribute \src "libresoc.v:196059.9-196059.17"
+      attribute \src "libresoc.v:196067.9-196067.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
     switch \exec_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 1'0
         assign { } { }
         assign $1\core_issue_i[0:0] $2\core_issue_i[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:372"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373"
         switch \exec_insn_valid_i
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409711,25 +409719,25 @@ module \ti
     sync always
       update \core_issue_i $0\core_issue_i[0:0]
   end
-  attribute \src "libresoc.v:196074.3-196108.6"
-  process $proc$libresoc.v:196074$13685
+  attribute \src "libresoc.v:196082.3-196116.6"
+  process $proc$libresoc.v:196082$13685
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\exec_fsm_state$next[0:0]$13686 $5\exec_fsm_state$next[0:0]$13691
-    attribute \src "libresoc.v:196075.5-196075.29"
+    attribute \src "libresoc.v:196083.5-196083.29"
     switch \initial
-      attribute \src "libresoc.v:196075.9-196075.17"
+      attribute \src "libresoc.v:196083.9-196083.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
     switch \exec_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 1'0
         assign { } { }
         assign $1\exec_fsm_state$next[0:0]$13687 $2\exec_fsm_state$next[0:0]$13688
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:372"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373"
         switch \exec_insn_valid_i
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409742,13 +409750,13 @@ module \ti
       case 1'1
         assign { } { }
         assign $1\exec_fsm_state$next[0:0]$13687 $3\exec_fsm_state$next[0:0]$13689
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
         switch \$149
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
             assign { } { }
             assign $3\exec_fsm_state$next[0:0]$13689 $4\exec_fsm_state$next[0:0]$13690
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:394"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:395"
             switch \exec_pc_valid_o
               attribute \src "libresoc.v:0.0-0.0"
               case 1'1
@@ -409775,26 +409783,26 @@ module \ti
     sync always
       update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13686
   end
-  attribute \src "libresoc.v:196109.3-196137.6"
-  process $proc$libresoc.v:196109$13692
+  attribute \src "libresoc.v:196117.3-196145.6"
+  process $proc$libresoc.v:196117$13692
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\sv_changed$next[0:0]$13693 $4\sv_changed$next[0:0]$13697
-    attribute \src "libresoc.v:196110.5-196110.29"
+    attribute \src "libresoc.v:196118.5-196118.29"
     switch \initial
-      attribute \src "libresoc.v:196110.9-196110.17"
+      attribute \src "libresoc.v:196118.9-196118.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
     switch \exec_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
         assign { } { }
         assign { } { }
         assign $1\sv_changed$next[0:0]$13694 $3\sv_changed$next[0:0]$13696
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:382"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:383"
         switch \$151
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409803,7 +409811,7 @@ module \ti
           case 
             assign $2\sv_changed$next[0:0]$13695 \sv_changed
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
         switch \$155
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409827,26 +409835,26 @@ module \ti
     sync always
       update \sv_changed$next $0\sv_changed$next[0:0]$13693
   end
-  attribute \src "libresoc.v:196138.3-196166.6"
-  process $proc$libresoc.v:196138$13698
+  attribute \src "libresoc.v:196146.3-196174.6"
+  process $proc$libresoc.v:196146$13698
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\pc_changed$next[0:0]$13699 $4\pc_changed$next[0:0]$13703
-    attribute \src "libresoc.v:196139.5-196139.29"
+    attribute \src "libresoc.v:196147.5-196147.29"
     switch \initial
-      attribute \src "libresoc.v:196139.9-196139.17"
+      attribute \src "libresoc.v:196147.9-196147.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
     switch \exec_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
         assign { } { }
         assign { } { }
         assign $1\pc_changed$next[0:0]$13700 $3\pc_changed$next[0:0]$13702
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:384"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385"
         switch \$157
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409855,7 +409863,7 @@ module \ti
           case 
             assign $2\pc_changed$next[0:0]$13701 \pc_changed
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
         switch \$161
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409879,24 +409887,24 @@ module \ti
     sync always
       update \pc_changed$next $0\pc_changed$next[0:0]$13699
   end
-  attribute \src "libresoc.v:196167.3-196182.6"
-  process $proc$libresoc.v:196167$13704
+  attribute \src "libresoc.v:196175.3-196190.6"
+  process $proc$libresoc.v:196175$13704
     assign { } { }
     assign { } { }
     assign $0\insn_done[0:0] $1\insn_done[0:0]
-    attribute \src "libresoc.v:196168.5-196168.29"
+    attribute \src "libresoc.v:196176.5-196176.29"
     switch \initial
-      attribute \src "libresoc.v:196168.9-196168.17"
+      attribute \src "libresoc.v:196176.9-196176.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
     switch \exec_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
         assign { } { }
         assign $1\insn_done[0:0] $2\insn_done[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
         switch \$163
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409911,24 +409919,24 @@ module \ti
     sync always
       update \insn_done $0\insn_done[0:0]
   end
-  attribute \src "libresoc.v:196183.3-196198.6"
-  process $proc$libresoc.v:196183$13705
+  attribute \src "libresoc.v:196191.3-196206.6"
+  process $proc$libresoc.v:196191$13705
     assign { } { }
     assign { } { }
     assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0]
-    attribute \src "libresoc.v:196184.5-196184.29"
+    attribute \src "libresoc.v:196192.5-196192.29"
     switch \initial
-      attribute \src "libresoc.v:196184.9-196184.17"
+      attribute \src "libresoc.v:196192.9-196192.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
     switch \exec_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
         assign { } { }
         assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
         switch \$165
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -409943,18 +409951,18 @@ module \ti
     sync always
       update \exec_pc_ready_i $0\exec_pc_ready_i[0:0]
   end
-  attribute \src "libresoc.v:196199.3-196208.6"
-  process $proc$libresoc.v:196199$13706
+  attribute \src "libresoc.v:196207.3-196216.6"
+  process $proc$libresoc.v:196207$13706
     assign { } { }
     assign { } { }
     assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0]
-    attribute \src "libresoc.v:196200.5-196200.29"
+    attribute \src "libresoc.v:196208.5-196208.29"
     switch \initial
-      attribute \src "libresoc.v:196200.9-196200.17"
+      attribute \src "libresoc.v:196208.9-196208.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:569"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:570"
     switch \dbg_d_gpr_req
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -409966,18 +409974,18 @@ module \ti
     sync always
       update \core_dmi__addr $0\core_dmi__addr[4:0]
   end
-  attribute \src "libresoc.v:196209.3-196218.6"
-  process $proc$libresoc.v:196209$13707
+  attribute \src "libresoc.v:196217.3-196226.6"
+  process $proc$libresoc.v:196217$13707
     assign { } { }
     assign { } { }
     assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0]
-    attribute \src "libresoc.v:196210.5-196210.29"
+    attribute \src "libresoc.v:196218.5-196218.29"
     switch \initial
-      attribute \src "libresoc.v:196210.9-196210.17"
+      attribute \src "libresoc.v:196218.9-196218.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:569"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:570"
     switch \dbg_d_gpr_req
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -409989,14 +409997,14 @@ module \ti
     sync always
       update \core_dmi__ren $0\core_dmi__ren[0:0]
   end
-  attribute \src "libresoc.v:196219.3-196227.6"
-  process $proc$libresoc.v:196219$13708
+  attribute \src "libresoc.v:196227.3-196235.6"
+  process $proc$libresoc.v:196227$13708
     assign { } { }
     assign { } { }
     assign $0\d_reg_delay$next[0:0]$13709 $1\d_reg_delay$next[0:0]$13710
-    attribute \src "libresoc.v:196220.5-196220.29"
+    attribute \src "libresoc.v:196228.5-196228.29"
     switch \initial
-      attribute \src "libresoc.v:196220.9-196220.17"
+      attribute \src "libresoc.v:196228.9-196228.17"
       case 1'1
       case 
     end
@@ -410012,18 +410020,18 @@ module \ti
     sync always
       update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13709
   end
-  attribute \src "libresoc.v:196228.3-196237.6"
-  process $proc$libresoc.v:196228$13711
+  attribute \src "libresoc.v:196236.3-196245.6"
+  process $proc$libresoc.v:196236$13711
     assign { } { }
     assign { } { }
     assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0]
-    attribute \src "libresoc.v:196229.5-196229.29"
+    attribute \src "libresoc.v:196237.5-196237.29"
     switch \initial
-      attribute \src "libresoc.v:196229.9-196229.17"
+      attribute \src "libresoc.v:196237.9-196237.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580"
     switch \d_reg_delay
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -410035,18 +410043,18 @@ module \ti
     sync always
       update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0]
   end
-  attribute \src "libresoc.v:196238.3-196247.6"
-  process $proc$libresoc.v:196238$13712
+  attribute \src "libresoc.v:196246.3-196255.6"
+  process $proc$libresoc.v:196246$13712
     assign { } { }
     assign { } { }
     assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0]
-    attribute \src "libresoc.v:196239.5-196239.29"
+    attribute \src "libresoc.v:196247.5-196247.29"
     switch \initial
-      attribute \src "libresoc.v:196239.9-196239.17"
+      attribute \src "libresoc.v:196247.9-196247.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580"
     switch \d_reg_delay
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -410058,18 +410066,18 @@ module \ti
     sync always
       update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0]
   end
-  attribute \src "libresoc.v:196248.3-196257.6"
-  process $proc$libresoc.v:196248$13713
+  attribute \src "libresoc.v:196256.3-196265.6"
+  process $proc$libresoc.v:196256$13713
     assign { } { }
     assign { } { }
     assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0]
-    attribute \src "libresoc.v:196249.5-196249.29"
+    attribute \src "libresoc.v:196257.5-196257.29"
     switch \initial
-      attribute \src "libresoc.v:196249.9-196249.17"
+      attribute \src "libresoc.v:196257.9-196257.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:586"
     switch \dbg_d_cr_req
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -410081,14 +410089,14 @@ module \ti
     sync always
       update \core_full_rd2__ren $0\core_full_rd2__ren[7:0]
   end
-  attribute \src "libresoc.v:196258.3-196266.6"
-  process $proc$libresoc.v:196258$13714
+  attribute \src "libresoc.v:196266.3-196274.6"
+  process $proc$libresoc.v:196266$13714
     assign { } { }
     assign { } { }
     assign $0\d_cr_delay$next[0:0]$13715 $1\d_cr_delay$next[0:0]$13716
-    attribute \src "libresoc.v:196259.5-196259.29"
+    attribute \src "libresoc.v:196267.5-196267.29"
     switch \initial
-      attribute \src "libresoc.v:196259.9-196259.17"
+      attribute \src "libresoc.v:196267.9-196267.17"
       case 1'1
       case 
     end
@@ -410104,18 +410112,18 @@ module \ti
     sync always
       update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13715
   end
-  attribute \src "libresoc.v:196267.3-196276.6"
-  process $proc$libresoc.v:196267$13717
+  attribute \src "libresoc.v:196275.3-196284.6"
+  process $proc$libresoc.v:196275$13717
     assign { } { }
     assign { } { }
     assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0]
-    attribute \src "libresoc.v:196268.5-196268.29"
+    attribute \src "libresoc.v:196276.5-196276.29"
     switch \initial
-      attribute \src "libresoc.v:196268.9-196268.17"
+      attribute \src "libresoc.v:196276.9-196276.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:589"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:590"
     switch \d_cr_delay
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -410127,18 +410135,18 @@ module \ti
     sync always
       update \dbg_d_cr_data $0\dbg_d_cr_data[63:0]
   end
-  attribute \src "libresoc.v:196277.3-196286.6"
-  process $proc$libresoc.v:196277$13718
+  attribute \src "libresoc.v:196285.3-196294.6"
+  process $proc$libresoc.v:196285$13718
     assign { } { }
     assign { } { }
     assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0]
-    attribute \src "libresoc.v:196278.5-196278.29"
+    attribute \src "libresoc.v:196286.5-196286.29"
     switch \initial
-      attribute \src "libresoc.v:196278.9-196278.17"
+      attribute \src "libresoc.v:196286.9-196286.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:589"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:590"
     switch \d_cr_delay
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -410150,18 +410158,18 @@ module \ti
     sync always
       update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0]
   end
-  attribute \src "libresoc.v:196287.3-196296.6"
-  process $proc$libresoc.v:196287$13719
+  attribute \src "libresoc.v:196295.3-196304.6"
+  process $proc$libresoc.v:196295$13719
     assign { } { }
     assign { } { }
     assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0]
-    attribute \src "libresoc.v:196288.5-196288.29"
+    attribute \src "libresoc.v:196296.5-196296.29"
     switch \initial
-      attribute \src "libresoc.v:196288.9-196288.17"
+      attribute \src "libresoc.v:196296.9-196296.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:596"
     switch \dbg_d_xer_req
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -410173,14 +410181,14 @@ module \ti
     sync always
       update \core_full_rd__ren $0\core_full_rd__ren[2:0]
   end
-  attribute \src "libresoc.v:196297.3-196305.6"
-  process $proc$libresoc.v:196297$13720
+  attribute \src "libresoc.v:196305.3-196313.6"
+  process $proc$libresoc.v:196305$13720
     assign { } { }
     assign { } { }
     assign $0\d_xer_delay$next[0:0]$13721 $1\d_xer_delay$next[0:0]$13722
-    attribute \src "libresoc.v:196298.5-196298.29"
+    attribute \src "libresoc.v:196306.5-196306.29"
     switch \initial
-      attribute \src "libresoc.v:196298.9-196298.17"
+      attribute \src "libresoc.v:196306.9-196306.17"
       case 1'1
       case 
     end
@@ -410196,18 +410204,18 @@ module \ti
     sync always
       update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13721
   end
-  attribute \src "libresoc.v:196306.3-196315.6"
-  process $proc$libresoc.v:196306$13723
+  attribute \src "libresoc.v:196314.3-196323.6"
+  process $proc$libresoc.v:196314$13723
     assign { } { }
     assign { } { }
     assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0]
-    attribute \src "libresoc.v:196307.5-196307.29"
+    attribute \src "libresoc.v:196315.5-196315.29"
     switch \initial
-      attribute \src "libresoc.v:196307.9-196307.17"
+      attribute \src "libresoc.v:196315.9-196315.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600"
     switch \d_xer_delay
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -410219,18 +410227,18 @@ module \ti
     sync always
       update \dbg_d_xer_data $0\dbg_d_xer_data[63:0]
   end
-  attribute \src "libresoc.v:196316.3-196325.6"
-  process $proc$libresoc.v:196316$13724
+  attribute \src "libresoc.v:196324.3-196333.6"
+  process $proc$libresoc.v:196324$13724
     assign { } { }
     assign { } { }
     assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0]
-    attribute \src "libresoc.v:196317.5-196317.29"
+    attribute \src "libresoc.v:196325.5-196325.29"
     switch \initial
-      attribute \src "libresoc.v:196317.9-196317.17"
+      attribute \src "libresoc.v:196325.9-196325.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600"
     switch \d_xer_delay
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -410242,18 +410250,18 @@ module \ti
     sync always
       update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0]
   end
-  attribute \src "libresoc.v:196326.3-196340.6"
-  process $proc$libresoc.v:196326$13725
+  attribute \src "libresoc.v:196334.3-196348.6"
+  process $proc$libresoc.v:196334$13725
     assign { } { }
     assign { } { }
     assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0]
-    attribute \src "libresoc.v:196327.5-196327.29"
+    attribute \src "libresoc.v:196335.5-196335.29"
     switch \initial
-      attribute \src "libresoc.v:196327.9-196327.17"
+      attribute \src "libresoc.v:196335.9-196335.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
     switch \fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'00
@@ -410269,18 +410277,18 @@ module \ti
     sync always
       update \core_issue__addr $0\core_issue__addr[2:0]
   end
-  attribute \src "libresoc.v:196341.3-196355.6"
-  process $proc$libresoc.v:196341$13726
+  attribute \src "libresoc.v:196349.3-196363.6"
+  process $proc$libresoc.v:196349$13726
     assign { } { }
     assign { } { }
     assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0]
-    attribute \src "libresoc.v:196342.5-196342.29"
+    attribute \src "libresoc.v:196350.5-196350.29"
     switch \initial
-      attribute \src "libresoc.v:196342.9-196342.17"
+      attribute \src "libresoc.v:196350.9-196350.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
     switch \fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'00
@@ -410296,19 +410304,19 @@ module \ti
     sync always
       update \core_issue__ren $0\core_issue__ren[0:0]
   end
-  attribute \src "libresoc.v:196356.3-196383.6"
-  process $proc$libresoc.v:196356$13727
+  attribute \src "libresoc.v:196364.3-196391.6"
+  process $proc$libresoc.v:196364$13727
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\fsm_state$next[1:0]$13728 $2\fsm_state$next[1:0]$13730
-    attribute \src "libresoc.v:196357.5-196357.29"
+    attribute \src "libresoc.v:196365.5-196365.29"
     switch \initial
-      attribute \src "libresoc.v:196357.9-196357.17"
+      attribute \src "libresoc.v:196365.9-196365.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
     switch \fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'00
@@ -410341,18 +410349,18 @@ module \ti
     sync always
       update \fsm_state$next $0\fsm_state$next[1:0]$13728
   end
-  attribute \src "libresoc.v:196384.3-196394.6"
-  process $proc$libresoc.v:196384$13731
+  attribute \src "libresoc.v:196392.3-196402.6"
+  process $proc$libresoc.v:196392$13731
     assign { } { }
     assign { } { }
     assign $0\new_dec[63:0] $1\new_dec[63:0]
-    attribute \src "libresoc.v:196385.5-196385.29"
+    attribute \src "libresoc.v:196393.5-196393.29"
     switch \initial
-      attribute \src "libresoc.v:196385.9-196385.17"
+      attribute \src "libresoc.v:196393.9-196393.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
     switch \fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'01
@@ -410364,18 +410372,18 @@ module \ti
     sync always
       update \new_dec $0\new_dec[63:0]
   end
-  attribute \src "libresoc.v:196395.3-196409.6"
-  process $proc$libresoc.v:196395$13732
+  attribute \src "libresoc.v:196403.3-196417.6"
+  process $proc$libresoc.v:196403$13732
     assign { } { }
     assign { } { }
     assign $0\core_issue__addr$13[2:0]$13733 $1\core_issue__addr$13[2:0]$13734
-    attribute \src "libresoc.v:196396.5-196396.29"
+    attribute \src "libresoc.v:196404.5-196404.29"
     switch \initial
-      attribute \src "libresoc.v:196396.9-196396.17"
+      attribute \src "libresoc.v:196404.9-196404.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
     switch \fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'01
@@ -410391,18 +410399,18 @@ module \ti
     sync always
       update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13733
   end
-  attribute \src "libresoc.v:196410.3-196424.6"
-  process $proc$libresoc.v:196410$13735
+  attribute \src "libresoc.v:196418.3-196432.6"
+  process $proc$libresoc.v:196418$13735
     assign { } { }
     assign { } { }
     assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0]
-    attribute \src "libresoc.v:196411.5-196411.29"
+    attribute \src "libresoc.v:196419.5-196419.29"
     switch \initial
-      attribute \src "libresoc.v:196411.9-196411.17"
+      attribute \src "libresoc.v:196419.9-196419.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
     switch \fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'01
@@ -410418,18 +410426,18 @@ module \ti
     sync always
       update \core_issue__wen $0\core_issue__wen[0:0]
   end
-  attribute \src "libresoc.v:196425.3-196439.6"
-  process $proc$libresoc.v:196425$13736
+  attribute \src "libresoc.v:196433.3-196447.6"
+  process $proc$libresoc.v:196433$13736
     assign { } { }
     assign { } { }
     assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0]
-    attribute \src "libresoc.v:196426.5-196426.29"
+    attribute \src "libresoc.v:196434.5-196434.29"
     switch \initial
-      attribute \src "libresoc.v:196426.9-196426.17"
+      attribute \src "libresoc.v:196434.9-196434.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
     switch \fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'01
@@ -410445,19 +410453,19 @@ module \ti
     sync always
       update \core_issue__data_i $0\core_issue__data_i[63:0]
   end
-  attribute \src "libresoc.v:196440.3-196455.6"
-  process $proc$libresoc.v:196440$13737
+  attribute \src "libresoc.v:196448.3-196463.6"
+  process $proc$libresoc.v:196448$13737
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\dec2_cur_dec$next[63:0]$13738 $2\dec2_cur_dec$next[63:0]$13740
-    attribute \src "libresoc.v:196441.5-196441.29"
+    attribute \src "libresoc.v:196449.5-196449.29"
     switch \initial
-      attribute \src "libresoc.v:196441.9-196441.17"
+      attribute \src "libresoc.v:196449.9-196449.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
     switch \fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'01
@@ -410478,18 +410486,18 @@ module \ti
     sync always
       update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13738
   end
-  attribute \src "libresoc.v:196456.3-196466.6"
-  process $proc$libresoc.v:196456$13741
+  attribute \src "libresoc.v:196464.3-196474.6"
+  process $proc$libresoc.v:196464$13741
     assign { } { }
     assign { } { }
     assign $0\new_tb[63:0] $1\new_tb[63:0]
-    attribute \src "libresoc.v:196457.5-196457.29"
+    attribute \src "libresoc.v:196465.5-196465.29"
     switch \initial
-      attribute \src "libresoc.v:196457.9-196457.17"
+      attribute \src "libresoc.v:196465.9-196465.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
     switch \fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'11
@@ -410501,14 +410509,14 @@ module \ti
     sync always
       update \new_tb $0\new_tb[63:0]
   end
-  attribute \src "libresoc.v:196467.3-196475.6"
-  process $proc$libresoc.v:196467$13742
+  attribute \src "libresoc.v:196475.3-196483.6"
+  process $proc$libresoc.v:196475$13742
     assign { } { }
     assign { } { }
     assign $0\dbg_dmi_we_i$next[0:0]$13743 $1\dbg_dmi_we_i$next[0:0]$13744
-    attribute \src "libresoc.v:196468.5-196468.29"
+    attribute \src "libresoc.v:196476.5-196476.29"
     switch \initial
-      attribute \src "libresoc.v:196468.9-196468.17"
+      attribute \src "libresoc.v:196476.9-196476.17"
       case 1'1
       case 
     end
@@ -410524,14 +410532,14 @@ module \ti
     sync always
       update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13743
   end
-  attribute \src "libresoc.v:196476.3-196484.6"
-  process $proc$libresoc.v:196476$13745
+  attribute \src "libresoc.v:196484.3-196492.6"
+  process $proc$libresoc.v:196484$13745
     assign { } { }
     assign { } { }
     assign $0\pc_ok_delay$next[0:0]$13746 $1\pc_ok_delay$next[0:0]$13747
-    attribute \src "libresoc.v:196477.5-196477.29"
+    attribute \src "libresoc.v:196485.5-196485.29"
     switch \initial
-      attribute \src "libresoc.v:196477.9-196477.17"
+      attribute \src "libresoc.v:196485.9-196485.17"
       case 1'1
       case 
     end
@@ -410547,19 +410555,19 @@ module \ti
     sync always
       update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13746
   end
-  attribute \src "libresoc.v:196485.3-196500.6"
-  process $proc$libresoc.v:196485$13748
+  attribute \src "libresoc.v:196493.3-196508.6"
+  process $proc$libresoc.v:196493$13748
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\pc[63:0] $2\pc[63:0]
-    attribute \src "libresoc.v:196486.5-196486.29"
+    attribute \src "libresoc.v:196494.5-196494.29"
     switch \initial
-      attribute \src "libresoc.v:196486.9-196486.17"
+      attribute \src "libresoc.v:196494.9-196494.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:483"
     switch \pc_i_ok
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -410568,7 +410576,7 @@ module \ti
       case 
         assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:489"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:490"
     switch \pc_ok_delay
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -410580,18 +410588,18 @@ module \ti
     sync always
       update \pc $0\pc[63:0]
   end
-  attribute \src "libresoc.v:196501.3-196513.6"
-  process $proc$libresoc.v:196501$13749
+  attribute \src "libresoc.v:196509.3-196521.6"
+  process $proc$libresoc.v:196509$13749
     assign { } { }
     assign { } { }
     assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0]
-    attribute \src "libresoc.v:196502.5-196502.29"
+    attribute \src "libresoc.v:196510.5-196510.29"
     switch \initial
-      attribute \src "libresoc.v:196502.9-196502.17"
+      attribute \src "libresoc.v:196510.9-196510.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:483"
     switch \pc_i_ok
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -410604,14 +410612,14 @@ module \ti
     sync always
       update \core_cia__ren $0\core_cia__ren[2:0]
   end
-  attribute \src "libresoc.v:196514.3-196522.6"
-  process $proc$libresoc.v:196514$13750
+  attribute \src "libresoc.v:196522.3-196530.6"
+  process $proc$libresoc.v:196522$13750
     assign { } { }
     assign { } { }
     assign $0\svstate_ok_delay$next[0:0]$13751 $1\svstate_ok_delay$next[0:0]$13752
-    attribute \src "libresoc.v:196515.5-196515.29"
+    attribute \src "libresoc.v:196523.5-196523.29"
     switch \initial
-      attribute \src "libresoc.v:196515.9-196515.17"
+      attribute \src "libresoc.v:196523.9-196523.17"
       case 1'1
       case 
     end
@@ -410627,19 +410635,19 @@ module \ti
     sync always
       update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13751
   end
-  attribute \src "libresoc.v:196523.3-196538.6"
-  process $proc$libresoc.v:196523$13753
+  attribute \src "libresoc.v:196531.3-196546.6"
+  process $proc$libresoc.v:196531$13753
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\svstate[63:0] $2\svstate[63:0]
-    attribute \src "libresoc.v:196524.5-196524.29"
+    attribute \src "libresoc.v:196532.5-196532.29"
     switch \initial
-      attribute \src "libresoc.v:196524.9-196524.17"
+      attribute \src "libresoc.v:196532.9-196532.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:496"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:497"
     switch \svstate_i_ok
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -410648,7 +410656,7 @@ module \ti
       case 
         assign $1\svstate[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504"
     switch \svstate_ok_delay
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -410660,18 +410668,18 @@ module \ti
     sync always
       update \svstate $0\svstate[63:0]
   end
-  attribute \src "libresoc.v:196539.3-196551.6"
-  process $proc$libresoc.v:196539$13754
+  attribute \src "libresoc.v:196547.3-196559.6"
+  process $proc$libresoc.v:196547$13754
     assign { } { }
     assign { } { }
     assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0]
-    attribute \src "libresoc.v:196540.5-196540.29"
+    attribute \src "libresoc.v:196548.5-196548.29"
     switch \initial
-      attribute \src "libresoc.v:196540.9-196540.17"
+      attribute \src "libresoc.v:196548.9-196548.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:496"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:497"
     switch \svstate_i_ok
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -410684,14 +410692,14 @@ module \ti
     sync always
       update \core_sv__ren $0\core_sv__ren[2:0]
   end
-  attribute \src "libresoc.v:196552.3-196560.6"
-  process $proc$libresoc.v:196552$13755
+  attribute \src "libresoc.v:196560.3-196568.6"
+  process $proc$libresoc.v:196560$13755
     assign { } { }
     assign { } { }
     assign $0\dbg_dmi_din$next[63:0]$13756 $1\dbg_dmi_din$next[63:0]$13757
-    attribute \src "libresoc.v:196553.5-196553.29"
+    attribute \src "libresoc.v:196561.5-196561.29"
     switch \initial
-      attribute \src "libresoc.v:196553.9-196553.17"
+      attribute \src "libresoc.v:196561.9-196561.17"
       case 1'1
       case 
     end
@@ -410707,36 +410715,36 @@ module \ti
     sync always
       update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13756
   end
-  attribute \src "libresoc.v:196561.3-196586.6"
-  process $proc$libresoc.v:196561$13758
+  attribute \src "libresoc.v:196569.3-196594.6"
+  process $proc$libresoc.v:196569$13758
     assign { } { }
     assign { } { }
     assign $0\core_wen[2:0] $1\core_wen[2:0]
-    attribute \src "libresoc.v:196562.5-196562.29"
+    attribute \src "libresoc.v:196570.5-196570.29"
     switch \initial
-      attribute \src "libresoc.v:196562.9-196562.17"
+      attribute \src "libresoc.v:196570.9-196570.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
     switch \issue_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 3'100
         assign { } { }
         assign $1\core_wen[2:0] $2\core_wen[2:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
         switch \$48
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
             assign { } { }
             assign $2\core_wen[2:0] $3\core_wen[2:0]
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316"
             switch \exec_pc_ready_i
               attribute \src "libresoc.v:0.0-0.0"
               case 1'1
                 assign { } { }
                 assign $3\core_wen[2:0] $4\core_wen[2:0]
-                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:328"
+                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:329"
                 switch \$50
                   attribute \src "libresoc.v:0.0-0.0"
                   case 1'1
@@ -410757,36 +410765,36 @@ module \ti
     sync always
       update \core_wen $0\core_wen[2:0]
   end
-  attribute \src "libresoc.v:196587.3-196612.6"
-  process $proc$libresoc.v:196587$13759
+  attribute \src "libresoc.v:196595.3-196620.6"
+  process $proc$libresoc.v:196595$13759
     assign { } { }
     assign { } { }
     assign $0\core_data_i[63:0] $1\core_data_i[63:0]
-    attribute \src "libresoc.v:196588.5-196588.29"
+    attribute \src "libresoc.v:196596.5-196596.29"
     switch \initial
-      attribute \src "libresoc.v:196588.9-196588.17"
+      attribute \src "libresoc.v:196596.9-196596.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
     switch \issue_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 3'100
         assign { } { }
         assign $1\core_data_i[63:0] $2\core_data_i[63:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
         switch \$56
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
             assign { } { }
             assign $2\core_data_i[63:0] $3\core_data_i[63:0]
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316"
             switch \exec_pc_ready_i
               attribute \src "libresoc.v:0.0-0.0"
               case 1'1
                 assign { } { }
                 assign $3\core_data_i[63:0] $4\core_data_i[63:0]
-                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:328"
+                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:329"
                 switch \$58
                   attribute \src "libresoc.v:0.0-0.0"
                   case 1'1
@@ -410807,24 +410815,24 @@ module \ti
     sync always
       update \core_data_i $0\core_data_i[63:0]
   end
-  attribute \src "libresoc.v:196613.3-196628.6"
-  process $proc$libresoc.v:196613$13760
+  attribute \src "libresoc.v:196621.3-196636.6"
+  process $proc$libresoc.v:196621$13760
     assign { } { }
     assign { } { }
     assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0]
-    attribute \src "libresoc.v:196614.5-196614.29"
+    attribute \src "libresoc.v:196622.5-196622.29"
     switch \initial
-      attribute \src "libresoc.v:196614.9-196614.17"
+      attribute \src "libresoc.v:196622.9-196622.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'00
         assign { } { }
         assign $1\core_msr__ren[2:0] $2\core_msr__ren[2:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
         switch \fetch_pc_valid_i
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -410839,14 +410847,14 @@ module \ti
     sync always
       update \core_msr__ren $0\core_msr__ren[2:0]
   end
-  attribute \src "libresoc.v:196629.3-196637.6"
-  process $proc$libresoc.v:196629$13761
+  attribute \src "libresoc.v:196637.3-196645.6"
+  process $proc$libresoc.v:196637$13761
     assign { } { }
     assign { } { }
     assign $0\jtag_dmi0__ack_o$next[0:0]$13762 $1\jtag_dmi0__ack_o$next[0:0]$13763
-    attribute \src "libresoc.v:196630.5-196630.29"
+    attribute \src "libresoc.v:196638.5-196638.29"
     switch \initial
-      attribute \src "libresoc.v:196630.9-196630.17"
+      attribute \src "libresoc.v:196638.9-196638.17"
       case 1'1
       case 
     end
@@ -410862,18 +410870,18 @@ module \ti
     sync always
       update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13762
   end
-  attribute \src "libresoc.v:196638.3-196648.6"
-  process $proc$libresoc.v:196638$13764
+  attribute \src "libresoc.v:196646.3-196656.6"
+  process $proc$libresoc.v:196646$13764
     assign { } { }
     assign { } { }
     assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0]
-    attribute \src "libresoc.v:196639.5-196639.29"
+    attribute \src "libresoc.v:196647.5-196647.29"
     switch \initial
-      attribute \src "libresoc.v:196639.9-196639.17"
+      attribute \src "libresoc.v:196647.9-196647.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'00
@@ -410885,24 +410893,24 @@ module \ti
     sync always
       update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0]
   end
-  attribute \src "libresoc.v:196649.3-196684.6"
-  process $proc$libresoc.v:196649$13765
+  attribute \src "libresoc.v:196657.3-196692.6"
+  process $proc$libresoc.v:196657$13765
     assign { } { }
     assign { } { }
     assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0]
-    attribute \src "libresoc.v:196650.5-196650.29"
+    attribute \src "libresoc.v:196658.5-196658.29"
     switch \initial
-      attribute \src "libresoc.v:196650.9-196650.17"
+      attribute \src "libresoc.v:196658.9-196658.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'00
         assign { } { }
         assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
         switch \fetch_pc_valid_i
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -410915,7 +410923,7 @@ module \ti
       case 2'01
         assign { } { }
         assign $1\imem_a_pc_i[47:0] $3\imem_a_pc_i[47:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
         switch \imem_f_busy_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -410924,7 +410932,7 @@ module \ti
           case 
             assign { } { }
             assign $3\imem_a_pc_i[47:0] $4\imem_a_pc_i[47:0]
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
             switch \$60
               attribute \src "libresoc.v:0.0-0.0"
               case 1'1
@@ -410941,24 +410949,24 @@ module \ti
     sync always
       update \imem_a_pc_i $0\imem_a_pc_i[47:0]
   end
-  attribute \src "libresoc.v:196685.3-196729.6"
-  process $proc$libresoc.v:196685$13766
+  attribute \src "libresoc.v:196693.3-196737.6"
+  process $proc$libresoc.v:196693$13766
     assign { } { }
     assign { } { }
     assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0]
-    attribute \src "libresoc.v:196686.5-196686.29"
+    attribute \src "libresoc.v:196694.5-196694.29"
     switch \initial
-      attribute \src "libresoc.v:196686.9-196686.17"
+      attribute \src "libresoc.v:196694.9-196694.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'00
         assign { } { }
         assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
         switch \fetch_pc_valid_i
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -410971,7 +410979,7 @@ module \ti
       case 2'01
         assign { } { }
         assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
         switch \imem_f_busy_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -410981,7 +410989,7 @@ module \ti
           case 
             assign { } { }
             assign $3\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0]
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
             switch \$65
               attribute \src "libresoc.v:0.0-0.0"
               case 1'1
@@ -410996,7 +411004,7 @@ module \ti
       case 2'11
         assign { } { }
         assign $1\imem_a_valid_i[0:0] $5\imem_a_valid_i[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:228"
         switch \imem_f_busy_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411011,24 +411019,24 @@ module \ti
     sync always
       update \imem_a_valid_i $0\imem_a_valid_i[0:0]
   end
-  attribute \src "libresoc.v:196730.3-196774.6"
-  process $proc$libresoc.v:196730$13767
+  attribute \src "libresoc.v:196738.3-196782.6"
+  process $proc$libresoc.v:196738$13767
     assign { } { }
     assign { } { }
     assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0]
-    attribute \src "libresoc.v:196731.5-196731.29"
+    attribute \src "libresoc.v:196739.5-196739.29"
     switch \initial
-      attribute \src "libresoc.v:196731.9-196731.17"
+      attribute \src "libresoc.v:196739.9-196739.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'00
         assign { } { }
         assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
         switch \fetch_pc_valid_i
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411041,7 +411049,7 @@ module \ti
       case 2'01
         assign { } { }
         assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
         switch \imem_f_busy_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411051,7 +411059,7 @@ module \ti
           case 
             assign { } { }
             assign $3\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0]
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
             switch \$67
               attribute \src "libresoc.v:0.0-0.0"
               case 1'1
@@ -411066,7 +411074,7 @@ module \ti
       case 2'11
         assign { } { }
         assign $1\imem_f_valid_i[0:0] $5\imem_f_valid_i[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:228"
         switch \imem_f_busy_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411081,25 +411089,25 @@ module \ti
     sync always
       update \imem_f_valid_i $0\imem_f_valid_i[0:0]
   end
-  attribute \src "libresoc.v:196775.3-196795.6"
-  process $proc$libresoc.v:196775$13768
+  attribute \src "libresoc.v:196783.3-196803.6"
+  process $proc$libresoc.v:196783$13768
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\dec2_cur_pc$next[63:0]$13769 $3\dec2_cur_pc$next[63:0]$13772
-    attribute \src "libresoc.v:196776.5-196776.29"
+    attribute \src "libresoc.v:196784.5-196784.29"
     switch \initial
-      attribute \src "libresoc.v:196776.9-196776.17"
+      attribute \src "libresoc.v:196784.9-196784.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'00
         assign { } { }
         assign $1\dec2_cur_pc$next[63:0]$13770 $2\dec2_cur_pc$next[63:0]$13771
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
         switch \fetch_pc_valid_i
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411123,8 +411131,8 @@ module \ti
     sync always
       update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13769
   end
-  attribute \src "libresoc.v:196796.3-196834.6"
-  process $proc$libresoc.v:196796$13773
+  attribute \src "libresoc.v:196804.3-196842.6"
+  process $proc$libresoc.v:196804$13773
     assign { } { }
     assign { } { }
     assign { } { }
@@ -411155,13 +411163,13 @@ module \ti
     assign $0\cur_cur_svstep$next[1:0]$13777 $4\cur_cur_svstep$next[1:0]$13801
     assign $0\cur_cur_vl$next[6:0]$13778 $4\cur_cur_vl$next[6:0]$13802
     assign $0\dec2_cur_cur_srcstep$next[6:0]$13779 $4\dec2_cur_cur_srcstep$next[6:0]$13803
-    attribute \src "libresoc.v:196797.5-196797.29"
+    attribute \src "libresoc.v:196805.5-196805.29"
     switch \initial
-      attribute \src "libresoc.v:196797.9-196797.17"
+      attribute \src "libresoc.v:196805.9-196805.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'00
@@ -411177,7 +411185,7 @@ module \ti
         assign $1\cur_cur_svstep$next[1:0]$13783 $2\cur_cur_svstep$next[1:0]$13789
         assign $1\cur_cur_vl$next[6:0]$13784 $2\cur_cur_vl$next[6:0]$13790
         assign $1\dec2_cur_cur_srcstep$next[6:0]$13785 $2\dec2_cur_cur_srcstep$next[6:0]$13791
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
         switch \fetch_pc_valid_i
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411204,7 +411212,7 @@ module \ti
         assign $1\cur_cur_vl$next[6:0]$13784 \cur_cur_vl
         assign $1\dec2_cur_cur_srcstep$next[6:0]$13785 \dec2_cur_cur_srcstep
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341"
     switch \update_svstate
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -411255,14 +411263,14 @@ module \ti
       update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13778
       update \dec2_cur_cur_srcstep$next $0\dec2_cur_cur_srcstep$next[6:0]$13779
   end
-  attribute \src "libresoc.v:196835.3-196843.6"
-  process $proc$libresoc.v:196835$13804
+  attribute \src "libresoc.v:196843.3-196851.6"
+  process $proc$libresoc.v:196843$13804
     assign { } { }
     assign { } { }
     assign $0\jtag_dmi0__dout$next[63:0]$13805 $1\jtag_dmi0__dout$next[63:0]$13806
-    attribute \src "libresoc.v:196836.5-196836.29"
+    attribute \src "libresoc.v:196844.5-196844.29"
     switch \initial
-      attribute \src "libresoc.v:196836.9-196836.17"
+      attribute \src "libresoc.v:196844.9-196844.17"
       case 1'1
       case 
     end
@@ -411278,25 +411286,25 @@ module \ti
     sync always
       update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13805
   end
-  attribute \src "libresoc.v:196844.3-196873.6"
-  process $proc$libresoc.v:196844$13807
+  attribute \src "libresoc.v:196852.3-196881.6"
+  process $proc$libresoc.v:196852$13807
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\msr_read$next[0:0]$13808 $4\msr_read$next[0:0]$13812
-    attribute \src "libresoc.v:196845.5-196845.29"
+    attribute \src "libresoc.v:196853.5-196853.29"
     switch \initial
-      attribute \src "libresoc.v:196845.9-196845.17"
+      attribute \src "libresoc.v:196853.9-196853.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'00
         assign { } { }
         assign $1\msr_read$next[0:0]$13809 $2\msr_read$next[0:0]$13810
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
         switch \fetch_pc_valid_i
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411309,7 +411317,7 @@ module \ti
       case 2'01
         assign { } { }
         assign $1\msr_read$next[0:0]$13809 $3\msr_read$next[0:0]$13811
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
         switch \$69
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411333,25 +411341,25 @@ module \ti
     sync always
       update \msr_read$next $0\msr_read$next[0:0]$13808
   end
-  attribute \src "libresoc.v:196874.3-196935.6"
-  process $proc$libresoc.v:196874$13813
+  attribute \src "libresoc.v:196882.3-196943.6"
+  process $proc$libresoc.v:196882$13813
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\fetch_fsm_state$next[1:0]$13814 $7\fetch_fsm_state$next[1:0]$13821
-    attribute \src "libresoc.v:196875.5-196875.29"
+    attribute \src "libresoc.v:196883.5-196883.29"
     switch \initial
-      attribute \src "libresoc.v:196875.9-196875.17"
+      attribute \src "libresoc.v:196883.9-196883.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'00
         assign { } { }
         assign $1\fetch_fsm_state$next[1:0]$13815 $2\fetch_fsm_state$next[1:0]$13816
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177"
         switch \fetch_pc_valid_i
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411364,7 +411372,7 @@ module \ti
       case 2'01
         assign { } { }
         assign $1\fetch_fsm_state$next[1:0]$13815 $3\fetch_fsm_state$next[1:0]$13817
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
         switch \imem_f_busy_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411373,7 +411381,7 @@ module \ti
           case 
             assign { } { }
             assign $3\fetch_fsm_state$next[1:0]$13817 $4\fetch_fsm_state$next[1:0]$13818
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
             switch \$71
               attribute \src "libresoc.v:0.0-0.0"
               case 1'1
@@ -411389,7 +411397,7 @@ module \ti
       case 2'11
         assign { } { }
         assign $1\fetch_fsm_state$next[1:0]$13815 $5\fetch_fsm_state$next[1:0]$13819
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:228"
         switch \imem_f_busy_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411403,7 +411411,7 @@ module \ti
       case 2'10
         assign { } { }
         assign $1\fetch_fsm_state$next[1:0]$13815 $6\fetch_fsm_state$next[1:0]$13820
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241"
         switch \fetch_insn_ready_i
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411427,25 +411435,25 @@ module \ti
     sync always
       update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13814
   end
-  attribute \src "libresoc.v:196936.3-196956.6"
-  process $proc$libresoc.v:196936$13822
+  attribute \src "libresoc.v:196944.3-196964.6"
+  process $proc$libresoc.v:196944$13822
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\dec2_cur_msr$next[63:0]$13823 $3\dec2_cur_msr$next[63:0]$13826
-    attribute \src "libresoc.v:196937.5-196937.29"
+    attribute \src "libresoc.v:196945.5-196945.29"
     switch \initial
-      attribute \src "libresoc.v:196937.9-196937.17"
+      attribute \src "libresoc.v:196945.9-196945.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'01
         assign { } { }
         assign $1\dec2_cur_msr$next[63:0]$13824 $2\dec2_cur_msr$next[63:0]$13825
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197"
         switch \$73
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411469,24 +411477,24 @@ module \ti
     sync always
       update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13823
   end
-  attribute \src "libresoc.v:196957.3-196975.6"
-  process $proc$libresoc.v:196957$13827
+  attribute \src "libresoc.v:196965.3-196983.6"
+  process $proc$libresoc.v:196965$13827
     assign { } { }
     assign { } { }
     assign $0\svp64_raw_opcode_in[31:0] $1\svp64_raw_opcode_in[31:0]
-    attribute \src "libresoc.v:196958.5-196958.29"
+    attribute \src "libresoc.v:196966.5-196966.29"
     switch \initial
-      attribute \src "libresoc.v:196958.9-196958.17"
+      attribute \src "libresoc.v:196966.9-196966.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'01
         assign { } { }
         assign $1\svp64_raw_opcode_in[31:0] $2\svp64_raw_opcode_in[31:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
         switch \imem_f_busy_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411502,24 +411510,24 @@ module \ti
     sync always
       update \svp64_raw_opcode_in $0\svp64_raw_opcode_in[31:0]
   end
-  attribute \src "libresoc.v:196976.3-196994.6"
-  process $proc$libresoc.v:196976$13828
+  attribute \src "libresoc.v:196984.3-197002.6"
+  process $proc$libresoc.v:196984$13828
     assign { } { }
     assign { } { }
     assign $0\svp64_bigendian[0:0] $1\svp64_bigendian[0:0]
-    attribute \src "libresoc.v:196977.5-196977.29"
+    attribute \src "libresoc.v:196985.5-196985.29"
     switch \initial
-      attribute \src "libresoc.v:196977.9-196977.17"
+      attribute \src "libresoc.v:196985.9-196985.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'01
         assign { } { }
         assign $1\svp64_bigendian[0:0] $2\svp64_bigendian[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
         switch \imem_f_busy_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411535,8 +411543,8 @@ module \ti
     sync always
       update \svp64_bigendian $0\svp64_bigendian[0:0]
   end
-  attribute \src "libresoc.v:196995.3-197032.6"
-  process $proc$libresoc.v:196995$13829
+  attribute \src "libresoc.v:197003.3-197040.6"
+  process $proc$libresoc.v:197003$13829
     assign { } { }
     assign { } { }
     assign { } { }
@@ -411565,13 +411573,13 @@ module \ti
     assign $0\dec_svp64__mmode$next[0:0]$13834 $3\dec_svp64__mmode$next[0:0]$13855
     assign $0\dec_svp64__mode$next[4:0]$13835 $3\dec_svp64__mode$next[4:0]$13856
     assign $0\dec_svp64__subvl$next[1:0]$13836 $3\dec_svp64__subvl$next[1:0]$13857
-    attribute \src "libresoc.v:196996.5-196996.29"
+    attribute \src "libresoc.v:197004.5-197004.29"
     switch \initial
-      attribute \src "libresoc.v:196996.9-196996.17"
+      attribute \src "libresoc.v:197004.9-197004.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'01
@@ -411589,7 +411597,7 @@ module \ti
         assign $1\dec_svp64__mmode$next[0:0]$13841 $2\dec_svp64__mmode$next[0:0]$13848
         assign $1\dec_svp64__mode$next[4:0]$13842 $2\dec_svp64__mode$next[4:0]$13849
         assign $1\dec_svp64__subvl$next[1:0]$13843 $2\dec_svp64__subvl$next[1:0]$13850
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
         switch \imem_f_busy_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411656,24 +411664,24 @@ module \ti
       update \dec_svp64__mode$next $0\dec_svp64__mode$next[4:0]$13835
       update \dec_svp64__subvl$next $0\dec_svp64__subvl$next[1:0]$13836
   end
-  attribute \src "libresoc.v:197033.3-197051.6"
-  process $proc$libresoc.v:197033$13858
+  attribute \src "libresoc.v:197041.3-197059.6"
+  process $proc$libresoc.v:197041$13858
     assign { } { }
     assign { } { }
     assign $0\nia$next[63:0]$13859 $1\nia$next[63:0]$13860
-    attribute \src "libresoc.v:197034.5-197034.29"
+    attribute \src "libresoc.v:197042.5-197042.29"
     switch \initial
-      attribute \src "libresoc.v:197034.9-197034.17"
+      attribute \src "libresoc.v:197042.9-197042.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'01
         assign { } { }
         assign $1\nia$next[63:0]$13860 $2\nia$next[63:0]$13861
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
         switch \imem_f_busy_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411689,24 +411697,24 @@ module \ti
     sync always
       update \nia$next $0\nia$next[63:0]$13859
   end
-  attribute \src "libresoc.v:197052.3-197087.6"
-  process $proc$libresoc.v:197052$13862
+  attribute \src "libresoc.v:197060.3-197095.6"
+  process $proc$libresoc.v:197060$13862
     assign { } { }
     assign { } { }
     assign $0\fetch_insn_o[31:0] $1\fetch_insn_o[31:0]
-    attribute \src "libresoc.v:197053.5-197053.29"
+    attribute \src "libresoc.v:197061.5-197061.29"
     switch \initial
-      attribute \src "libresoc.v:197053.9-197053.17"
+      attribute \src "libresoc.v:197061.9-197061.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'01
         assign { } { }
         assign $1\fetch_insn_o[31:0] $2\fetch_insn_o[31:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200"
         switch \imem_f_busy_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411715,7 +411723,7 @@ module \ti
           case 
             assign { } { }
             assign $2\fetch_insn_o[31:0] $3\fetch_insn_o[31:0]
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:215"
             switch \$84
               attribute \src "libresoc.v:0.0-0.0"
               case 1'1
@@ -411729,7 +411737,7 @@ module \ti
       case 2'11
         assign { } { }
         assign $1\fetch_insn_o[31:0] $4\fetch_insn_o[31:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:228"
         switch \imem_f_busy_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411745,18 +411753,18 @@ module \ti
     sync always
       update \fetch_insn_o $0\fetch_insn_o[31:0]
   end
-  attribute \src "libresoc.v:197088.3-197098.6"
-  process $proc$libresoc.v:197088$13863
+  attribute \src "libresoc.v:197096.3-197106.6"
+  process $proc$libresoc.v:197096$13863
     assign { } { }
     assign { } { }
     assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0]
-    attribute \src "libresoc.v:197089.5-197089.29"
+    attribute \src "libresoc.v:197097.5-197097.29"
     switch \initial
-      attribute \src "libresoc.v:197089.9-197089.17"
+      attribute \src "libresoc.v:197097.9-197097.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172"
     switch \fetch_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 2'10
@@ -411768,25 +411776,25 @@ module \ti
     sync always
       update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0]
   end
-  attribute \src "libresoc.v:197099.3-197160.6"
-  process $proc$libresoc.v:197099$13864
+  attribute \src "libresoc.v:197107.3-197168.6"
+  process $proc$libresoc.v:197107$13864
     assign { } { }
     assign { } { }
     assign { } { }
     assign $0\issue_fsm_state$next[2:0]$13865 $8\issue_fsm_state$next[2:0]$13873
-    attribute \src "libresoc.v:197100.5-197100.29"
+    attribute \src "libresoc.v:197108.5-197108.29"
     switch \initial
-      attribute \src "libresoc.v:197100.9-197100.17"
+      attribute \src "libresoc.v:197108.9-197108.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
     switch \issue_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 3'000
         assign { } { }
         assign $1\issue_fsm_state$next[2:0]$13866 $2\issue_fsm_state$next[2:0]$13867
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
         switch \$101
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411799,7 +411807,7 @@ module \ti
       case 3'001
         assign { } { }
         assign $1\issue_fsm_state$next[2:0]$13866 $3\issue_fsm_state$next[2:0]$13868
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290"
         switch \fetch_pc_ready_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411812,7 +411820,7 @@ module \ti
       case 3'010
         assign { } { }
         assign $1\issue_fsm_state$next[2:0]$13866 $4\issue_fsm_state$next[2:0]$13869
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296"
         switch \fetch_insn_valid_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411825,7 +411833,7 @@ module \ti
       case 3'011
         assign { } { }
         assign $1\issue_fsm_state$next[2:0]$13866 $5\issue_fsm_state$next[2:0]$13870
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
         switch \exec_insn_ready_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411838,13 +411846,13 @@ module \ti
       case 3'100
         assign { } { }
         assign $1\issue_fsm_state$next[2:0]$13866 $6\issue_fsm_state$next[2:0]$13871
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
         switch \$107
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
             assign { } { }
             assign $6\issue_fsm_state$next[2:0]$13871 $7\issue_fsm_state$next[2:0]$13872
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316"
             switch \exec_pc_ready_i
               attribute \src "libresoc.v:0.0-0.0"
               case 1'1
@@ -411871,24 +411879,24 @@ module \ti
     sync always
       update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13865
   end
-  attribute \src "libresoc.v:197161.3-197191.6"
-  process $proc$libresoc.v:197161$13874
+  attribute \src "libresoc.v:197169.3-197199.6"
+  process $proc$libresoc.v:197169$13874
     assign { } { }
     assign { } { }
     assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0]
-    attribute \src "libresoc.v:197162.5-197162.29"
+    attribute \src "libresoc.v:197170.5-197170.29"
     switch \initial
-      attribute \src "libresoc.v:197162.9-197162.17"
+      attribute \src "libresoc.v:197170.9-197170.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
     switch \issue_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 3'000
         assign { } { }
         assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
         switch \$113
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411902,7 +411910,7 @@ module \ti
       case 3'100
         assign { } { }
         assign $1\core_stopped_i[0:0] $3\core_stopped_i[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
         switch \$119
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411918,24 +411926,24 @@ module \ti
     sync always
       update \core_stopped_i $0\core_stopped_i[0:0]
   end
-  attribute \src "libresoc.v:197192.3-197222.6"
-  process $proc$libresoc.v:197192$13875
+  attribute \src "libresoc.v:197200.3-197230.6"
+  process $proc$libresoc.v:197200$13875
     assign { } { }
     assign { } { }
     assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0]
-    attribute \src "libresoc.v:197193.5-197193.29"
+    attribute \src "libresoc.v:197201.5-197201.29"
     switch \initial
-      attribute \src "libresoc.v:197193.9-197193.17"
+      attribute \src "libresoc.v:197201.9-197201.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
     switch \issue_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 3'000
         assign { } { }
         assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
         switch \$125
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411949,7 +411957,7 @@ module \ti
       case 3'100
         assign { } { }
         assign $1\dbg_core_stopped_i[0:0] $3\dbg_core_stopped_i[0:0]
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314"
         switch \$131
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -411965,18 +411973,18 @@ module \ti
     sync always
       update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0]
   end
-  attribute \src "libresoc.v:197223.3-197233.6"
-  process $proc$libresoc.v:197223$13876
+  attribute \src "libresoc.v:197231.3-197241.6"
+  process $proc$libresoc.v:197231$13876
     assign { } { }
     assign { } { }
     assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0]
-    attribute \src "libresoc.v:197224.5-197224.29"
+    attribute \src "libresoc.v:197232.5-197232.29"
     switch \initial
-      attribute \src "libresoc.v:197224.9-197224.17"
+      attribute \src "libresoc.v:197232.9-197232.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
     switch \issue_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 3'001
@@ -411988,18 +411996,18 @@ module \ti
     sync always
       update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0]
   end
-  attribute \src "libresoc.v:197234.3-197244.6"
-  process $proc$libresoc.v:197234$13877
+  attribute \src "libresoc.v:197242.3-197252.6"
+  process $proc$libresoc.v:197242$13877
     assign { } { }
     assign { } { }
     assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0]
-    attribute \src "libresoc.v:197235.5-197235.29"
+    attribute \src "libresoc.v:197243.5-197243.29"
     switch \initial
-      attribute \src "libresoc.v:197235.9-197235.17"
+      attribute \src "libresoc.v:197243.9-197243.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
     switch \issue_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 3'010
@@ -412011,8 +412019,8 @@ module \ti
     sync always
       update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0]
   end
-  attribute \src "libresoc.v:197245.3-197363.6"
-  process $proc$libresoc.v:197245$13878
+  attribute \src "libresoc.v:197253.3-197371.6"
+  process $proc$libresoc.v:197253$13878
     assign { } { }
     assign { } { }
     assign { } { }
@@ -412276,13 +412284,13 @@ module \ti
     assign $0\core_fasto2_ok$next[0:0]$13934 $5\core_fasto2_ok$next[0:0]$14198
     assign $0\core_rego_ok$next[0:0]$13935 $5\core_rego_ok$next[0:0]$14199
     assign $0\core_spro_ok$next[0:0]$13936 $5\core_spro_ok$next[0:0]$14200
-    attribute \src "libresoc.v:197246.5-197246.29"
+    attribute \src "libresoc.v:197254.5-197254.29"
     switch \initial
-      attribute \src "libresoc.v:197246.9-197246.17"
+      attribute \src "libresoc.v:197254.9-197254.17"
       case 1'1
       case 
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274"
     switch \issue_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 3'010
@@ -412404,7 +412412,7 @@ module \ti
         assign $1\core_rego_ok$next[0:0]$13994 $2\core_rego_ok$next[0:0]$14053
         assign $1\core_spro_ok$next[0:0]$13995 $2\core_spro_ok$next[0:0]$14054
         assign $1\core_xer_out$next[0:0]$13996 $2\core_xer_out$next[0:0]$14055
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296"
         switch \fetch_insn_valid_o
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -412590,7 +412598,7 @@ module \ti
         assign $1\core_spro_ok$next[0:0]$13995 \core_spro_ok
         assign $1\core_xer_out$next[0:0]$13996 \core_xer_out
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:368"
     switch \exec_fsm_state
       attribute \src "libresoc.v:0.0-0.0"
       case 1'1
@@ -412712,7 +412720,7 @@ module \ti
         assign $3\core_rego_ok$next[0:0]$14112 $4\core_rego_ok$next[0:0]$14171
         assign $3\core_spro_ok$next[0:0]$14113 $4\core_spro_ok$next[0:0]$14172
         assign $3\core_xer_out$next[0:0]$14114 $4\core_xer_out$next[0:0]$14173
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387"
         switch \$133
           attribute \src "libresoc.v:0.0-0.0"
           case 1'1
@@ -413046,80 +413054,80 @@ module \ti
       update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13936
       update \core_xer_out$next $0\core_xer_out$next[0:0]$13937
   end
-  connect \$99 $not$libresoc.v:194907$13409_Y
-  connect \$101 $and$libresoc.v:194908$13410_Y
-  connect \$103 $not$libresoc.v:194909$13411_Y
-  connect \$105 $not$libresoc.v:194910$13412_Y
-  connect \$107 $and$libresoc.v:194911$13413_Y
-  connect \$109 $not$libresoc.v:194912$13414_Y
-  connect \$111 $not$libresoc.v:194913$13415_Y
-  connect \$113 $and$libresoc.v:194914$13416_Y
-  connect \$115 $not$libresoc.v:194915$13417_Y
-  connect \$117 $not$libresoc.v:194916$13418_Y
-  connect \$119 $and$libresoc.v:194917$13419_Y
-  connect \$121 $not$libresoc.v:194918$13420_Y
-  connect \$123 $not$libresoc.v:194919$13421_Y
-  connect \$125 $and$libresoc.v:194920$13422_Y
-  connect \$127 $not$libresoc.v:194921$13423_Y
-  connect \$129 $not$libresoc.v:194922$13424_Y
-  connect \$131 $and$libresoc.v:194923$13425_Y
-  connect \$133 $not$libresoc.v:194924$13426_Y
-  connect \$135 $not$libresoc.v:194925$13427_Y
-  connect \$137 $not$libresoc.v:194926$13428_Y
-  connect \$139 $not$libresoc.v:194927$13429_Y
-  connect \$141 $not$libresoc.v:194928$13430_Y
-  connect \$143 $and$libresoc.v:194929$13431_Y
-  connect \$145 $pos$libresoc.v:194930$13432_Y
-  connect \$147 $ne$libresoc.v:194931$13433_Y
-  connect \$149 $not$libresoc.v:194932$13434_Y
-  connect \$152 $and$libresoc.v:194933$13435_Y
-  connect \$151 $reduce_or$libresoc.v:194934$13436_Y
-  connect \$155 $not$libresoc.v:194935$13437_Y
-  connect \$158 $and$libresoc.v:194936$13438_Y
-  connect \$157 $reduce_or$libresoc.v:194937$13439_Y
-  connect \$161 $not$libresoc.v:194938$13440_Y
-  connect \$163 $not$libresoc.v:194939$13441_Y
-  connect \$165 $not$libresoc.v:194940$13442_Y
-  connect \$167 $pos$libresoc.v:194941$13444_Y
-  connect \$169 $pos$libresoc.v:194942$13446_Y
-  connect \$172 $sub$libresoc.v:194943$13447_Y
-  connect \$175 $add$libresoc.v:194944$13448_Y
-  connect \$23 $ne$libresoc.v:194945$13449_Y
-  connect \$26 $sub$libresoc.v:194946$13450_Y
-  connect \$28 $or$libresoc.v:194947$13451_Y
-  connect \$30 $or$libresoc.v:194948$13452_Y
-  connect \$32 $ne$libresoc.v:194949$13453_Y
-  connect \$34 $not$libresoc.v:194950$13454_Y
-  connect \$36 $and$libresoc.v:194951$13455_Y
-  connect \$38 $not$libresoc.v:194952$13456_Y
-  connect \$40 $not$libresoc.v:194953$13457_Y
-  connect \$42 $pos$libresoc.v:194954$13459_Y
-  connect \$44 $not$libresoc.v:194955$13460_Y
-  connect \$46 $not$libresoc.v:194956$13461_Y
-  connect \$48 $and$libresoc.v:194957$13462_Y
-  connect \$50 $not$libresoc.v:194958$13463_Y
-  connect \$52 $not$libresoc.v:194959$13464_Y
-  connect \$54 $not$libresoc.v:194960$13465_Y
-  connect \$56 $and$libresoc.v:194961$13466_Y
-  connect \$58 $not$libresoc.v:194962$13467_Y
-  connect \$60 $not$libresoc.v:194963$13468_Y
-  connect \$63 $add$libresoc.v:194964$13469_Y
-  connect \$65 $not$libresoc.v:194965$13470_Y
-  connect \$67 $not$libresoc.v:194966$13471_Y
-  connect \$69 $not$libresoc.v:194967$13472_Y
-  connect \$71 $not$libresoc.v:194968$13473_Y
-  connect \$73 $not$libresoc.v:194969$13474_Y
-  connect \$76 $mul$libresoc.v:194970$13475_Y
-  connect \$75 $shr$libresoc.v:194971$13476_Y [31:0]
-  connect \$80 $ternary$libresoc.v:194972$13477_Y
-  connect \$82 $add$libresoc.v:194973$13478_Y
-  connect \$84 $not$libresoc.v:194974$13479_Y
-  connect \$87 $mul$libresoc.v:194975$13480_Y
-  connect \$86 $shr$libresoc.v:194976$13481_Y [31:0]
-  connect \$92 $add$libresoc.v:194977$13482_Y
-  connect \$94 $mul$libresoc.v:194978$13483_Y
-  connect \$90 $shr$libresoc.v:194979$13484_Y [31:0]
-  connect \$97 $not$libresoc.v:194980$13485_Y
+  connect \$99 $not$libresoc.v:194915$13409_Y
+  connect \$101 $and$libresoc.v:194916$13410_Y
+  connect \$103 $not$libresoc.v:194917$13411_Y
+  connect \$105 $not$libresoc.v:194918$13412_Y
+  connect \$107 $and$libresoc.v:194919$13413_Y
+  connect \$109 $not$libresoc.v:194920$13414_Y
+  connect \$111 $not$libresoc.v:194921$13415_Y
+  connect \$113 $and$libresoc.v:194922$13416_Y
+  connect \$115 $not$libresoc.v:194923$13417_Y
+  connect \$117 $not$libresoc.v:194924$13418_Y
+  connect \$119 $and$libresoc.v:194925$13419_Y
+  connect \$121 $not$libresoc.v:194926$13420_Y
+  connect \$123 $not$libresoc.v:194927$13421_Y
+  connect \$125 $and$libresoc.v:194928$13422_Y
+  connect \$127 $not$libresoc.v:194929$13423_Y
+  connect \$129 $not$libresoc.v:194930$13424_Y
+  connect \$131 $and$libresoc.v:194931$13425_Y
+  connect \$133 $not$libresoc.v:194932$13426_Y
+  connect \$135 $not$libresoc.v:194933$13427_Y
+  connect \$137 $not$libresoc.v:194934$13428_Y
+  connect \$139 $not$libresoc.v:194935$13429_Y
+  connect \$141 $not$libresoc.v:194936$13430_Y
+  connect \$143 $and$libresoc.v:194937$13431_Y
+  connect \$145 $pos$libresoc.v:194938$13432_Y
+  connect \$147 $ne$libresoc.v:194939$13433_Y
+  connect \$149 $not$libresoc.v:194940$13434_Y
+  connect \$152 $and$libresoc.v:194941$13435_Y
+  connect \$151 $reduce_or$libresoc.v:194942$13436_Y
+  connect \$155 $not$libresoc.v:194943$13437_Y
+  connect \$158 $and$libresoc.v:194944$13438_Y
+  connect \$157 $reduce_or$libresoc.v:194945$13439_Y
+  connect \$161 $not$libresoc.v:194946$13440_Y
+  connect \$163 $not$libresoc.v:194947$13441_Y
+  connect \$165 $not$libresoc.v:194948$13442_Y
+  connect \$167 $pos$libresoc.v:194949$13444_Y
+  connect \$169 $pos$libresoc.v:194950$13446_Y
+  connect \$172 $sub$libresoc.v:194951$13447_Y
+  connect \$175 $add$libresoc.v:194952$13448_Y
+  connect \$23 $ne$libresoc.v:194953$13449_Y
+  connect \$26 $sub$libresoc.v:194954$13450_Y
+  connect \$28 $or$libresoc.v:194955$13451_Y
+  connect \$30 $or$libresoc.v:194956$13452_Y
+  connect \$32 $ne$libresoc.v:194957$13453_Y
+  connect \$34 $not$libresoc.v:194958$13454_Y
+  connect \$36 $and$libresoc.v:194959$13455_Y
+  connect \$38 $not$libresoc.v:194960$13456_Y
+  connect \$40 $not$libresoc.v:194961$13457_Y
+  connect \$42 $pos$libresoc.v:194962$13459_Y
+  connect \$44 $not$libresoc.v:194963$13460_Y
+  connect \$46 $not$libresoc.v:194964$13461_Y
+  connect \$48 $and$libresoc.v:194965$13462_Y
+  connect \$50 $not$libresoc.v:194966$13463_Y
+  connect \$52 $not$libresoc.v:194967$13464_Y
+  connect \$54 $not$libresoc.v:194968$13465_Y
+  connect \$56 $and$libresoc.v:194969$13466_Y
+  connect \$58 $not$libresoc.v:194970$13467_Y
+  connect \$60 $not$libresoc.v:194971$13468_Y
+  connect \$63 $add$libresoc.v:194972$13469_Y
+  connect \$65 $not$libresoc.v:194973$13470_Y
+  connect \$67 $not$libresoc.v:194974$13471_Y
+  connect \$69 $not$libresoc.v:194975$13472_Y
+  connect \$71 $not$libresoc.v:194976$13473_Y
+  connect \$73 $not$libresoc.v:194977$13474_Y
+  connect \$76 $mul$libresoc.v:194978$13475_Y
+  connect \$75 $shr$libresoc.v:194979$13476_Y [31:0]
+  connect \$80 $ternary$libresoc.v:194980$13477_Y
+  connect \$82 $add$libresoc.v:194981$13478_Y
+  connect \$84 $not$libresoc.v:194982$13479_Y
+  connect \$87 $mul$libresoc.v:194983$13480_Y
+  connect \$86 $shr$libresoc.v:194984$13481_Y [31:0]
+  connect \$92 $add$libresoc.v:194985$13482_Y
+  connect \$94 $mul$libresoc.v:194986$13483_Y
+  connect \$90 $shr$libresoc.v:194987$13484_Y [31:0]
+  connect \$97 $not$libresoc.v:194988$13485_Y
   connect \$25 \$26
   connect \$62 \$63
   connect \$79 \$82
@@ -413151,485 +413159,485 @@ module \ti
   connect \sram4k_1_enable \jtag_wb_sram_en
   connect \sram4k_0_enable \jtag_wb_sram_en
 end
-attribute \src "libresoc.v:197398.1-198585.10"
+attribute \src "libresoc.v:197406.1-198593.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0"
 attribute \generator "nMigen"
 module \trap0
-  attribute \src "libresoc.v:198130.3-198131.25"
+  attribute \src "libresoc.v:198138.3-198139.25"
   wire $0\all_rd_dly[0:0]
-  attribute \src "libresoc.v:198128.3-198129.41"
+  attribute \src "libresoc.v:198136.3-198137.41"
   wire $0\alu_done_dly[0:0]
-  attribute \src "libresoc.v:198488.3-198496.6"
+  attribute \src "libresoc.v:198496.3-198504.6"
   wire $0\alu_l_r_alu$next[0:0]$14528
-  attribute \src "libresoc.v:198056.3-198057.39"
+  attribute \src "libresoc.v:198064.3-198065.39"
   wire $0\alu_l_r_alu[0:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14454
-  attribute \src "libresoc.v:198096.3-198097.61"
+  attribute \src "libresoc.v:198104.3-198105.61"
   wire width 64 $0\alu_trap0_trap_op__cia[63:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 13 $0\alu_trap0_trap_op__fn_unit$next[12:0]$14455
-  attribute \src "libresoc.v:198090.3-198091.69"
+  attribute \src "libresoc.v:198098.3-198099.69"
   wire width 13 $0\alu_trap0_trap_op__fn_unit[12:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14456
-  attribute \src "libresoc.v:198092.3-198093.63"
+  attribute \src "libresoc.v:198100.3-198101.63"
   wire width 32 $0\alu_trap0_trap_op__insn[31:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14457
-  attribute \src "libresoc.v:198088.3-198089.73"
+  attribute \src "libresoc.v:198096.3-198097.73"
   wire width 7 $0\alu_trap0_trap_op__insn_type[6:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14458
-  attribute \src "libresoc.v:198098.3-198099.71"
+  attribute \src "libresoc.v:198106.3-198107.71"
   wire $0\alu_trap0_trap_op__is_32bit[0:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14459
-  attribute \src "libresoc.v:198104.3-198105.71"
+  attribute \src "libresoc.v:198112.3-198113.71"
   wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14460
-  attribute \src "libresoc.v:198094.3-198095.61"
+  attribute \src "libresoc.v:198102.3-198103.61"
   wire width 64 $0\alu_trap0_trap_op__msr[63:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14461
-  attribute \src "libresoc.v:198102.3-198103.71"
+  attribute \src "libresoc.v:198110.3-198111.71"
   wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14462
-  attribute \src "libresoc.v:198100.3-198101.71"
+  attribute \src "libresoc.v:198108.3-198109.71"
   wire width 8 $0\alu_trap0_trap_op__traptype[7:0]
-  attribute \src "libresoc.v:198479.3-198487.6"
+  attribute \src "libresoc.v:198487.3-198495.6"
   wire $0\alui_l_r_alui$next[0:0]$14525
-  attribute \src "libresoc.v:198058.3-198059.43"
+  attribute \src "libresoc.v:198066.3-198067.43"
   wire $0\alui_l_r_alui[0:0]
-  attribute \src "libresoc.v:198329.3-198350.6"
+  attribute \src "libresoc.v:198337.3-198358.6"
   wire width 64 $0\data_r0__o$next[63:0]$14473
-  attribute \src "libresoc.v:198084.3-198085.37"
+  attribute \src "libresoc.v:198092.3-198093.37"
   wire width 64 $0\data_r0__o[63:0]
-  attribute \src "libresoc.v:198329.3-198350.6"
+  attribute \src "libresoc.v:198337.3-198358.6"
   wire $0\data_r0__o_ok$next[0:0]$14474
-  attribute \src "libresoc.v:198086.3-198087.43"
+  attribute \src "libresoc.v:198094.3-198095.43"
   wire $0\data_r0__o_ok[0:0]
-  attribute \src "libresoc.v:198351.3-198372.6"
+  attribute \src "libresoc.v:198359.3-198380.6"
   wire width 64 $0\data_r1__fast1$next[63:0]$14481
-  attribute \src "libresoc.v:198080.3-198081.45"
+  attribute \src "libresoc.v:198088.3-198089.45"
   wire width 64 $0\data_r1__fast1[63:0]
-  attribute \src "libresoc.v:198351.3-198372.6"
+  attribute \src "libresoc.v:198359.3-198380.6"
   wire $0\data_r1__fast1_ok$next[0:0]$14482
-  attribute \src "libresoc.v:198082.3-198083.51"
+  attribute \src "libresoc.v:198090.3-198091.51"
   wire $0\data_r1__fast1_ok[0:0]
-  attribute \src "libresoc.v:198373.3-198394.6"
+  attribute \src "libresoc.v:198381.3-198402.6"
   wire width 64 $0\data_r2__fast2$next[63:0]$14489
-  attribute \src "libresoc.v:198076.3-198077.45"
+  attribute \src "libresoc.v:198084.3-198085.45"
   wire width 64 $0\data_r2__fast2[63:0]
-  attribute \src "libresoc.v:198373.3-198394.6"
+  attribute \src "libresoc.v:198381.3-198402.6"
   wire $0\data_r2__fast2_ok$next[0:0]$14490
-  attribute \src "libresoc.v:198078.3-198079.51"
+  attribute \src "libresoc.v:198086.3-198087.51"
   wire $0\data_r2__fast2_ok[0:0]
-  attribute \src "libresoc.v:198395.3-198416.6"
+  attribute \src "libresoc.v:198403.3-198424.6"
   wire width 64 $0\data_r3__nia$next[63:0]$14497
-  attribute \src "libresoc.v:198072.3-198073.41"
+  attribute \src "libresoc.v:198080.3-198081.41"
   wire width 64 $0\data_r3__nia[63:0]
-  attribute \src "libresoc.v:198395.3-198416.6"
+  attribute \src "libresoc.v:198403.3-198424.6"
   wire $0\data_r3__nia_ok$next[0:0]$14498
-  attribute \src "libresoc.v:198074.3-198075.47"
+  attribute \src "libresoc.v:198082.3-198083.47"
   wire $0\data_r3__nia_ok[0:0]
-  attribute \src "libresoc.v:198417.3-198438.6"
+  attribute \src "libresoc.v:198425.3-198446.6"
   wire width 64 $0\data_r4__msr$next[63:0]$14505
-  attribute \src "libresoc.v:198068.3-198069.41"
+  attribute \src "libresoc.v:198076.3-198077.41"
   wire width 64 $0\data_r4__msr[63:0]
-  attribute \src "libresoc.v:198417.3-198438.6"
+  attribute \src "libresoc.v:198425.3-198446.6"
   wire $0\data_r4__msr_ok$next[0:0]$14506
-  attribute \src "libresoc.v:198070.3-198071.47"
+  attribute \src "libresoc.v:198078.3-198079.47"
   wire $0\data_r4__msr_ok[0:0]
-  attribute \src "libresoc.v:198497.3-198506.6"
+  attribute \src "libresoc.v:198505.3-198514.6"
   wire width 64 $0\dest1_o[63:0]
-  attribute \src "libresoc.v:198507.3-198516.6"
+  attribute \src "libresoc.v:198515.3-198524.6"
   wire width 64 $0\dest2_o[63:0]
-  attribute \src "libresoc.v:198517.3-198526.6"
+  attribute \src "libresoc.v:198525.3-198534.6"
   wire width 64 $0\dest3_o[63:0]
-  attribute \src "libresoc.v:198527.3-198536.6"
+  attribute \src "libresoc.v:198535.3-198544.6"
   wire width 64 $0\dest4_o[63:0]
-  attribute \src "libresoc.v:198537.3-198546.6"
+  attribute \src "libresoc.v:198545.3-198554.6"
   wire width 64 $0\dest5_o[63:0]
-  attribute \src "libresoc.v:197399.7-197399.20"
+  attribute \src "libresoc.v:197407.7-197407.20"
   wire $0\initial[0:0]
-  attribute \src "libresoc.v:198266.3-198274.6"
+  attribute \src "libresoc.v:198274.3-198282.6"
   wire $0\opc_l_r_opc$next[0:0]$14439
-  attribute \src "libresoc.v:198114.3-198115.39"
+  attribute \src "libresoc.v:198122.3-198123.39"
   wire $0\opc_l_r_opc[0:0]
-  attribute \src "libresoc.v:198257.3-198265.6"
+  attribute \src "libresoc.v:198265.3-198273.6"
   wire $0\opc_l_s_opc$next[0:0]$14436
-  attribute \src "libresoc.v:198116.3-198117.39"
+  attribute \src "libresoc.v:198124.3-198125.39"
   wire $0\opc_l_s_opc[0:0]
-  attribute \src "libresoc.v:198547.3-198555.6"
+  attribute \src "libresoc.v:198555.3-198563.6"
   wire width 5 $0\prev_wr_go$next[4:0]$14536
-  attribute \src "libresoc.v:198126.3-198127.37"
+  attribute \src "libresoc.v:198134.3-198135.37"
   wire width 5 $0\prev_wr_go[4:0]
-  attribute \src "libresoc.v:198211.3-198220.6"
+  attribute \src "libresoc.v:198219.3-198228.6"
   wire $0\req_done[0:0]
-  attribute \src "libresoc.v:198302.3-198310.6"
+  attribute \src "libresoc.v:198310.3-198318.6"
   wire width 5 $0\req_l_r_req$next[4:0]$14451
-  attribute \src "libresoc.v:198106.3-198107.39"
+  attribute \src "libresoc.v:198114.3-198115.39"
   wire width 5 $0\req_l_r_req[4:0]
-  attribute \src "libresoc.v:198293.3-198301.6"
+  attribute \src "libresoc.v:198301.3-198309.6"
   wire width 5 $0\req_l_s_req$next[4:0]$14448
-  attribute \src "libresoc.v:198108.3-198109.39"
+  attribute \src "libresoc.v:198116.3-198117.39"
   wire width 5 $0\req_l_s_req[4:0]
-  attribute \src "libresoc.v:198230.3-198238.6"
+  attribute \src "libresoc.v:198238.3-198246.6"
   wire $0\rok_l_r_rdok$next[0:0]$14427
-  attribute \src "libresoc.v:198122.3-198123.41"
+  attribute \src "libresoc.v:198130.3-198131.41"
   wire $0\rok_l_r_rdok[0:0]
-  attribute \src "libresoc.v:198221.3-198229.6"
+  attribute \src "libresoc.v:198229.3-198237.6"
   wire $0\rok_l_s_rdok$next[0:0]$14424
-  attribute \src "libresoc.v:198124.3-198125.41"
+  attribute \src "libresoc.v:198132.3-198133.41"
   wire $0\rok_l_s_rdok[0:0]
-  attribute \src "libresoc.v:198248.3-198256.6"
+  attribute \src "libresoc.v:198256.3-198264.6"
   wire $0\rst_l_r_rst$next[0:0]$14433
-  attribute \src "libresoc.v:198118.3-198119.39"
+  attribute \src "libresoc.v:198126.3-198127.39"
   wire $0\rst_l_r_rst[0:0]
-  attribute \src "libresoc.v:198239.3-198247.6"
+  attribute \src "libresoc.v:198247.3-198255.6"
   wire $0\rst_l_s_rst$next[0:0]$14430
-  attribute \src "libresoc.v:198120.3-198121.39"
+  attribute \src "libresoc.v:198128.3-198129.39"
   wire $0\rst_l_s_rst[0:0]
-  attribute \src "libresoc.v:198284.3-198292.6"
+  attribute \src "libresoc.v:198292.3-198300.6"
   wire width 4 $0\src_l_r_src$next[3:0]$14445
-  attribute \src "libresoc.v:198110.3-198111.39"
+  attribute \src "libresoc.v:198118.3-198119.39"
   wire width 4 $0\src_l_r_src[3:0]
-  attribute \src "libresoc.v:198275.3-198283.6"
+  attribute \src "libresoc.v:198283.3-198291.6"
   wire width 4 $0\src_l_s_src$next[3:0]$14442
-  attribute \src "libresoc.v:198112.3-198113.39"
+  attribute \src "libresoc.v:198120.3-198121.39"
   wire width 4 $0\src_l_s_src[3:0]
-  attribute \src "libresoc.v:198439.3-198448.6"
+  attribute \src "libresoc.v:198447.3-198456.6"
   wire width 64 $0\src_r0$next[63:0]$14513
-  attribute \src "libresoc.v:198066.3-198067.29"
+  attribute \src "libresoc.v:198074.3-198075.29"
   wire width 64 $0\src_r0[63:0]
-  attribute \src "libresoc.v:198449.3-198458.6"
+  attribute \src "libresoc.v:198457.3-198466.6"
   wire width 64 $0\src_r1$next[63:0]$14516
-  attribute \src "libresoc.v:198064.3-198065.29"
+  attribute \src "libresoc.v:198072.3-198073.29"
   wire width 64 $0\src_r1[63:0]
-  attribute \src "libresoc.v:198459.3-198468.6"
+  attribute \src "libresoc.v:198467.3-198476.6"
   wire width 64 $0\src_r2$next[63:0]$14519
-  attribute \src "libresoc.v:198062.3-198063.29"
+  attribute \src "libresoc.v:198070.3-198071.29"
   wire width 64 $0\src_r2[63:0]
-  attribute \src "libresoc.v:198469.3-198478.6"
+  attribute \src "libresoc.v:198477.3-198486.6"
   wire width 64 $0\src_r3$next[63:0]$14522
-  attribute \src "libresoc.v:198060.3-198061.29"
+  attribute \src "libresoc.v:198068.3-198069.29"
   wire width 64 $0\src_r3[63:0]
-  attribute \src "libresoc.v:197525.7-197525.24"
+  attribute \src "libresoc.v:197533.7-197533.24"
   wire $1\all_rd_dly[0:0]
-  attribute \src "libresoc.v:197535.7-197535.26"
+  attribute \src "libresoc.v:197543.7-197543.26"
   wire $1\alu_done_dly[0:0]
-  attribute \src "libresoc.v:198488.3-198496.6"
+  attribute \src "libresoc.v:198496.3-198504.6"
   wire $1\alu_l_r_alu$next[0:0]$14529
-  attribute \src "libresoc.v:197543.7-197543.25"
+  attribute \src "libresoc.v:197551.7-197551.25"
   wire $1\alu_l_r_alu[0:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14463
-  attribute \src "libresoc.v:197579.14-197579.59"
+  attribute \src "libresoc.v:197587.14-197587.59"
   wire width 64 $1\alu_trap0_trap_op__cia[63:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 13 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14464
-  attribute \src "libresoc.v:197597.14-197597.51"
+  attribute \src "libresoc.v:197605.14-197605.51"
   wire width 13 $1\alu_trap0_trap_op__fn_unit[12:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14465
-  attribute \src "libresoc.v:197601.14-197601.45"
+  attribute \src "libresoc.v:197609.14-197609.45"
   wire width 32 $1\alu_trap0_trap_op__insn[31:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14466
-  attribute \src "libresoc.v:197679.13-197679.49"
+  attribute \src "libresoc.v:197687.13-197687.49"
   wire width 7 $1\alu_trap0_trap_op__insn_type[6:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14467
-  attribute \src "libresoc.v:197683.7-197683.41"
+  attribute \src "libresoc.v:197691.7-197691.41"
   wire $1\alu_trap0_trap_op__is_32bit[0:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14468
-  attribute \src "libresoc.v:197687.13-197687.48"
+  attribute \src "libresoc.v:197695.13-197695.48"
   wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14469
-  attribute \src "libresoc.v:197691.14-197691.59"
+  attribute \src "libresoc.v:197699.14-197699.59"
   wire width 64 $1\alu_trap0_trap_op__msr[63:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14470
-  attribute \src "libresoc.v:197695.14-197695.52"
+  attribute \src "libresoc.v:197703.14-197703.52"
   wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0]
-  attribute \src "libresoc.v:198311.3-198328.6"
+  attribute \src "libresoc.v:198319.3-198336.6"
   wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14471
-  attribute \src "libresoc.v:197699.13-197699.48"
+  attribute \src "libresoc.v:197707.13-197707.48"
   wire width 8 $1\alu_trap0_trap_op__traptype[7:0]
-  attribute \src "libresoc.v:198479.3-198487.6"
+  attribute \src "libresoc.v:198487.3-198495.6"
   wire $1\alui_l_r_alui$next[0:0]$14526
-  attribute \src "libresoc.v:197705.7-197705.27"
+  attribute \src "libresoc.v:197713.7-197713.27"
   wire $1\alui_l_r_alui[0:0]
-  attribute \src "libresoc.v:198329.3-198350.6"
+  attribute \src "libresoc.v:198337.3-198358.6"
   wire width 64 $1\data_r0__o$next[63:0]$14475
-  attribute \src "libresoc.v:197737.14-197737.47"
+  attribute \src "libresoc.v:197745.14-197745.47"
   wire width 64 $1\data_r0__o[63:0]
-  attribute \src "libresoc.v:198329.3-198350.6"
+  attribute \src "libresoc.v:198337.3-198358.6"
   wire $1\data_r0__o_ok$next[0:0]$14476
-  attribute \src "libresoc.v:197741.7-197741.27"
+  attribute \src "libresoc.v:197749.7-197749.27"
   wire $1\data_r0__o_ok[0:0]
-  attribute \src "libresoc.v:198351.3-198372.6"
+  attribute \src "libresoc.v:198359.3-198380.6"
   wire width 64 $1\data_r1__fast1$next[63:0]$14483
-  attribute \src "libresoc.v:197745.14-197745.51"
+  attribute \src "libresoc.v:197753.14-197753.51"
   wire width 64 $1\data_r1__fast1[63:0]
-  attribute \src "libresoc.v:198351.3-198372.6"
+  attribute \src "libresoc.v:198359.3-198380.6"
   wire $1\data_r1__fast1_ok$next[0:0]$14484
-  attribute \src "libresoc.v:197749.7-197749.31"
+  attribute \src "libresoc.v:197757.7-197757.31"
   wire $1\data_r1__fast1_ok[0:0]
-  attribute \src "libresoc.v:198373.3-198394.6"
+  attribute \src "libresoc.v:198381.3-198402.6"
   wire width 64 $1\data_r2__fast2$next[63:0]$14491
-  attribute \src "libresoc.v:197753.14-197753.51"
+  attribute \src "libresoc.v:197761.14-197761.51"
   wire width 64 $1\data_r2__fast2[63:0]
-  attribute \src "libresoc.v:198373.3-198394.6"
+  attribute \src "libresoc.v:198381.3-198402.6"
   wire $1\data_r2__fast2_ok$next[0:0]$14492
-  attribute \src "libresoc.v:197757.7-197757.31"
+  attribute \src "libresoc.v:197765.7-197765.31"
   wire $1\data_r2__fast2_ok[0:0]
-  attribute \src "libresoc.v:198395.3-198416.6"
+  attribute \src "libresoc.v:198403.3-198424.6"
   wire width 64 $1\data_r3__nia$next[63:0]$14499
-  attribute \src "libresoc.v:197761.14-197761.49"
+  attribute \src "libresoc.v:197769.14-197769.49"
   wire width 64 $1\data_r3__nia[63:0]
-  attribute \src "libresoc.v:198395.3-198416.6"
+  attribute \src "libresoc.v:198403.3-198424.6"
   wire $1\data_r3__nia_ok$next[0:0]$14500
-  attribute \src "libresoc.v:197765.7-197765.29"
+  attribute \src "libresoc.v:197773.7-197773.29"
   wire $1\data_r3__nia_ok[0:0]
-  attribute \src "libresoc.v:198417.3-198438.6"
+  attribute \src "libresoc.v:198425.3-198446.6"
   wire width 64 $1\data_r4__msr$next[63:0]$14507
-  attribute \src "libresoc.v:197769.14-197769.49"
+  attribute \src "libresoc.v:197777.14-197777.49"
   wire width 64 $1\data_r4__msr[63:0]
-  attribute \src "libresoc.v:198417.3-198438.6"
+  attribute \src "libresoc.v:198425.3-198446.6"
   wire $1\data_r4__msr_ok$next[0:0]$14508
-  attribute \src "libresoc.v:197773.7-197773.29"
+  attribute \src "libresoc.v:197781.7-197781.29"
   wire $1\data_r4__msr_ok[0:0]
-  attribute \src "libresoc.v:198497.3-198506.6"
+  attribute \src "libresoc.v:198505.3-198514.6"
   wire width 64 $1\dest1_o[63:0]
-  attribute \src "libresoc.v:198507.3-198516.6"
+  attribute \src "libresoc.v:198515.3-198524.6"
   wire width 64 $1\dest2_o[63:0]
-  attribute \src "libresoc.v:198517.3-198526.6"
+  attribute \src "libresoc.v:198525.3-198534.6"
   wire width 64 $1\dest3_o[63:0]
-  attribute \src "libresoc.v:198527.3-198536.6"
+  attribute \src "libresoc.v:198535.3-198544.6"
   wire width 64 $1\dest4_o[63:0]
-  attribute \src "libresoc.v:198537.3-198546.6"
+  attribute \src "libresoc.v:198545.3-198554.6"
   wire width 64 $1\dest5_o[63:0]
-  attribute \src "libresoc.v:198266.3-198274.6"
+  attribute \src "libresoc.v:198274.3-198282.6"
   wire $1\opc_l_r_opc$next[0:0]$14440
-  attribute \src "libresoc.v:197804.7-197804.25"
+  attribute \src "libresoc.v:197812.7-197812.25"
   wire $1\opc_l_r_opc[0:0]
-  attribute \src "libresoc.v:198257.3-198265.6"
+  attribute \src "libresoc.v:198265.3-198273.6"
   wire $1\opc_l_s_opc$next[0:0]$14437
-  attribute \src "libresoc.v:197808.7-197808.25"
+  attribute \src "libresoc.v:197816.7-197816.25"
   wire $1\opc_l_s_opc[0:0]
-  attribute \src "libresoc.v:198547.3-198555.6"
+  attribute \src "libresoc.v:198555.3-198563.6"
   wire width 5 $1\prev_wr_go$next[4:0]$14537
-  attribute \src "libresoc.v:197918.13-197918.31"
+  attribute \src "libresoc.v:197926.13-197926.31"
   wire width 5 $1\prev_wr_go[4:0]
-  attribute \src "libresoc.v:198211.3-198220.6"
+  attribute \src "libresoc.v:198219.3-198228.6"
   wire $1\req_done[0:0]
-  attribute \src "libresoc.v:198302.3-198310.6"
+  attribute \src "libresoc.v:198310.3-198318.6"
   wire width 5 $1\req_l_r_req$next[4:0]$14452
-  attribute \src "libresoc.v:197926.13-197926.32"
+  attribute \src "libresoc.v:197934.13-197934.32"
   wire width 5 $1\req_l_r_req[4:0]
-  attribute \src "libresoc.v:198293.3-198301.6"
+  attribute \src "libresoc.v:198301.3-198309.6"
   wire width 5 $1\req_l_s_req$next[4:0]$14449
-  attribute \src "libresoc.v:197930.13-197930.32"
+  attribute \src "libresoc.v:197938.13-197938.32"
   wire width 5 $1\req_l_s_req[4:0]
-  attribute \src "libresoc.v:198230.3-198238.6"
+  attribute \src "libresoc.v:198238.3-198246.6"
   wire $1\rok_l_r_rdok$next[0:0]$14428
-  attribute \src "libresoc.v:197942.7-197942.26"
+  attribute \src "libresoc.v:197950.7-197950.26"
   wire $1\rok_l_r_rdok[0:0]
-  attribute \src "libresoc.v:198221.3-198229.6"
+  attribute \src "libresoc.v:198229.3-198237.6"
   wire $1\rok_l_s_rdok$next[0:0]$14425
-  attribute \src "libresoc.v:197946.7-197946.26"
+  attribute \src "libresoc.v:197954.7-197954.26"
   wire $1\rok_l_s_rdok[0:0]
-  attribute \src "libresoc.v:198248.3-198256.6"
+  attribute \src "libresoc.v:198256.3-198264.6"
   wire $1\rst_l_r_rst$next[0:0]$14434
-  attribute \src "libresoc.v:197950.7-197950.25"
+  attribute \src "libresoc.v:197958.7-197958.25"
   wire $1\rst_l_r_rst[0:0]
-  attribute \src "libresoc.v:198239.3-198247.6"
+  attribute \src "libresoc.v:198247.3-198255.6"
   wire $1\rst_l_s_rst$next[0:0]$14431
-  attribute \src "libresoc.v:197954.7-197954.25"
+  attribute \src "libresoc.v:197962.7-197962.25"
   wire $1\rst_l_s_rst[0:0]
-  attribute \src "libresoc.v:198284.3-198292.6"
+  attribute \src "libresoc.v:198292.3-198300.6"
   wire width 4 $1\src_l_r_src$next[3:0]$14446
-  attribute \src "libresoc.v:197970.13-197970.31"
+  attribute \src "libresoc.v:197978.13-197978.31"
   wire width 4 $1\src_l_r_src[3:0]
-  attribute \src "libresoc.v:198275.3-198283.6"
+  attribute \src "libresoc.v:198283.3-198291.6"
   wire width 4 $1\src_l_s_src$next[3:0]$14443
-  attribute \src "libresoc.v:197974.13-197974.31"
+  attribute \src "libresoc.v:197982.13-197982.31"
   wire width 4 $1\src_l_s_src[3:0]
-  attribute \src "libresoc.v:198439.3-198448.6"
+  attribute \src "libresoc.v:198447.3-198456.6"
   wire width 64 $1\src_r0$next[63:0]$14514
-  attribute \src "libresoc.v:197978.14-197978.43"
+  attribute \src "libresoc.v:197986.14-197986.43"
   wire width 64 $1\src_r0[63:0]
-  attribute \src "libresoc.v:198449.3-198458.6"
+  attribute \src "libresoc.v:198457.3-198466.6"
   wire width 64 $1\src_r1$next[63:0]$14517
-  attribute \src "libresoc.v:197982.14-197982.43"
+  attribute \src "libresoc.v:197990.14-197990.43"
   wire width 64 $1\src_r1[63:0]
-  attribute \src "libresoc.v:198459.3-198468.6"
+  attribute \src "libresoc.v:198467.3-198476.6"
   wire width 64 $1\src_r2$next[63:0]$14520
-  attribute \src "libresoc.v:197986.14-197986.43"
+  attribute \src "libresoc.v:197994.14-197994.43"
   wire width 64 $1\src_r2[63:0]
-  attribute \src "libresoc.v:198469.3-198478.6"
+  attribute \src "libresoc.v:198477.3-198486.6"
   wire width 64 $1\src_r3$next[63:0]$14523
-  attribute \src "libresoc.v:197990.14-197990.43"
+  attribute \src "libresoc.v:197998.14-197998.43"
   wire width 64 $1\src_r3[63:0]
-  attribute \src "libresoc.v:198329.3-198350.6"
+  attribute \src "libresoc.v:198337.3-198358.6"
   wire width 64 $2\data_r0__o$next[63:0]$14477
-  attribute \src "libresoc.v:198329.3-198350.6"
+  attribute \src "libresoc.v:198337.3-198358.6"
   wire $2\data_r0__o_ok$next[0:0]$14478
-  attribute \src "libresoc.v:198351.3-198372.6"
+  attribute \src "libresoc.v:198359.3-198380.6"
   wire width 64 $2\data_r1__fast1$next[63:0]$14485
-  attribute \src "libresoc.v:198351.3-198372.6"
+  attribute \src "libresoc.v:198359.3-198380.6"
   wire $2\data_r1__fast1_ok$next[0:0]$14486
-  attribute \src "libresoc.v:198373.3-198394.6"
+  attribute \src "libresoc.v:198381.3-198402.6"
   wire width 64 $2\data_r2__fast2$next[63:0]$14493
-  attribute \src "libresoc.v:198373.3-198394.6"
+  attribute \src "libresoc.v:198381.3-198402.6"
   wire $2\data_r2__fast2_ok$next[0:0]$14494
-  attribute \src "libresoc.v:198395.3-198416.6"
+  attribute \src "libresoc.v:198403.3-198424.6"
   wire width 64 $2\data_r3__nia$next[63:0]$14501
-  attribute \src "libresoc.v:198395.3-198416.6"
+  attribute \src "libresoc.v:198403.3-198424.6"
   wire $2\data_r3__nia_ok$next[0:0]$14502
-  attribute \src "libresoc.v:198417.3-198438.6"
+  attribute \src "libresoc.v:198425.3-198446.6"
   wire width 64 $2\data_r4__msr$next[63:0]$14509
-  attribute \src "libresoc.v:198417.3-198438.6"
+  attribute \src "libresoc.v:198425.3-198446.6"
   wire $2\data_r4__msr_ok$next[0:0]$14510
-  attribute \src "libresoc.v:198329.3-198350.6"
+  attribute \src "libresoc.v:198337.3-198358.6"
   wire $3\data_r0__o_ok$next[0:0]$14479
-  attribute \src "libresoc.v:198351.3-198372.6"
+  attribute \src "libresoc.v:198359.3-198380.6"
   wire $3\data_r1__fast1_ok$next[0:0]$14487
-  attribute \src "libresoc.v:198373.3-198394.6"
+  attribute \src "libresoc.v:198381.3-198402.6"
   wire $3\data_r2__fast2_ok$next[0:0]$14495
-  attribute \src "libresoc.v:198395.3-198416.6"
+  attribute \src "libresoc.v:198403.3-198424.6"
   wire $3\data_r3__nia_ok$next[0:0]$14503
-  attribute \src "libresoc.v:198417.3-198438.6"
+  attribute \src "libresoc.v:198425.3-198446.6"
   wire $3\data_r4__msr_ok$next[0:0]$14511
-  attribute \src "libresoc.v:197996.18-197996.112"
-  wire width 4 $and$libresoc.v:197996$14324_Y
-  attribute \src "libresoc.v:197997.19-197997.125"
-  wire $and$libresoc.v:197997$14325_Y
-  attribute \src "libresoc.v:197998.19-197998.125"
-  wire $and$libresoc.v:197998$14326_Y
-  attribute \src "libresoc.v:197999.19-197999.125"
-  wire $and$libresoc.v:197999$14327_Y
-  attribute \src "libresoc.v:198000.19-198000.125"
-  wire $and$libresoc.v:198000$14328_Y
-  attribute \src "libresoc.v:198001.19-198001.125"
-  wire $and$libresoc.v:198001$14329_Y
-  attribute \src "libresoc.v:198002.19-198002.157"
-  wire width 5 $and$libresoc.v:198002$14330_Y
-  attribute \src "libresoc.v:198003.19-198003.121"
-  wire width 5 $and$libresoc.v:198003$14331_Y
-  attribute \src "libresoc.v:198004.19-198004.127"
-  wire $and$libresoc.v:198004$14332_Y
-  attribute \src "libresoc.v:198005.19-198005.127"
-  wire $and$libresoc.v:198005$14333_Y
-  attribute \src "libresoc.v:198006.18-198006.110"
-  wire $and$libresoc.v:198006$14334_Y
-  attribute \src "libresoc.v:198007.19-198007.127"
-  wire $and$libresoc.v:198007$14335_Y
-  attribute \src "libresoc.v:198008.19-198008.127"
-  wire $and$libresoc.v:198008$14336_Y
-  attribute \src "libresoc.v:198009.19-198009.127"
-  wire $and$libresoc.v:198009$14337_Y
-  attribute \src "libresoc.v:198011.18-198011.98"
-  wire $and$libresoc.v:198011$14339_Y
-  attribute \src "libresoc.v:198013.18-198013.100"
-  wire $and$libresoc.v:198013$14341_Y
-  attribute \src "libresoc.v:198014.18-198014.171"
-  wire width 5 $and$libresoc.v:198014$14342_Y
-  attribute \src "libresoc.v:198016.18-198016.119"
-  wire width 5 $and$libresoc.v:198016$14344_Y
-  attribute \src "libresoc.v:198019.18-198019.116"
-  wire $and$libresoc.v:198019$14347_Y
-  attribute \src "libresoc.v:198023.17-198023.123"
-  wire $and$libresoc.v:198023$14351_Y
-  attribute \src "libresoc.v:198025.18-198025.113"
-  wire $and$libresoc.v:198025$14353_Y
-  attribute \src "libresoc.v:198026.18-198026.125"
-  wire width 5 $and$libresoc.v:198026$14354_Y
-  attribute \src "libresoc.v:198028.18-198028.112"
-  wire $and$libresoc.v:198028$14356_Y
-  attribute \src "libresoc.v:198030.18-198030.127"
-  wire $and$libresoc.v:198030$14358_Y
-  attribute \src "libresoc.v:198031.18-198031.127"
-  wire $and$libresoc.v:198031$14359_Y
-  attribute \src "libresoc.v:198032.18-198032.117"
-  wire $and$libresoc.v:198032$14360_Y
-  attribute \src "libresoc.v:198037.18-198037.131"
-  wire $and$libresoc.v:198037$14365_Y
-  attribute \src "libresoc.v:198038.18-198038.124"
-  wire width 5 $and$libresoc.v:198038$14366_Y
-  attribute \src "libresoc.v:198041.18-198041.116"
-  wire $and$libresoc.v:198041$14369_Y
-  attribute \src "libresoc.v:198042.18-198042.120"
-  wire $and$libresoc.v:198042$14370_Y
-  attribute \src "libresoc.v:198043.18-198043.120"
-  wire $and$libresoc.v:198043$14371_Y
-  attribute \src "libresoc.v:198044.18-198044.118"
-  wire $and$libresoc.v:198044$14372_Y
-  attribute \src "libresoc.v:198045.18-198045.118"
-  wire $and$libresoc.v:198045$14373_Y
-  attribute \src "libresoc.v:198051.18-198051.135"
-  wire $and$libresoc.v:198051$14379_Y
-  attribute \src "libresoc.v:198052.18-198052.133"
-  wire $and$libresoc.v:198052$14380_Y
-  attribute \src "libresoc.v:198053.18-198053.160"
-  wire width 4 $and$libresoc.v:198053$14381_Y
-  attribute \src "libresoc.v:198054.18-198054.112"
-  wire width 4 $and$libresoc.v:198054$14382_Y
-  attribute \src "libresoc.v:198027.18-198027.113"
-  wire $eq$libresoc.v:198027$14355_Y
-  attribute \src "libresoc.v:198029.18-198029.119"
-  wire $eq$libresoc.v:198029$14357_Y
-  attribute \src "libresoc.v:198010.18-198010.97"
-  wire $not$libresoc.v:198010$14338_Y
-  attribute \src "libresoc.v:198012.18-198012.99"
-  wire $not$libresoc.v:198012$14340_Y
-  attribute \src "libresoc.v:198015.18-198015.113"
-  wire width 5 $not$libresoc.v:198015$14343_Y
-  attribute \src "libresoc.v:198018.18-198018.106"
-  wire $not$libresoc.v:198018$14346_Y
-  attribute \src "libresoc.v:198024.18-198024.121"
-  wire $not$libresoc.v:198024$14352_Y
-  attribute \src "libresoc.v:198039.17-198039.113"
-  wire width 4 $not$libresoc.v:198039$14367_Y
-  attribute \src "libresoc.v:198055.18-198055.114"
-  wire width 4 $not$libresoc.v:198055$14383_Y
-  attribute \src "libresoc.v:198022.18-198022.112"
-  wire $or$libresoc.v:198022$14350_Y
-  attribute \src "libresoc.v:198033.18-198033.122"
-  wire $or$libresoc.v:198033$14361_Y
-  attribute \src "libresoc.v:198034.18-198034.124"
-  wire $or$libresoc.v:198034$14362_Y
-  attribute \src "libresoc.v:198035.18-198035.181"
-  wire width 5 $or$libresoc.v:198035$14363_Y
-  attribute \src "libresoc.v:198036.18-198036.168"
-  wire width 4 $or$libresoc.v:198036$14364_Y
-  attribute \src "libresoc.v:198040.18-198040.120"
-  wire width 5 $or$libresoc.v:198040$14368_Y
-  attribute \src "libresoc.v:198050.17-198050.117"
-  wire width 4 $or$libresoc.v:198050$14378_Y
-  attribute \src "libresoc.v:197995.17-197995.104"
-  wire $reduce_and$libresoc.v:197995$14323_Y
-  attribute \src "libresoc.v:198017.18-198017.106"
-  wire $reduce_or$libresoc.v:198017$14345_Y
-  attribute \src "libresoc.v:198020.18-198020.113"
-  wire $reduce_or$libresoc.v:198020$14348_Y
-  attribute \src "libresoc.v:198021.18-198021.112"
-  wire $reduce_or$libresoc.v:198021$14349_Y
-  attribute \src "libresoc.v:198046.18-198046.118"
-  wire width 64 $ternary$libresoc.v:198046$14374_Y
-  attribute \src "libresoc.v:198047.18-198047.118"
-  wire width 64 $ternary$libresoc.v:198047$14375_Y
-  attribute \src "libresoc.v:198048.18-198048.118"
-  wire width 64 $ternary$libresoc.v:198048$14376_Y
-  attribute \src "libresoc.v:198049.18-198049.118"
-  wire width 64 $ternary$libresoc.v:198049$14377_Y
+  attribute \src "libresoc.v:198004.18-198004.112"
+  wire width 4 $and$libresoc.v:198004$14324_Y
+  attribute \src "libresoc.v:198005.19-198005.125"
+  wire $and$libresoc.v:198005$14325_Y
+  attribute \src "libresoc.v:198006.19-198006.125"
+  wire $and$libresoc.v:198006$14326_Y
+  attribute \src "libresoc.v:198007.19-198007.125"
+  wire $and$libresoc.v:198007$14327_Y
+  attribute \src "libresoc.v:198008.19-198008.125"
+  wire $and$libresoc.v:198008$14328_Y
+  attribute \src "libresoc.v:198009.19-198009.125"
+  wire $and$libresoc.v:198009$14329_Y
+  attribute \src "libresoc.v:198010.19-198010.157"
+  wire width 5 $and$libresoc.v:198010$14330_Y
+  attribute \src "libresoc.v:198011.19-198011.121"
+  wire width 5 $and$libresoc.v:198011$14331_Y
+  attribute \src "libresoc.v:198012.19-198012.127"
+  wire $and$libresoc.v:198012$14332_Y
+  attribute \src "libresoc.v:198013.19-198013.127"
+  wire $and$libresoc.v:198013$14333_Y
+  attribute \src "libresoc.v:198014.18-198014.110"
+  wire $and$libresoc.v:198014$14334_Y
+  attribute \src "libresoc.v:198015.19-198015.127"
+  wire $and$libresoc.v:198015$14335_Y
+  attribute \src "libresoc.v:198016.19-198016.127"
+  wire $and$libresoc.v:198016$14336_Y
+  attribute \src "libresoc.v:198017.19-198017.127"
+  wire $and$libresoc.v:198017$14337_Y
+  attribute \src "libresoc.v:198019.18-198019.98"
+  wire $and$libresoc.v:198019$14339_Y
+  attribute \src "libresoc.v:198021.18-198021.100"
+  wire $and$libresoc.v:198021$14341_Y
+  attribute \src "libresoc.v:198022.18-198022.171"
+  wire width 5 $and$libresoc.v:198022$14342_Y
+  attribute \src "libresoc.v:198024.18-198024.119"
+  wire width 5 $and$libresoc.v:198024$14344_Y
+  attribute \src "libresoc.v:198027.18-198027.116"
+  wire $and$libresoc.v:198027$14347_Y
+  attribute \src "libresoc.v:198031.17-198031.123"
+  wire $and$libresoc.v:198031$14351_Y
+  attribute \src "libresoc.v:198033.18-198033.113"
+  wire $and$libresoc.v:198033$14353_Y
+  attribute \src "libresoc.v:198034.18-198034.125"
+  wire width 5 $and$libresoc.v:198034$14354_Y
+  attribute \src "libresoc.v:198036.18-198036.112"
+  wire $and$libresoc.v:198036$14356_Y
+  attribute \src "libresoc.v:198038.18-198038.127"
+  wire $and$libresoc.v:198038$14358_Y
+  attribute \src "libresoc.v:198039.18-198039.127"
+  wire $and$libresoc.v:198039$14359_Y
+  attribute \src "libresoc.v:198040.18-198040.117"
+  wire $and$libresoc.v:198040$14360_Y
+  attribute \src "libresoc.v:198045.18-198045.131"
+  wire $and$libresoc.v:198045$14365_Y
+  attribute \src "libresoc.v:198046.18-198046.124"
+  wire width 5 $and$libresoc.v:198046$14366_Y
+  attribute \src "libresoc.v:198049.18-198049.116"
+  wire $and$libresoc.v:198049$14369_Y
+  attribute \src "libresoc.v:198050.18-198050.120"
+  wire $and$libresoc.v:198050$14370_Y
+  attribute \src "libresoc.v:198051.18-198051.120"
+  wire $and$libresoc.v:198051$14371_Y
+  attribute \src "libresoc.v:198052.18-198052.118"
+  wire $and$libresoc.v:198052$14372_Y
+  attribute \src "libresoc.v:198053.18-198053.118"
+  wire $and$libresoc.v:198053$14373_Y
+  attribute \src "libresoc.v:198059.18-198059.135"
+  wire $and$libresoc.v:198059$14379_Y
+  attribute \src "libresoc.v:198060.18-198060.133"
+  wire $and$libresoc.v:198060$14380_Y
+  attribute \src "libresoc.v:198061.18-198061.160"
+  wire width 4 $and$libresoc.v:198061$14381_Y
+  attribute \src "libresoc.v:198062.18-198062.112"
+  wire width 4 $and$libresoc.v:198062$14382_Y
+  attribute \src "libresoc.v:198035.18-198035.113"
+  wire $eq$libresoc.v:198035$14355_Y
+  attribute \src "libresoc.v:198037.18-198037.119"
+  wire $eq$libresoc.v:198037$14357_Y
+  attribute \src "libresoc.v:198018.18-198018.97"
+  wire $not$libresoc.v:198018$14338_Y
+  attribute \src "libresoc.v:198020.18-198020.99"
+  wire $not$libresoc.v:198020$14340_Y
+  attribute \src "libresoc.v:198023.18-198023.113"
+  wire width 5 $not$libresoc.v:198023$14343_Y
+  attribute \src "libresoc.v:198026.18-198026.106"
+  wire $not$libresoc.v:198026$14346_Y
+  attribute \src "libresoc.v:198032.18-198032.121"
+  wire $not$libresoc.v:198032$14352_Y
+  attribute \src "libresoc.v:198047.17-198047.113"
+  wire width 4 $not$libresoc.v:198047$14367_Y
+  attribute \src "libresoc.v:198063.18-198063.114"
+  wire width 4 $not$libresoc.v:198063$14383_Y
+  attribute \src "libresoc.v:198030.18-198030.112"
+  wire $or$libresoc.v:198030$14350_Y
+  attribute \src "libresoc.v:198041.18-198041.122"
+  wire $or$libresoc.v:198041$14361_Y
+  attribute \src "libresoc.v:198042.18-198042.124"
+  wire $or$libresoc.v:198042$14362_Y
+  attribute \src "libresoc.v:198043.18-198043.181"
+  wire width 5 $or$libresoc.v:198043$14363_Y
+  attribute \src "libresoc.v:198044.18-198044.168"
+  wire width 4 $or$libresoc.v:198044$14364_Y
+  attribute \src "libresoc.v:198048.18-198048.120"
+  wire width 5 $or$libresoc.v:198048$14368_Y
+  attribute \src "libresoc.v:198058.17-198058.117"
+  wire width 4 $or$libresoc.v:198058$14378_Y
+  attribute \src "libresoc.v:198003.17-198003.104"
+  wire $reduce_and$libresoc.v:198003$14323_Y
+  attribute \src "libresoc.v:198025.18-198025.106"
+  wire $reduce_or$libresoc.v:198025$14345_Y
+  attribute \src "libresoc.v:198028.18-198028.113"
+  wire $reduce_or$libresoc.v:198028$14348_Y
+  attribute \src "libresoc.v:198029.18-198029.112"
+  wire $reduce_or$libresoc.v:198029$14349_Y
+  attribute \src "libresoc.v:198054.18-198054.118"
+  wire width 64 $ternary$libresoc.v:198054$14374_Y
+  attribute \src "libresoc.v:198055.18-198055.118"
+  wire width 64 $ternary$libresoc.v:198055$14375_Y
+  attribute \src "libresoc.v:198056.18-198056.118"
+  wire width 64 $ternary$libresoc.v:198056$14376_Y
+  attribute \src "libresoc.v:198057.18-198057.118"
+  wire width 64 $ternary$libresoc.v:198057$14377_Y
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
   wire \$101
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
@@ -413940,9 +413948,9 @@ module \trap0
   wire \alui_l_r_alui$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
   wire \alui_l_s_alui
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 32 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
   wire output 12 \cu_busy_o
@@ -414020,7 +414028,7 @@ module \trap0
   wire output 24 \fast1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire output 25 \fast2_ok
-  attribute \src "libresoc.v:197399.7-197399.15"
+  attribute \src "libresoc.v:197407.7-197407.15"
   wire \initial
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
   wire output 30 \msr_ok
@@ -414223,7 +414231,7 @@ module \trap0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
   wire \wr_any
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
-  cell $and $and$libresoc.v:197996$14324
+  cell $and $and$libresoc.v:198004$14324
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -414231,10 +414239,10 @@ module \trap0
     parameter \Y_WIDTH 4
     connect \A \$95
     connect \B \$97
-    connect \Y $and$libresoc.v:197996$14324_Y
+    connect \Y $and$libresoc.v:198004$14324_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
-  cell $and $and$libresoc.v:197997$14325
+  cell $and $and$libresoc.v:198005$14325
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414242,10 +414250,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \cu_busy_o
     connect \B \cu_shadown_i
-    connect \Y $and$libresoc.v:197997$14325_Y
+    connect \Y $and$libresoc.v:198005$14325_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
-  cell $and $and$libresoc.v:197998$14326
+  cell $and $and$libresoc.v:198006$14326
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414253,10 +414261,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \cu_busy_o
     connect \B \cu_shadown_i
-    connect \Y $and$libresoc.v:197998$14326_Y
+    connect \Y $and$libresoc.v:198006$14326_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
-  cell $and $and$libresoc.v:197999$14327
+  cell $and $and$libresoc.v:198007$14327
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414264,10 +414272,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \cu_busy_o
     connect \B \cu_shadown_i
-    connect \Y $and$libresoc.v:197999$14327_Y
+    connect \Y $and$libresoc.v:198007$14327_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
-  cell $and $and$libresoc.v:198000$14328
+  cell $and $and$libresoc.v:198008$14328
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414275,10 +414283,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \cu_busy_o
     connect \B \cu_shadown_i
-    connect \Y $and$libresoc.v:198000$14328_Y
+    connect \Y $and$libresoc.v:198008$14328_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
-  cell $and $and$libresoc.v:198001$14329
+  cell $and $and$libresoc.v:198009$14329
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414286,10 +414294,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \cu_busy_o
     connect \B \cu_shadown_i
-    connect \Y $and$libresoc.v:198001$14329_Y
+    connect \Y $and$libresoc.v:198009$14329_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
-  cell $and $and$libresoc.v:198002$14330
+  cell $and $and$libresoc.v:198010$14330
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -414297,10 +414305,10 @@ module \trap0
     parameter \Y_WIDTH 5
     connect \A \req_l_q_req
     connect \B { \$101 \$103 \$105 \$107 \$109 }
-    connect \Y $and$libresoc.v:198002$14330_Y
+    connect \Y $and$libresoc.v:198010$14330_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
-  cell $and $and$libresoc.v:198003$14331
+  cell $and $and$libresoc.v:198011$14331
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -414308,10 +414316,10 @@ module \trap0
     parameter \Y_WIDTH 5
     connect \A \$111
     connect \B \cu_wrmask_o
-    connect \Y $and$libresoc.v:198003$14331_Y
+    connect \Y $and$libresoc.v:198011$14331_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
-  cell $and $and$libresoc.v:198004$14332
+  cell $and $and$libresoc.v:198012$14332
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414319,10 +414327,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \cu_wr__go_i [0]
     connect \B \cu_busy_o
-    connect \Y $and$libresoc.v:198004$14332_Y
+    connect \Y $and$libresoc.v:198012$14332_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
-  cell $and $and$libresoc.v:198005$14333
+  cell $and $and$libresoc.v:198013$14333
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414330,10 +414338,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \cu_wr__go_i [1]
     connect \B \cu_busy_o
-    connect \Y $and$libresoc.v:198005$14333_Y
+    connect \Y $and$libresoc.v:198013$14333_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
-  cell $and $and$libresoc.v:198006$14334
+  cell $and $and$libresoc.v:198014$14334
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414341,10 +414349,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \$3
     connect \B \$5
-    connect \Y $and$libresoc.v:198006$14334_Y
+    connect \Y $and$libresoc.v:198014$14334_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
-  cell $and $and$libresoc.v:198007$14335
+  cell $and $and$libresoc.v:198015$14335
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414352,10 +414360,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \cu_wr__go_i [2]
     connect \B \cu_busy_o
-    connect \Y $and$libresoc.v:198007$14335_Y
+    connect \Y $and$libresoc.v:198015$14335_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
-  cell $and $and$libresoc.v:198008$14336
+  cell $and $and$libresoc.v:198016$14336
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414363,10 +414371,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \cu_wr__go_i [3]
     connect \B \cu_busy_o
-    connect \Y $and$libresoc.v:198008$14336_Y
+    connect \Y $and$libresoc.v:198016$14336_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
-  cell $and $and$libresoc.v:198009$14337
+  cell $and $and$libresoc.v:198017$14337
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414374,10 +414382,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \cu_wr__go_i [4]
     connect \B \cu_busy_o
-    connect \Y $and$libresoc.v:198009$14337_Y
+    connect \Y $and$libresoc.v:198017$14337_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
-  cell $and $and$libresoc.v:198011$14339
+  cell $and $and$libresoc.v:198019$14339
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414385,10 +414393,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \all_rd
     connect \B \$13
-    connect \Y $and$libresoc.v:198011$14339_Y
+    connect \Y $and$libresoc.v:198019$14339_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
-  cell $and $and$libresoc.v:198013$14341
+  cell $and $and$libresoc.v:198021$14341
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414396,10 +414404,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \alu_done
     connect \B \$17
-    connect \Y $and$libresoc.v:198013$14341_Y
+    connect \Y $and$libresoc.v:198021$14341_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
-  cell $and $and$libresoc.v:198014$14342
+  cell $and $and$libresoc.v:198022$14342
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -414407,10 +414415,10 @@ module \trap0
     parameter \Y_WIDTH 5
     connect \A \cu_wr__go_i
     connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
-    connect \Y $and$libresoc.v:198014$14342_Y
+    connect \Y $and$libresoc.v:198022$14342_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
-  cell $and $and$libresoc.v:198016$14344
+  cell $and $and$libresoc.v:198024$14344
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -414418,10 +414426,10 @@ module \trap0
     parameter \Y_WIDTH 5
     connect \A \cu_wr__rel_o
     connect \B \$25
-    connect \Y $and$libresoc.v:198016$14344_Y
+    connect \Y $and$libresoc.v:198024$14344_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
-  cell $and $and$libresoc.v:198019$14347
+  cell $and $and$libresoc.v:198027$14347
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414429,10 +414437,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \cu_busy_o
     connect \B \$23
-    connect \Y $and$libresoc.v:198019$14347_Y
+    connect \Y $and$libresoc.v:198027$14347_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
-  cell $and $and$libresoc.v:198023$14351
+  cell $and $and$libresoc.v:198031$14351
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414440,10 +414448,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \cu_busy_o
     connect \B \rok_l_q_rdok
-    connect \Y $and$libresoc.v:198023$14351_Y
+    connect \Y $and$libresoc.v:198031$14351_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
-  cell $and $and$libresoc.v:198025$14353
+  cell $and $and$libresoc.v:198033$14353
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414451,10 +414459,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \wr_any
     connect \B \$39
-    connect \Y $and$libresoc.v:198025$14353_Y
+    connect \Y $and$libresoc.v:198033$14353_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
-  cell $and $and$libresoc.v:198026$14354
+  cell $and $and$libresoc.v:198034$14354
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -414462,10 +414470,10 @@ module \trap0
     parameter \Y_WIDTH 5
     connect \A \req_l_q_req
     connect \B \cu_wrmask_o
-    connect \Y $and$libresoc.v:198026$14354_Y
+    connect \Y $and$libresoc.v:198034$14354_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
-  cell $and $and$libresoc.v:198028$14356
+  cell $and $and$libresoc.v:198036$14356
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414473,10 +414481,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \$41
     connect \B \$45
-    connect \Y $and$libresoc.v:198028$14356_Y
+    connect \Y $and$libresoc.v:198036$14356_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
-  cell $and $and$libresoc.v:198030$14358
+  cell $and $and$libresoc.v:198038$14358
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414484,10 +414492,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \$49
     connect \B \alu_trap0_n_ready_i
-    connect \Y $and$libresoc.v:198030$14358_Y
+    connect \Y $and$libresoc.v:198038$14358_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
-  cell $and $and$libresoc.v:198031$14359
+  cell $and $and$libresoc.v:198039$14359
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414495,10 +414503,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \$51
     connect \B \alu_trap0_n_valid_o
-    connect \Y $and$libresoc.v:198031$14359_Y
+    connect \Y $and$libresoc.v:198039$14359_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
-  cell $and $and$libresoc.v:198032$14360
+  cell $and $and$libresoc.v:198040$14360
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414506,10 +414514,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \$53
     connect \B \cu_busy_o
-    connect \Y $and$libresoc.v:198032$14360_Y
+    connect \Y $and$libresoc.v:198040$14360_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
-  cell $and $and$libresoc.v:198037$14365
+  cell $and $and$libresoc.v:198045$14365
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414517,10 +414525,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \alu_trap0_n_valid_o
     connect \B \cu_busy_o
-    connect \Y $and$libresoc.v:198037$14365_Y
+    connect \Y $and$libresoc.v:198045$14365_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
-  cell $and $and$libresoc.v:198038$14366
+  cell $and $and$libresoc.v:198046$14366
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -414528,10 +414536,10 @@ module \trap0
     parameter \Y_WIDTH 5
     connect \A \alu_pulsem
     connect \B \cu_wrmask_o
-    connect \Y $and$libresoc.v:198038$14366_Y
+    connect \Y $and$libresoc.v:198046$14366_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
-  cell $and $and$libresoc.v:198041$14369
+  cell $and $and$libresoc.v:198049$14369
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414539,10 +414547,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \o_ok
     connect \B \cu_busy_o
-    connect \Y $and$libresoc.v:198041$14369_Y
+    connect \Y $and$libresoc.v:198049$14369_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
-  cell $and $and$libresoc.v:198042$14370
+  cell $and $and$libresoc.v:198050$14370
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414550,10 +414558,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \fast1_ok
     connect \B \cu_busy_o
-    connect \Y $and$libresoc.v:198042$14370_Y
+    connect \Y $and$libresoc.v:198050$14370_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
-  cell $and $and$libresoc.v:198043$14371
+  cell $and $and$libresoc.v:198051$14371
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414561,10 +414569,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \fast2_ok
     connect \B \cu_busy_o
-    connect \Y $and$libresoc.v:198043$14371_Y
+    connect \Y $and$libresoc.v:198051$14371_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
-  cell $and $and$libresoc.v:198044$14372
+  cell $and $and$libresoc.v:198052$14372
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414572,10 +414580,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \nia_ok
     connect \B \cu_busy_o
-    connect \Y $and$libresoc.v:198044$14372_Y
+    connect \Y $and$libresoc.v:198052$14372_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
-  cell $and $and$libresoc.v:198045$14373
+  cell $and $and$libresoc.v:198053$14373
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414583,10 +414591,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \msr_ok
     connect \B \cu_busy_o
-    connect \Y $and$libresoc.v:198045$14373_Y
+    connect \Y $and$libresoc.v:198053$14373_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
-  cell $and $and$libresoc.v:198051$14379
+  cell $and $and$libresoc.v:198059$14379
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414594,10 +414602,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \alu_trap0_p_ready_o
     connect \B \alui_l_q_alui
-    connect \Y $and$libresoc.v:198051$14379_Y
+    connect \Y $and$libresoc.v:198059$14379_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
-  cell $and $and$libresoc.v:198052$14380
+  cell $and $and$libresoc.v:198060$14380
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414605,10 +414613,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \alu_trap0_n_valid_o
     connect \B \alu_l_q_alu
-    connect \Y $and$libresoc.v:198052$14380_Y
+    connect \Y $and$libresoc.v:198060$14380_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
-  cell $and $and$libresoc.v:198053$14381
+  cell $and $and$libresoc.v:198061$14381
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -414616,10 +414624,10 @@ module \trap0
     parameter \Y_WIDTH 4
     connect \A \src_l_q_src
     connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
-    connect \Y $and$libresoc.v:198053$14381_Y
+    connect \Y $and$libresoc.v:198061$14381_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
-  cell $and $and$libresoc.v:198054$14382
+  cell $and $and$libresoc.v:198062$14382
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -414627,10 +414635,10 @@ module \trap0
     parameter \Y_WIDTH 4
     connect \A \$93
     connect \B 4'1111
-    connect \Y $and$libresoc.v:198054$14382_Y
+    connect \Y $and$libresoc.v:198062$14382_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
-  cell $eq $eq$libresoc.v:198027$14355
+  cell $eq $eq$libresoc.v:198035$14355
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -414638,10 +414646,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \$43
     connect \B 1'0
-    connect \Y $eq$libresoc.v:198027$14355_Y
+    connect \Y $eq$libresoc.v:198035$14355_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
-  cell $eq $eq$libresoc.v:198029$14357
+  cell $eq $eq$libresoc.v:198037$14357
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -414649,66 +414657,66 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \cu_wrmask_o
     connect \B 1'0
-    connect \Y $eq$libresoc.v:198029$14357_Y
+    connect \Y $eq$libresoc.v:198037$14357_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
-  cell $not $not$libresoc.v:198010$14338
+  cell $not $not$libresoc.v:198018$14338
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \all_rd_dly
-    connect \Y $not$libresoc.v:198010$14338_Y
+    connect \Y $not$libresoc.v:198018$14338_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
-  cell $not $not$libresoc.v:198012$14340
+  cell $not $not$libresoc.v:198020$14340
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \alu_done_dly
-    connect \Y $not$libresoc.v:198012$14340_Y
+    connect \Y $not$libresoc.v:198020$14340_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
-  cell $not $not$libresoc.v:198015$14343
+  cell $not $not$libresoc.v:198023$14343
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 5
     connect \A \cu_wrmask_o
-    connect \Y $not$libresoc.v:198015$14343_Y
+    connect \Y $not$libresoc.v:198023$14343_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
-  cell $not $not$libresoc.v:198018$14346
+  cell $not $not$libresoc.v:198026$14346
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$24
-    connect \Y $not$libresoc.v:198018$14346_Y
+    connect \Y $not$libresoc.v:198026$14346_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
-  cell $not $not$libresoc.v:198024$14352
+  cell $not $not$libresoc.v:198032$14352
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \alu_trap0_n_ready_i
-    connect \Y $not$libresoc.v:198024$14352_Y
+    connect \Y $not$libresoc.v:198032$14352_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
-  cell $not $not$libresoc.v:198039$14367
+  cell $not $not$libresoc.v:198047$14367
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
     connect \A \cu_rd__rel_o
-    connect \Y $not$libresoc.v:198039$14367_Y
+    connect \Y $not$libresoc.v:198047$14367_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
-  cell $not $not$libresoc.v:198055$14383
+  cell $not $not$libresoc.v:198063$14383
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
     connect \A \cu_rdmaskn_i
-    connect \Y $not$libresoc.v:198055$14383_Y
+    connect \Y $not$libresoc.v:198063$14383_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
-  cell $or $or$libresoc.v:198022$14350
+  cell $or $or$libresoc.v:198030$14350
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414716,10 +414724,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \$33
     connect \B \$35
-    connect \Y $or$libresoc.v:198022$14350_Y
+    connect \Y $or$libresoc.v:198030$14350_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
-  cell $or $or$libresoc.v:198033$14361
+  cell $or $or$libresoc.v:198041$14361
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414727,10 +414735,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \req_done
     connect \B \cu_go_die_i
-    connect \Y $or$libresoc.v:198033$14361_Y
+    connect \Y $or$libresoc.v:198041$14361_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
-  cell $or $or$libresoc.v:198034$14362
+  cell $or $or$libresoc.v:198042$14362
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -414738,10 +414746,10 @@ module \trap0
     parameter \Y_WIDTH 1
     connect \A \cu_issue_i
     connect \B \cu_go_die_i
-    connect \Y $or$libresoc.v:198034$14362_Y
+    connect \Y $or$libresoc.v:198042$14362_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
-  cell $or $or$libresoc.v:198035$14363
+  cell $or $or$libresoc.v:198043$14363
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -414749,10 +414757,10 @@ module \trap0
     parameter \Y_WIDTH 5
     connect \A \cu_wr__go_i
     connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
-    connect \Y $or$libresoc.v:198035$14363_Y
+    connect \Y $or$libresoc.v:198043$14363_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
-  cell $or $or$libresoc.v:198036$14364
+  cell $or $or$libresoc.v:198044$14364
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -414760,10 +414768,10 @@ module \trap0
     parameter \Y_WIDTH 4
     connect \A \cu_rd__go_i
     connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
-    connect \Y $or$libresoc.v:198036$14364_Y
+    connect \Y $or$libresoc.v:198044$14364_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
-  cell $or $or$libresoc.v:198040$14368
+  cell $or $or$libresoc.v:198048$14368
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
@@ -414771,10 +414779,10 @@ module \trap0
     parameter \Y_WIDTH 5
     connect \A \reset_w
     connect \B \prev_wr_go
-    connect \Y $or$libresoc.v:198040$14368_Y
+    connect \Y $or$libresoc.v:198048$14368_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
-  cell $or $or$libresoc.v:198050$14378
+  cell $or $or$libresoc.v:198058$14378
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -414782,74 +414790,74 @@ module \trap0
     parameter \Y_WIDTH 4
     connect \A \$6
     connect \B \cu_rd__go_i
-    connect \Y $or$libresoc.v:198050$14378_Y
+    connect \Y $or$libresoc.v:198058$14378_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
-  cell $reduce_and $reduce_and$libresoc.v:197995$14323
+  cell $reduce_and $reduce_and$libresoc.v:198003$14323
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
     connect \A \$8
-    connect \Y $reduce_and$libresoc.v:197995$14323_Y
+    connect \Y $reduce_and$libresoc.v:198003$14323_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
-  cell $reduce_or $reduce_or$libresoc.v:198017$14345
+  cell $reduce_or $reduce_or$libresoc.v:198025$14345
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
     connect \A \$27
-    connect \Y $reduce_or$libresoc.v:198017$14345_Y
+    connect \Y $reduce_or$libresoc.v:198025$14345_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
-  cell $reduce_or $reduce_or$libresoc.v:198020$14348
+  cell $reduce_or $reduce_or$libresoc.v:198028$14348
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
     connect \A \cu_wr__go_i
-    connect \Y $reduce_or$libresoc.v:198020$14348_Y
+    connect \Y $reduce_or$libresoc.v:198028$14348_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
-  cell $reduce_or $reduce_or$libresoc.v:198021$14349
+  cell $reduce_or $reduce_or$libresoc.v:198029$14349
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
     connect \A \prev_wr_go
-    connect \Y $reduce_or$libresoc.v:198021$14349_Y
+    connect \Y $reduce_or$libresoc.v:198029$14349_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
-  cell $mux $ternary$libresoc.v:198046$14374
+  cell $mux $ternary$libresoc.v:198054$14374
     parameter \WIDTH 64
     connect \A \src_r0
     connect \B \src1_i
     connect \S \src_l_q_src [0]
-    connect \Y $ternary$libresoc.v:198046$14374_Y
+    connect \Y $ternary$libresoc.v:198054$14374_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
-  cell $mux $ternary$libresoc.v:198047$14375
+  cell $mux $ternary$libresoc.v:198055$14375
     parameter \WIDTH 64
     connect \A \src_r1
     connect \B \src2_i
     connect \S \src_l_q_src [1]
-    connect \Y $ternary$libresoc.v:198047$14375_Y
+    connect \Y $ternary$libresoc.v:198055$14375_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
-  cell $mux $ternary$libresoc.v:198048$14376
+  cell $mux $ternary$libresoc.v:198056$14376
     parameter \WIDTH 64
     connect \A \src_r2
     connect \B \src3_i
     connect \S \src_l_q_src [2]
-    connect \Y $ternary$libresoc.v:198048$14376_Y
+    connect \Y $ternary$libresoc.v:198056$14376_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
-  cell $mux $ternary$libresoc.v:198049$14377
+  cell $mux $ternary$libresoc.v:198057$14377
     parameter \WIDTH 64
     connect \A \src_r3
     connect \B \src4_i
     connect \S \src_l_q_src [3]
-    connect \Y $ternary$libresoc.v:198049$14377_Y
+    connect \Y $ternary$libresoc.v:198057$14377_Y
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:198132.14-198138.4"
+  attribute \src "libresoc.v:198140.14-198146.4"
   cell \alu_l$45 \alu_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -414858,7 +414866,7 @@ module \trap0
     connect \s_alu \alu_l_s_alu
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:198139.13-198169.4"
+  attribute \src "libresoc.v:198147.13-198177.4"
   cell \alu_trap0 \alu_trap0
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -414891,7 +414899,7 @@ module \trap0
     connect \trap_op__traptype \alu_trap0_trap_op__traptype
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:198170.15-198176.4"
+  attribute \src "libresoc.v:198178.15-198184.4"
   cell \alui_l$44 \alui_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -414900,7 +414908,7 @@ module \trap0
     connect \s_alui \alui_l_s_alui
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:198177.14-198183.4"
+  attribute \src "libresoc.v:198185.14-198191.4"
   cell \opc_l$40 \opc_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -414909,7 +414917,7 @@ module \trap0
     connect \s_opc \opc_l_s_opc
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:198184.14-198190.4"
+  attribute \src "libresoc.v:198192.14-198198.4"
   cell \req_l$41 \req_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -414918,7 +414926,7 @@ module \trap0
     connect \s_req \req_l_s_req
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:198191.14-198197.4"
+  attribute \src "libresoc.v:198199.14-198205.4"
   cell \rok_l$43 \rok_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -414927,7 +414935,7 @@ module \trap0
     connect \s_rdok \rok_l_s_rdok
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:198198.14-198203.4"
+  attribute \src "libresoc.v:198206.14-198211.4"
   cell \rst_l$42 \rst_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -414935,7 +414943,7 @@ module \trap0
     connect \s_rst \rst_l_s_rst
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:198204.14-198210.4"
+  attribute \src "libresoc.v:198212.14-198218.4"
   cell \src_l$39 \src_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -414943,592 +414951,592 @@ module \trap0
     connect \r_src \src_l_r_src
     connect \s_src \src_l_s_src
   end
-  attribute \src "libresoc.v:197399.7-197399.20"
-  process $proc$libresoc.v:197399$14538
+  attribute \src "libresoc.v:197407.7-197407.20"
+  process $proc$libresoc.v:197407$14538
     assign { } { }
     assign $0\initial[0:0] 1'0
     sync always
       update \initial $0\initial[0:0]
     sync init
   end
-  attribute \src "libresoc.v:197525.7-197525.24"
-  process $proc$libresoc.v:197525$14539
+  attribute \src "libresoc.v:197533.7-197533.24"
+  process $proc$libresoc.v:197533$14539
     assign { } { }
     assign $1\all_rd_dly[0:0] 1'0
     sync always
     sync init
       update \all_rd_dly $1\all_rd_dly[0:0]
   end
-  attribute \src "libresoc.v:197535.7-197535.26"
-  process $proc$libresoc.v:197535$14540
+  attribute \src "libresoc.v:197543.7-197543.26"
+  process $proc$libresoc.v:197543$14540
     assign { } { }
     assign $1\alu_done_dly[0:0] 1'0
     sync always
     sync init
       update \alu_done_dly $1\alu_done_dly[0:0]
   end
-  attribute \src "libresoc.v:197543.7-197543.25"
-  process $proc$libresoc.v:197543$14541
+  attribute \src "libresoc.v:197551.7-197551.25"
+  process $proc$libresoc.v:197551$14541
     assign { } { }
     assign $1\alu_l_r_alu[0:0] 1'1
     sync always
     sync init
       update \alu_l_r_alu $1\alu_l_r_alu[0:0]
   end
-  attribute \src "libresoc.v:197579.14-197579.59"
-  process $proc$libresoc.v:197579$14542
+  attribute \src "libresoc.v:197587.14-197587.59"
+  process $proc$libresoc.v:197587$14542
     assign { } { }
     assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0]
   end
-  attribute \src "libresoc.v:197597.14-197597.51"
-  process $proc$libresoc.v:197597$14543
+  attribute \src "libresoc.v:197605.14-197605.51"
+  process $proc$libresoc.v:197605$14543
     assign { } { }
     assign $1\alu_trap0_trap_op__fn_unit[12:0] 13'0000000000000
     sync always
     sync init
       update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[12:0]
   end
-  attribute \src "libresoc.v:197601.14-197601.45"
-  process $proc$libresoc.v:197601$14544
+  attribute \src "libresoc.v:197609.14-197609.45"
+  process $proc$libresoc.v:197609$14544
     assign { } { }
     assign $1\alu_trap0_trap_op__insn[31:0] 0
     sync always
     sync init
       update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0]
   end
-  attribute \src "libresoc.v:197679.13-197679.49"
-  process $proc$libresoc.v:197679$14545
+  attribute \src "libresoc.v:197687.13-197687.49"
+  process $proc$libresoc.v:197687$14545
     assign { } { }
     assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000
     sync always
     sync init
       update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0]
   end
-  attribute \src "libresoc.v:197683.7-197683.41"
-  process $proc$libresoc.v:197683$14546
+  attribute \src "libresoc.v:197691.7-197691.41"
+  process $proc$libresoc.v:197691$14546
     assign { } { }
     assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0
     sync always
     sync init
       update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0]
   end
-  attribute \src "libresoc.v:197687.13-197687.48"
-  process $proc$libresoc.v:197687$14547
+  attribute \src "libresoc.v:197695.13-197695.48"
+  process $proc$libresoc.v:197695$14547
     assign { } { }
     assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000
     sync always
     sync init
       update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0]
   end
-  attribute \src "libresoc.v:197691.14-197691.59"
-  process $proc$libresoc.v:197691$14548
+  attribute \src "libresoc.v:197699.14-197699.59"
+  process $proc$libresoc.v:197699$14548
     assign { } { }
     assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0]
   end
-  attribute \src "libresoc.v:197695.14-197695.52"
-  process $proc$libresoc.v:197695$14549
+  attribute \src "libresoc.v:197703.14-197703.52"
+  process $proc$libresoc.v:197703$14549
     assign { } { }
     assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000
     sync always
     sync init
       update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0]
   end
-  attribute \src "libresoc.v:197699.13-197699.48"
-  process $proc$libresoc.v:197699$14550
+  attribute \src "libresoc.v:197707.13-197707.48"
+  process $proc$libresoc.v:197707$14550
     assign { } { }
     assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000
     sync always
     sync init
       update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0]
   end
-  attribute \src "libresoc.v:197705.7-197705.27"
-  process $proc$libresoc.v:197705$14551
+  attribute \src "libresoc.v:197713.7-197713.27"
+  process $proc$libresoc.v:197713$14551
     assign { } { }
     assign $1\alui_l_r_alui[0:0] 1'1
     sync always
     sync init
       update \alui_l_r_alui $1\alui_l_r_alui[0:0]
   end
-  attribute \src "libresoc.v:197737.14-197737.47"
-  process $proc$libresoc.v:197737$14552
+  attribute \src "libresoc.v:197745.14-197745.47"
+  process $proc$libresoc.v:197745$14552
     assign { } { }
     assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \data_r0__o $1\data_r0__o[63:0]
   end
-  attribute \src "libresoc.v:197741.7-197741.27"
-  process $proc$libresoc.v:197741$14553
+  attribute \src "libresoc.v:197749.7-197749.27"
+  process $proc$libresoc.v:197749$14553
     assign { } { }
     assign $1\data_r0__o_ok[0:0] 1'0
     sync always
     sync init
       update \data_r0__o_ok $1\data_r0__o_ok[0:0]
   end
-  attribute \src "libresoc.v:197745.14-197745.51"
-  process $proc$libresoc.v:197745$14554
+  attribute \src "libresoc.v:197753.14-197753.51"
+  process $proc$libresoc.v:197753$14554
     assign { } { }
     assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \data_r1__fast1 $1\data_r1__fast1[63:0]
   end
-  attribute \src "libresoc.v:197749.7-197749.31"
-  process $proc$libresoc.v:197749$14555
+  attribute \src "libresoc.v:197757.7-197757.31"
+  process $proc$libresoc.v:197757$14555
     assign { } { }
     assign $1\data_r1__fast1_ok[0:0] 1'0
     sync always
     sync init
       update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0]
   end
-  attribute \src "libresoc.v:197753.14-197753.51"
-  process $proc$libresoc.v:197753$14556
+  attribute \src "libresoc.v:197761.14-197761.51"
+  process $proc$libresoc.v:197761$14556
     assign { } { }
     assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \data_r2__fast2 $1\data_r2__fast2[63:0]
   end
-  attribute \src "libresoc.v:197757.7-197757.31"
-  process $proc$libresoc.v:197757$14557
+  attribute \src "libresoc.v:197765.7-197765.31"
+  process $proc$libresoc.v:197765$14557
     assign { } { }
     assign $1\data_r2__fast2_ok[0:0] 1'0
     sync always
     sync init
       update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0]
   end
-  attribute \src "libresoc.v:197761.14-197761.49"
-  process $proc$libresoc.v:197761$14558
+  attribute \src "libresoc.v:197769.14-197769.49"
+  process $proc$libresoc.v:197769$14558
     assign { } { }
     assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \data_r3__nia $1\data_r3__nia[63:0]
   end
-  attribute \src "libresoc.v:197765.7-197765.29"
-  process $proc$libresoc.v:197765$14559
+  attribute \src "libresoc.v:197773.7-197773.29"
+  process $proc$libresoc.v:197773$14559
     assign { } { }
     assign $1\data_r3__nia_ok[0:0] 1'0
     sync always
     sync init
       update \data_r3__nia_ok $1\data_r3__nia_ok[0:0]
   end
-  attribute \src "libresoc.v:197769.14-197769.49"
-  process $proc$libresoc.v:197769$14560
+  attribute \src "libresoc.v:197777.14-197777.49"
+  process $proc$libresoc.v:197777$14560
     assign { } { }
     assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \data_r4__msr $1\data_r4__msr[63:0]
   end
-  attribute \src "libresoc.v:197773.7-197773.29"
-  process $proc$libresoc.v:197773$14561
+  attribute \src "libresoc.v:197781.7-197781.29"
+  process $proc$libresoc.v:197781$14561
     assign { } { }
     assign $1\data_r4__msr_ok[0:0] 1'0
     sync always
     sync init
       update \data_r4__msr_ok $1\data_r4__msr_ok[0:0]
   end
-  attribute \src "libresoc.v:197804.7-197804.25"
-  process $proc$libresoc.v:197804$14562
+  attribute \src "libresoc.v:197812.7-197812.25"
+  process $proc$libresoc.v:197812$14562
     assign { } { }
     assign $1\opc_l_r_opc[0:0] 1'1
     sync always
     sync init
       update \opc_l_r_opc $1\opc_l_r_opc[0:0]
   end
-  attribute \src "libresoc.v:197808.7-197808.25"
-  process $proc$libresoc.v:197808$14563
+  attribute \src "libresoc.v:197816.7-197816.25"
+  process $proc$libresoc.v:197816$14563
     assign { } { }
     assign $1\opc_l_s_opc[0:0] 1'0
     sync always
     sync init
       update \opc_l_s_opc $1\opc_l_s_opc[0:0]
   end
-  attribute \src "libresoc.v:197918.13-197918.31"
-  process $proc$libresoc.v:197918$14564
+  attribute \src "libresoc.v:197926.13-197926.31"
+  process $proc$libresoc.v:197926$14564
     assign { } { }
     assign $1\prev_wr_go[4:0] 5'00000
     sync always
     sync init
       update \prev_wr_go $1\prev_wr_go[4:0]
   end
-  attribute \src "libresoc.v:197926.13-197926.32"
-  process $proc$libresoc.v:197926$14565
+  attribute \src "libresoc.v:197934.13-197934.32"
+  process $proc$libresoc.v:197934$14565
     assign { } { }
     assign $1\req_l_r_req[4:0] 5'11111
     sync always
     sync init
       update \req_l_r_req $1\req_l_r_req[4:0]
   end
-  attribute \src "libresoc.v:197930.13-197930.32"
-  process $proc$libresoc.v:197930$14566
+  attribute \src "libresoc.v:197938.13-197938.32"
+  process $proc$libresoc.v:197938$14566
     assign { } { }
     assign $1\req_l_s_req[4:0] 5'00000
     sync always
     sync init
       update \req_l_s_req $1\req_l_s_req[4:0]
   end
-  attribute \src "libresoc.v:197942.7-197942.26"
-  process $proc$libresoc.v:197942$14567
+  attribute \src "libresoc.v:197950.7-197950.26"
+  process $proc$libresoc.v:197950$14567
     assign { } { }
     assign $1\rok_l_r_rdok[0:0] 1'1
     sync always
     sync init
       update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
   end
-  attribute \src "libresoc.v:197946.7-197946.26"
-  process $proc$libresoc.v:197946$14568
+  attribute \src "libresoc.v:197954.7-197954.26"
+  process $proc$libresoc.v:197954$14568
     assign { } { }
     assign $1\rok_l_s_rdok[0:0] 1'0
     sync always
     sync init
       update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
   end
-  attribute \src "libresoc.v:197950.7-197950.25"
-  process $proc$libresoc.v:197950$14569
+  attribute \src "libresoc.v:197958.7-197958.25"
+  process $proc$libresoc.v:197958$14569
     assign { } { }
     assign $1\rst_l_r_rst[0:0] 1'1
     sync always
     sync init
       update \rst_l_r_rst $1\rst_l_r_rst[0:0]
   end
-  attribute \src "libresoc.v:197954.7-197954.25"
-  process $proc$libresoc.v:197954$14570
+  attribute \src "libresoc.v:197962.7-197962.25"
+  process $proc$libresoc.v:197962$14570
     assign { } { }
     assign $1\rst_l_s_rst[0:0] 1'0
     sync always
     sync init
       update \rst_l_s_rst $1\rst_l_s_rst[0:0]
   end
-  attribute \src "libresoc.v:197970.13-197970.31"
-  process $proc$libresoc.v:197970$14571
+  attribute \src "libresoc.v:197978.13-197978.31"
+  process $proc$libresoc.v:197978$14571
     assign { } { }
     assign $1\src_l_r_src[3:0] 4'1111
     sync always
     sync init
       update \src_l_r_src $1\src_l_r_src[3:0]
   end
-  attribute \src "libresoc.v:197974.13-197974.31"
-  process $proc$libresoc.v:197974$14572
+  attribute \src "libresoc.v:197982.13-197982.31"
+  process $proc$libresoc.v:197982$14572
     assign { } { }
     assign $1\src_l_s_src[3:0] 4'0000
     sync always
     sync init
       update \src_l_s_src $1\src_l_s_src[3:0]
   end
-  attribute \src "libresoc.v:197978.14-197978.43"
-  process $proc$libresoc.v:197978$14573
+  attribute \src "libresoc.v:197986.14-197986.43"
+  process $proc$libresoc.v:197986$14573
     assign { } { }
     assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \src_r0 $1\src_r0[63:0]
   end
-  attribute \src "libresoc.v:197982.14-197982.43"
-  process $proc$libresoc.v:197982$14574
+  attribute \src "libresoc.v:197990.14-197990.43"
+  process $proc$libresoc.v:197990$14574
     assign { } { }
     assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \src_r1 $1\src_r1[63:0]
   end
-  attribute \src "libresoc.v:197986.14-197986.43"
-  process $proc$libresoc.v:197986$14575
+  attribute \src "libresoc.v:197994.14-197994.43"
+  process $proc$libresoc.v:197994$14575
     assign { } { }
     assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \src_r2 $1\src_r2[63:0]
   end
-  attribute \src "libresoc.v:197990.14-197990.43"
-  process $proc$libresoc.v:197990$14576
+  attribute \src "libresoc.v:197998.14-197998.43"
+  process $proc$libresoc.v:197998$14576
     assign { } { }
     assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
     sync always
     sync init
       update \src_r3 $1\src_r3[63:0]
   end
-  attribute \src "libresoc.v:198056.3-198057.39"
-  process $proc$libresoc.v:198056$14384
+  attribute \src "libresoc.v:198064.3-198065.39"
+  process $proc$libresoc.v:198064$14384
     assign { } { }
     assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
     sync posedge \coresync_clk
       update \alu_l_r_alu $0\alu_l_r_alu[0:0]
   end
-  attribute \src "libresoc.v:198058.3-198059.43"
-  process $proc$libresoc.v:198058$14385
+  attribute \src "libresoc.v:198066.3-198067.43"
+  process $proc$libresoc.v:198066$14385
     assign { } { }
     assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
     sync posedge \coresync_clk
       update \alui_l_r_alui $0\alui_l_r_alui[0:0]
   end
-  attribute \src "libresoc.v:198060.3-198061.29"
-  process $proc$libresoc.v:198060$14386
+  attribute \src "libresoc.v:198068.3-198069.29"
+  process $proc$libresoc.v:198068$14386
     assign { } { }
     assign $0\src_r3[63:0] \src_r3$next
     sync posedge \coresync_clk
       update \src_r3 $0\src_r3[63:0]
   end
-  attribute \src "libresoc.v:198062.3-198063.29"
-  process $proc$libresoc.v:198062$14387
+  attribute \src "libresoc.v:198070.3-198071.29"
+  process $proc$libresoc.v:198070$14387
     assign { } { }
     assign $0\src_r2[63:0] \src_r2$next
     sync posedge \coresync_clk
       update \src_r2 $0\src_r2[63:0]
   end
-  attribute \src "libresoc.v:198064.3-198065.29"
-  process $proc$libresoc.v:198064$14388
+  attribute \src "libresoc.v:198072.3-198073.29"
+  process $proc$libresoc.v:198072$14388
     assign { } { }
     assign $0\src_r1[63:0] \src_r1$next
     sync posedge \coresync_clk
       update \src_r1 $0\src_r1[63:0]
   end
-  attribute \src "libresoc.v:198066.3-198067.29"
-  process $proc$libresoc.v:198066$14389
+  attribute \src "libresoc.v:198074.3-198075.29"
+  process $proc$libresoc.v:198074$14389
     assign { } { }
     assign $0\src_r0[63:0] \src_r0$next
     sync posedge \coresync_clk
       update \src_r0 $0\src_r0[63:0]
   end
-  attribute \src "libresoc.v:198068.3-198069.41"
-  process $proc$libresoc.v:198068$14390
+  attribute \src "libresoc.v:198076.3-198077.41"
+  process $proc$libresoc.v:198076$14390
     assign { } { }
     assign $0\data_r4__msr[63:0] \data_r4__msr$next
     sync posedge \coresync_clk
       update \data_r4__msr $0\data_r4__msr[63:0]
   end
-  attribute \src "libresoc.v:198070.3-198071.47"
-  process $proc$libresoc.v:198070$14391
+  attribute \src "libresoc.v:198078.3-198079.47"
+  process $proc$libresoc.v:198078$14391
     assign { } { }
     assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next
     sync posedge \coresync_clk
       update \data_r4__msr_ok $0\data_r4__msr_ok[0:0]
   end
-  attribute \src "libresoc.v:198072.3-198073.41"
-  process $proc$libresoc.v:198072$14392
+  attribute \src "libresoc.v:198080.3-198081.41"
+  process $proc$libresoc.v:198080$14392
     assign { } { }
     assign $0\data_r3__nia[63:0] \data_r3__nia$next
     sync posedge \coresync_clk
       update \data_r3__nia $0\data_r3__nia[63:0]
   end
-  attribute \src "libresoc.v:198074.3-198075.47"
-  process $proc$libresoc.v:198074$14393
+  attribute \src "libresoc.v:198082.3-198083.47"
+  process $proc$libresoc.v:198082$14393
     assign { } { }
     assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next
     sync posedge \coresync_clk
       update \data_r3__nia_ok $0\data_r3__nia_ok[0:0]
   end
-  attribute \src "libresoc.v:198076.3-198077.45"
-  process $proc$libresoc.v:198076$14394
+  attribute \src "libresoc.v:198084.3-198085.45"
+  process $proc$libresoc.v:198084$14394
     assign { } { }
     assign $0\data_r2__fast2[63:0] \data_r2__fast2$next
     sync posedge \coresync_clk
       update \data_r2__fast2 $0\data_r2__fast2[63:0]
   end
-  attribute \src "libresoc.v:198078.3-198079.51"
-  process $proc$libresoc.v:198078$14395
+  attribute \src "libresoc.v:198086.3-198087.51"
+  process $proc$libresoc.v:198086$14395
     assign { } { }
     assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next
     sync posedge \coresync_clk
       update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0]
   end
-  attribute \src "libresoc.v:198080.3-198081.45"
-  process $proc$libresoc.v:198080$14396
+  attribute \src "libresoc.v:198088.3-198089.45"
+  process $proc$libresoc.v:198088$14396
     assign { } { }
     assign $0\data_r1__fast1[63:0] \data_r1__fast1$next
     sync posedge \coresync_clk
       update \data_r1__fast1 $0\data_r1__fast1[63:0]
   end
-  attribute \src "libresoc.v:198082.3-198083.51"
-  process $proc$libresoc.v:198082$14397
+  attribute \src "libresoc.v:198090.3-198091.51"
+  process $proc$libresoc.v:198090$14397
     assign { } { }
     assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next
     sync posedge \coresync_clk
       update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0]
   end
-  attribute \src "libresoc.v:198084.3-198085.37"
-  process $proc$libresoc.v:198084$14398
+  attribute \src "libresoc.v:198092.3-198093.37"
+  process $proc$libresoc.v:198092$14398
     assign { } { }
     assign $0\data_r0__o[63:0] \data_r0__o$next
     sync posedge \coresync_clk
       update \data_r0__o $0\data_r0__o[63:0]
   end
-  attribute \src "libresoc.v:198086.3-198087.43"
-  process $proc$libresoc.v:198086$14399
+  attribute \src "libresoc.v:198094.3-198095.43"
+  process $proc$libresoc.v:198094$14399
     assign { } { }
     assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
     sync posedge \coresync_clk
       update \data_r0__o_ok $0\data_r0__o_ok[0:0]
   end
-  attribute \src "libresoc.v:198088.3-198089.73"
-  process $proc$libresoc.v:198088$14400
+  attribute \src "libresoc.v:198096.3-198097.73"
+  process $proc$libresoc.v:198096$14400
     assign { } { }
     assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next
     sync posedge \coresync_clk
       update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0]
   end
-  attribute \src "libresoc.v:198090.3-198091.69"
-  process $proc$libresoc.v:198090$14401
+  attribute \src "libresoc.v:198098.3-198099.69"
+  process $proc$libresoc.v:198098$14401
     assign { } { }
     assign $0\alu_trap0_trap_op__fn_unit[12:0] \alu_trap0_trap_op__fn_unit$next
     sync posedge \coresync_clk
       update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[12:0]
   end
-  attribute \src "libresoc.v:198092.3-198093.63"
-  process $proc$libresoc.v:198092$14402
+  attribute \src "libresoc.v:198100.3-198101.63"
+  process $proc$libresoc.v:198100$14402
     assign { } { }
     assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next
     sync posedge \coresync_clk
       update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0]
   end
-  attribute \src "libresoc.v:198094.3-198095.61"
-  process $proc$libresoc.v:198094$14403
+  attribute \src "libresoc.v:198102.3-198103.61"
+  process $proc$libresoc.v:198102$14403
     assign { } { }
     assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next
     sync posedge \coresync_clk
       update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0]
   end
-  attribute \src "libresoc.v:198096.3-198097.61"
-  process $proc$libresoc.v:198096$14404
+  attribute \src "libresoc.v:198104.3-198105.61"
+  process $proc$libresoc.v:198104$14404
     assign { } { }
     assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next
     sync posedge \coresync_clk
       update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0]
   end
-  attribute \src "libresoc.v:198098.3-198099.71"
-  process $proc$libresoc.v:198098$14405
+  attribute \src "libresoc.v:198106.3-198107.71"
+  process $proc$libresoc.v:198106$14405
     assign { } { }
     assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next
     sync posedge \coresync_clk
       update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0]
   end
-  attribute \src "libresoc.v:198100.3-198101.71"
-  process $proc$libresoc.v:198100$14406
+  attribute \src "libresoc.v:198108.3-198109.71"
+  process $proc$libresoc.v:198108$14406
     assign { } { }
     assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next
     sync posedge \coresync_clk
       update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0]
   end
-  attribute \src "libresoc.v:198102.3-198103.71"
-  process $proc$libresoc.v:198102$14407
+  attribute \src "libresoc.v:198110.3-198111.71"
+  process $proc$libresoc.v:198110$14407
     assign { } { }
     assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next
     sync posedge \coresync_clk
       update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0]
   end
-  attribute \src "libresoc.v:198104.3-198105.71"
-  process $proc$libresoc.v:198104$14408
+  attribute \src "libresoc.v:198112.3-198113.71"
+  process $proc$libresoc.v:198112$14408
     assign { } { }
     assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next
     sync posedge \coresync_clk
       update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0]
   end
-  attribute \src "libresoc.v:198106.3-198107.39"
-  process $proc$libresoc.v:198106$14409
+  attribute \src "libresoc.v:198114.3-198115.39"
+  process $proc$libresoc.v:198114$14409
     assign { } { }
     assign $0\req_l_r_req[4:0] \req_l_r_req$next
     sync posedge \coresync_clk
       update \req_l_r_req $0\req_l_r_req[4:0]
   end
-  attribute \src "libresoc.v:198108.3-198109.39"
-  process $proc$libresoc.v:198108$14410
+  attribute \src "libresoc.v:198116.3-198117.39"
+  process $proc$libresoc.v:198116$14410
     assign { } { }
     assign $0\req_l_s_req[4:0] \req_l_s_req$next
     sync posedge \coresync_clk
       update \req_l_s_req $0\req_l_s_req[4:0]
   end
-  attribute \src "libresoc.v:198110.3-198111.39"
-  process $proc$libresoc.v:198110$14411
+  attribute \src "libresoc.v:198118.3-198119.39"
+  process $proc$libresoc.v:198118$14411
     assign { } { }
     assign $0\src_l_r_src[3:0] \src_l_r_src$next
     sync posedge \coresync_clk
       update \src_l_r_src $0\src_l_r_src[3:0]
   end
-  attribute \src "libresoc.v:198112.3-198113.39"
-  process $proc$libresoc.v:198112$14412
+  attribute \src "libresoc.v:198120.3-198121.39"
+  process $proc$libresoc.v:198120$14412
     assign { } { }
     assign $0\src_l_s_src[3:0] \src_l_s_src$next
     sync posedge \coresync_clk
       update \src_l_s_src $0\src_l_s_src[3:0]
   end
-  attribute \src "libresoc.v:198114.3-198115.39"
-  process $proc$libresoc.v:198114$14413
+  attribute \src "libresoc.v:198122.3-198123.39"
+  process $proc$libresoc.v:198122$14413
     assign { } { }
     assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
     sync posedge \coresync_clk
       update \opc_l_r_opc $0\opc_l_r_opc[0:0]
   end
-  attribute \src "libresoc.v:198116.3-198117.39"
-  process $proc$libresoc.v:198116$14414
+  attribute \src "libresoc.v:198124.3-198125.39"
+  process $proc$libresoc.v:198124$14414
     assign { } { }
     assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
     sync posedge \coresync_clk
       update \opc_l_s_opc $0\opc_l_s_opc[0:0]
   end
-  attribute \src "libresoc.v:198118.3-198119.39"
-  process $proc$libresoc.v:198118$14415
+  attribute \src "libresoc.v:198126.3-198127.39"
+  process $proc$libresoc.v:198126$14415
     assign { } { }
     assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
     sync posedge \coresync_clk
       update \rst_l_r_rst $0\rst_l_r_rst[0:0]
   end
-  attribute \src "libresoc.v:198120.3-198121.39"
-  process $proc$libresoc.v:198120$14416
+  attribute \src "libresoc.v:198128.3-198129.39"
+  process $proc$libresoc.v:198128$14416
     assign { } { }
     assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
     sync posedge \coresync_clk
       update \rst_l_s_rst $0\rst_l_s_rst[0:0]
   end
-  attribute \src "libresoc.v:198122.3-198123.41"
-  process $proc$libresoc.v:198122$14417
+  attribute \src "libresoc.v:198130.3-198131.41"
+  process $proc$libresoc.v:198130$14417
     assign { } { }
     assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
     sync posedge \coresync_clk
       update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
   end
-  attribute \src "libresoc.v:198124.3-198125.41"
-  process $proc$libresoc.v:198124$14418
+  attribute \src "libresoc.v:198132.3-198133.41"
+  process $proc$libresoc.v:198132$14418
     assign { } { }
     assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
     sync posedge \coresync_clk
       update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
   end
-  attribute \src "libresoc.v:198126.3-198127.37"
-  process $proc$libresoc.v:198126$14419
+  attribute \src "libresoc.v:198134.3-198135.37"
+  process $proc$libresoc.v:198134$14419
     assign { } { }
     assign $0\prev_wr_go[4:0] \prev_wr_go$next
     sync posedge \coresync_clk
       update \prev_wr_go $0\prev_wr_go[4:0]
   end
-  attribute \src "libresoc.v:198128.3-198129.41"
-  process $proc$libresoc.v:198128$14420
+  attribute \src "libresoc.v:198136.3-198137.41"
+  process $proc$libresoc.v:198136$14420
     assign { } { }
     assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o
     sync posedge \coresync_clk
       update \alu_done_dly $0\alu_done_dly[0:0]
   end
-  attribute \src "libresoc.v:198130.3-198131.25"
-  process $proc$libresoc.v:198130$14421
+  attribute \src "libresoc.v:198138.3-198139.25"
+  process $proc$libresoc.v:198138$14421
     assign { } { }
     assign $0\all_rd_dly[0:0] \$11
     sync posedge \coresync_clk
       update \all_rd_dly $0\all_rd_dly[0:0]
   end
-  attribute \src "libresoc.v:198211.3-198220.6"
-  process $proc$libresoc.v:198211$14422
+  attribute \src "libresoc.v:198219.3-198228.6"
+  process $proc$libresoc.v:198219$14422
     assign { } { }
     assign { } { }
     assign $0\req_done[0:0] $1\req_done[0:0]
-    attribute \src "libresoc.v:198212.5-198212.29"
+    attribute \src "libresoc.v:198220.5-198220.29"
     switch \initial
-      attribute \src "libresoc.v:198212.9-198212.17"
+      attribute \src "libresoc.v:198220.9-198220.17"
       case 1'1
       case 
     end
@@ -415544,14 +415552,14 @@ module \trap0
     sync always
       update \req_done $0\req_done[0:0]
   end
-  attribute \src "libresoc.v:198221.3-198229.6"
-  process $proc$libresoc.v:198221$14423
+  attribute \src "libresoc.v:198229.3-198237.6"
+  process $proc$libresoc.v:198229$14423
     assign { } { }
     assign { } { }
     assign $0\rok_l_s_rdok$next[0:0]$14424 $1\rok_l_s_rdok$next[0:0]$14425
-    attribute \src "libresoc.v:198222.5-198222.29"
+    attribute \src "libresoc.v:198230.5-198230.29"
     switch \initial
-      attribute \src "libresoc.v:198222.9-198222.17"
+      attribute \src "libresoc.v:198230.9-198230.17"
       case 1'1
       case 
     end
@@ -415567,14 +415575,14 @@ module \trap0
     sync always
       update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14424
   end
-  attribute \src "libresoc.v:198230.3-198238.6"
-  process $proc$libresoc.v:198230$14426
+  attribute \src "libresoc.v:198238.3-198246.6"
+  process $proc$libresoc.v:198238$14426
     assign { } { }
     assign { } { }
     assign $0\rok_l_r_rdok$next[0:0]$14427 $1\rok_l_r_rdok$next[0:0]$14428
-    attribute \src "libresoc.v:198231.5-198231.29"
+    attribute \src "libresoc.v:198239.5-198239.29"
     switch \initial
-      attribute \src "libresoc.v:198231.9-198231.17"
+      attribute \src "libresoc.v:198239.9-198239.17"
       case 1'1
       case 
     end
@@ -415590,14 +415598,14 @@ module \trap0
     sync always
       update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14427
   end
-  attribute \src "libresoc.v:198239.3-198247.6"
-  process $proc$libresoc.v:198239$14429
+  attribute \src "libresoc.v:198247.3-198255.6"
+  process $proc$libresoc.v:198247$14429
     assign { } { }
     assign { } { }
     assign $0\rst_l_s_rst$next[0:0]$14430 $1\rst_l_s_rst$next[0:0]$14431
-    attribute \src "libresoc.v:198240.5-198240.29"
+    attribute \src "libresoc.v:198248.5-198248.29"
     switch \initial
-      attribute \src "libresoc.v:198240.9-198240.17"
+      attribute \src "libresoc.v:198248.9-198248.17"
       case 1'1
       case 
     end
@@ -415613,14 +415621,14 @@ module \trap0
     sync always
       update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14430
   end
-  attribute \src "libresoc.v:198248.3-198256.6"
-  process $proc$libresoc.v:198248$14432
+  attribute \src "libresoc.v:198256.3-198264.6"
+  process $proc$libresoc.v:198256$14432
     assign { } { }
     assign { } { }
     assign $0\rst_l_r_rst$next[0:0]$14433 $1\rst_l_r_rst$next[0:0]$14434
-    attribute \src "libresoc.v:198249.5-198249.29"
+    attribute \src "libresoc.v:198257.5-198257.29"
     switch \initial
-      attribute \src "libresoc.v:198249.9-198249.17"
+      attribute \src "libresoc.v:198257.9-198257.17"
       case 1'1
       case 
     end
@@ -415636,14 +415644,14 @@ module \trap0
     sync always
       update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14433
   end
-  attribute \src "libresoc.v:198257.3-198265.6"
-  process $proc$libresoc.v:198257$14435
+  attribute \src "libresoc.v:198265.3-198273.6"
+  process $proc$libresoc.v:198265$14435
     assign { } { }
     assign { } { }
     assign $0\opc_l_s_opc$next[0:0]$14436 $1\opc_l_s_opc$next[0:0]$14437
-    attribute \src "libresoc.v:198258.5-198258.29"
+    attribute \src "libresoc.v:198266.5-198266.29"
     switch \initial
-      attribute \src "libresoc.v:198258.9-198258.17"
+      attribute \src "libresoc.v:198266.9-198266.17"
       case 1'1
       case 
     end
@@ -415659,14 +415667,14 @@ module \trap0
     sync always
       update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14436
   end
-  attribute \src "libresoc.v:198266.3-198274.6"
-  process $proc$libresoc.v:198266$14438
+  attribute \src "libresoc.v:198274.3-198282.6"
+  process $proc$libresoc.v:198274$14438
     assign { } { }
     assign { } { }
     assign $0\opc_l_r_opc$next[0:0]$14439 $1\opc_l_r_opc$next[0:0]$14440
-    attribute \src "libresoc.v:198267.5-198267.29"
+    attribute \src "libresoc.v:198275.5-198275.29"
     switch \initial
-      attribute \src "libresoc.v:198267.9-198267.17"
+      attribute \src "libresoc.v:198275.9-198275.17"
       case 1'1
       case 
     end
@@ -415682,14 +415690,14 @@ module \trap0
     sync always
       update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14439
   end
-  attribute \src "libresoc.v:198275.3-198283.6"
-  process $proc$libresoc.v:198275$14441
+  attribute \src "libresoc.v:198283.3-198291.6"
+  process $proc$libresoc.v:198283$14441
     assign { } { }
     assign { } { }
     assign $0\src_l_s_src$next[3:0]$14442 $1\src_l_s_src$next[3:0]$14443
-    attribute \src "libresoc.v:198276.5-198276.29"
+    attribute \src "libresoc.v:198284.5-198284.29"
     switch \initial
-      attribute \src "libresoc.v:198276.9-198276.17"
+      attribute \src "libresoc.v:198284.9-198284.17"
       case 1'1
       case 
     end
@@ -415705,14 +415713,14 @@ module \trap0
     sync always
       update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14442
   end
-  attribute \src "libresoc.v:198284.3-198292.6"
-  process $proc$libresoc.v:198284$14444
+  attribute \src "libresoc.v:198292.3-198300.6"
+  process $proc$libresoc.v:198292$14444
     assign { } { }
     assign { } { }
     assign $0\src_l_r_src$next[3:0]$14445 $1\src_l_r_src$next[3:0]$14446
-    attribute \src "libresoc.v:198285.5-198285.29"
+    attribute \src "libresoc.v:198293.5-198293.29"
     switch \initial
-      attribute \src "libresoc.v:198285.9-198285.17"
+      attribute \src "libresoc.v:198293.9-198293.17"
       case 1'1
       case 
     end
@@ -415728,14 +415736,14 @@ module \trap0
     sync always
       update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14445
   end
-  attribute \src "libresoc.v:198293.3-198301.6"
-  process $proc$libresoc.v:198293$14447
+  attribute \src "libresoc.v:198301.3-198309.6"
+  process $proc$libresoc.v:198301$14447
     assign { } { }
     assign { } { }
     assign $0\req_l_s_req$next[4:0]$14448 $1\req_l_s_req$next[4:0]$14449
-    attribute \src "libresoc.v:198294.5-198294.29"
+    attribute \src "libresoc.v:198302.5-198302.29"
     switch \initial
-      attribute \src "libresoc.v:198294.9-198294.17"
+      attribute \src "libresoc.v:198302.9-198302.17"
       case 1'1
       case 
     end
@@ -415751,14 +415759,14 @@ module \trap0
     sync always
       update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14448
   end
-  attribute \src "libresoc.v:198302.3-198310.6"
-  process $proc$libresoc.v:198302$14450
+  attribute \src "libresoc.v:198310.3-198318.6"
+  process $proc$libresoc.v:198310$14450
     assign { } { }
     assign { } { }
     assign $0\req_l_r_req$next[4:0]$14451 $1\req_l_r_req$next[4:0]$14452
-    attribute \src "libresoc.v:198303.5-198303.29"
+    attribute \src "libresoc.v:198311.5-198311.29"
     switch \initial
-      attribute \src "libresoc.v:198303.9-198303.17"
+      attribute \src "libresoc.v:198311.9-198311.17"
       case 1'1
       case 
     end
@@ -415774,8 +415782,8 @@ module \trap0
     sync always
       update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14451
   end
-  attribute \src "libresoc.v:198311.3-198328.6"
-  process $proc$libresoc.v:198311$14453
+  attribute \src "libresoc.v:198319.3-198336.6"
+  process $proc$libresoc.v:198319$14453
     assign { } { }
     assign { } { }
     assign { } { }
@@ -415803,9 +415811,9 @@ module \trap0
     assign $0\alu_trap0_trap_op__msr$next[63:0]$14460 $1\alu_trap0_trap_op__msr$next[63:0]$14469
     assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14461 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14470
     assign $0\alu_trap0_trap_op__traptype$next[7:0]$14462 $1\alu_trap0_trap_op__traptype$next[7:0]$14471
-    attribute \src "libresoc.v:198312.5-198312.29"
+    attribute \src "libresoc.v:198320.5-198320.29"
     switch \initial
-      attribute \src "libresoc.v:198312.9-198312.17"
+      attribute \src "libresoc.v:198320.9-198320.17"
       case 1'1
       case 
     end
@@ -415845,8 +415853,8 @@ module \trap0
       update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14461
       update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14462
   end
-  attribute \src "libresoc.v:198329.3-198350.6"
-  process $proc$libresoc.v:198329$14472
+  attribute \src "libresoc.v:198337.3-198358.6"
+  process $proc$libresoc.v:198337$14472
     assign { } { }
     assign { } { }
     assign { } { }
@@ -415856,9 +415864,9 @@ module \trap0
     assign $0\data_r0__o$next[63:0]$14473 $2\data_r0__o$next[63:0]$14477
     assign { } { }
     assign $0\data_r0__o_ok$next[0:0]$14474 $3\data_r0__o_ok$next[0:0]$14479
-    attribute \src "libresoc.v:198330.5-198330.29"
+    attribute \src "libresoc.v:198338.5-198338.29"
     switch \initial
-      attribute \src "libresoc.v:198330.9-198330.17"
+      attribute \src "libresoc.v:198338.9-198338.17"
       case 1'1
       case 
     end
@@ -415897,8 +415905,8 @@ module \trap0
       update \data_r0__o$next $0\data_r0__o$next[63:0]$14473
       update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14474
   end
-  attribute \src "libresoc.v:198351.3-198372.6"
-  process $proc$libresoc.v:198351$14480
+  attribute \src "libresoc.v:198359.3-198380.6"
+  process $proc$libresoc.v:198359$14480
     assign { } { }
     assign { } { }
     assign { } { }
@@ -415908,9 +415916,9 @@ module \trap0
     assign $0\data_r1__fast1$next[63:0]$14481 $2\data_r1__fast1$next[63:0]$14485
     assign { } { }
     assign $0\data_r1__fast1_ok$next[0:0]$14482 $3\data_r1__fast1_ok$next[0:0]$14487
-    attribute \src "libresoc.v:198352.5-198352.29"
+    attribute \src "libresoc.v:198360.5-198360.29"
     switch \initial
-      attribute \src "libresoc.v:198352.9-198352.17"
+      attribute \src "libresoc.v:198360.9-198360.17"
       case 1'1
       case 
     end
@@ -415949,8 +415957,8 @@ module \trap0
       update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14481
       update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14482
   end
-  attribute \src "libresoc.v:198373.3-198394.6"
-  process $proc$libresoc.v:198373$14488
+  attribute \src "libresoc.v:198381.3-198402.6"
+  process $proc$libresoc.v:198381$14488
     assign { } { }
     assign { } { }
     assign { } { }
@@ -415960,9 +415968,9 @@ module \trap0
     assign $0\data_r2__fast2$next[63:0]$14489 $2\data_r2__fast2$next[63:0]$14493
     assign { } { }
     assign $0\data_r2__fast2_ok$next[0:0]$14490 $3\data_r2__fast2_ok$next[0:0]$14495
-    attribute \src "libresoc.v:198374.5-198374.29"
+    attribute \src "libresoc.v:198382.5-198382.29"
     switch \initial
-      attribute \src "libresoc.v:198374.9-198374.17"
+      attribute \src "libresoc.v:198382.9-198382.17"
       case 1'1
       case 
     end
@@ -416001,8 +416009,8 @@ module \trap0
       update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14489
       update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14490
   end
-  attribute \src "libresoc.v:198395.3-198416.6"
-  process $proc$libresoc.v:198395$14496
+  attribute \src "libresoc.v:198403.3-198424.6"
+  process $proc$libresoc.v:198403$14496
     assign { } { }
     assign { } { }
     assign { } { }
@@ -416012,9 +416020,9 @@ module \trap0
     assign $0\data_r3__nia$next[63:0]$14497 $2\data_r3__nia$next[63:0]$14501
     assign { } { }
     assign $0\data_r3__nia_ok$next[0:0]$14498 $3\data_r3__nia_ok$next[0:0]$14503
-    attribute \src "libresoc.v:198396.5-198396.29"
+    attribute \src "libresoc.v:198404.5-198404.29"
     switch \initial
-      attribute \src "libresoc.v:198396.9-198396.17"
+      attribute \src "libresoc.v:198404.9-198404.17"
       case 1'1
       case 
     end
@@ -416053,8 +416061,8 @@ module \trap0
       update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14497
       update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14498
   end
-  attribute \src "libresoc.v:198417.3-198438.6"
-  process $proc$libresoc.v:198417$14504
+  attribute \src "libresoc.v:198425.3-198446.6"
+  process $proc$libresoc.v:198425$14504
     assign { } { }
     assign { } { }
     assign { } { }
@@ -416064,9 +416072,9 @@ module \trap0
     assign $0\data_r4__msr$next[63:0]$14505 $2\data_r4__msr$next[63:0]$14509
     assign { } { }
     assign $0\data_r4__msr_ok$next[0:0]$14506 $3\data_r4__msr_ok$next[0:0]$14511
-    attribute \src "libresoc.v:198418.5-198418.29"
+    attribute \src "libresoc.v:198426.5-198426.29"
     switch \initial
-      attribute \src "libresoc.v:198418.9-198418.17"
+      attribute \src "libresoc.v:198426.9-198426.17"
       case 1'1
       case 
     end
@@ -416105,14 +416113,14 @@ module \trap0
       update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14505
       update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14506
   end
-  attribute \src "libresoc.v:198439.3-198448.6"
-  process $proc$libresoc.v:198439$14512
+  attribute \src "libresoc.v:198447.3-198456.6"
+  process $proc$libresoc.v:198447$14512
     assign { } { }
     assign { } { }
     assign $0\src_r0$next[63:0]$14513 $1\src_r0$next[63:0]$14514
-    attribute \src "libresoc.v:198440.5-198440.29"
+    attribute \src "libresoc.v:198448.5-198448.29"
     switch \initial
-      attribute \src "libresoc.v:198440.9-198440.17"
+      attribute \src "libresoc.v:198448.9-198448.17"
       case 1'1
       case 
     end
@@ -416128,14 +416136,14 @@ module \trap0
     sync always
       update \src_r0$next $0\src_r0$next[63:0]$14513
   end
-  attribute \src "libresoc.v:198449.3-198458.6"
-  process $proc$libresoc.v:198449$14515
+  attribute \src "libresoc.v:198457.3-198466.6"
+  process $proc$libresoc.v:198457$14515
     assign { } { }
     assign { } { }
     assign $0\src_r1$next[63:0]$14516 $1\src_r1$next[63:0]$14517
-    attribute \src "libresoc.v:198450.5-198450.29"
+    attribute \src "libresoc.v:198458.5-198458.29"
     switch \initial
-      attribute \src "libresoc.v:198450.9-198450.17"
+      attribute \src "libresoc.v:198458.9-198458.17"
       case 1'1
       case 
     end
@@ -416151,14 +416159,14 @@ module \trap0
     sync always
       update \src_r1$next $0\src_r1$next[63:0]$14516
   end
-  attribute \src "libresoc.v:198459.3-198468.6"
-  process $proc$libresoc.v:198459$14518
+  attribute \src "libresoc.v:198467.3-198476.6"
+  process $proc$libresoc.v:198467$14518
     assign { } { }
     assign { } { }
     assign $0\src_r2$next[63:0]$14519 $1\src_r2$next[63:0]$14520
-    attribute \src "libresoc.v:198460.5-198460.29"
+    attribute \src "libresoc.v:198468.5-198468.29"
     switch \initial
-      attribute \src "libresoc.v:198460.9-198460.17"
+      attribute \src "libresoc.v:198468.9-198468.17"
       case 1'1
       case 
     end
@@ -416174,14 +416182,14 @@ module \trap0
     sync always
       update \src_r2$next $0\src_r2$next[63:0]$14519
   end
-  attribute \src "libresoc.v:198469.3-198478.6"
-  process $proc$libresoc.v:198469$14521
+  attribute \src "libresoc.v:198477.3-198486.6"
+  process $proc$libresoc.v:198477$14521
     assign { } { }
     assign { } { }
     assign $0\src_r3$next[63:0]$14522 $1\src_r3$next[63:0]$14523
-    attribute \src "libresoc.v:198470.5-198470.29"
+    attribute \src "libresoc.v:198478.5-198478.29"
     switch \initial
-      attribute \src "libresoc.v:198470.9-198470.17"
+      attribute \src "libresoc.v:198478.9-198478.17"
       case 1'1
       case 
     end
@@ -416197,14 +416205,14 @@ module \trap0
     sync always
       update \src_r3$next $0\src_r3$next[63:0]$14522
   end
-  attribute \src "libresoc.v:198479.3-198487.6"
-  process $proc$libresoc.v:198479$14524
+  attribute \src "libresoc.v:198487.3-198495.6"
+  process $proc$libresoc.v:198487$14524
     assign { } { }
     assign { } { }
     assign $0\alui_l_r_alui$next[0:0]$14525 $1\alui_l_r_alui$next[0:0]$14526
-    attribute \src "libresoc.v:198480.5-198480.29"
+    attribute \src "libresoc.v:198488.5-198488.29"
     switch \initial
-      attribute \src "libresoc.v:198480.9-198480.17"
+      attribute \src "libresoc.v:198488.9-198488.17"
       case 1'1
       case 
     end
@@ -416220,14 +416228,14 @@ module \trap0
     sync always
       update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14525
   end
-  attribute \src "libresoc.v:198488.3-198496.6"
-  process $proc$libresoc.v:198488$14527
+  attribute \src "libresoc.v:198496.3-198504.6"
+  process $proc$libresoc.v:198496$14527
     assign { } { }
     assign { } { }
     assign $0\alu_l_r_alu$next[0:0]$14528 $1\alu_l_r_alu$next[0:0]$14529
-    attribute \src "libresoc.v:198489.5-198489.29"
+    attribute \src "libresoc.v:198497.5-198497.29"
     switch \initial
-      attribute \src "libresoc.v:198489.9-198489.17"
+      attribute \src "libresoc.v:198497.9-198497.17"
       case 1'1
       case 
     end
@@ -416243,14 +416251,14 @@ module \trap0
     sync always
       update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14528
   end
-  attribute \src "libresoc.v:198497.3-198506.6"
-  process $proc$libresoc.v:198497$14530
+  attribute \src "libresoc.v:198505.3-198514.6"
+  process $proc$libresoc.v:198505$14530
     assign { } { }
     assign { } { }
     assign $0\dest1_o[63:0] $1\dest1_o[63:0]
-    attribute \src "libresoc.v:198498.5-198498.29"
+    attribute \src "libresoc.v:198506.5-198506.29"
     switch \initial
-      attribute \src "libresoc.v:198498.9-198498.17"
+      attribute \src "libresoc.v:198506.9-198506.17"
       case 1'1
       case 
     end
@@ -416266,14 +416274,14 @@ module \trap0
     sync always
       update \dest1_o $0\dest1_o[63:0]
   end
-  attribute \src "libresoc.v:198507.3-198516.6"
-  process $proc$libresoc.v:198507$14531
+  attribute \src "libresoc.v:198515.3-198524.6"
+  process $proc$libresoc.v:198515$14531
     assign { } { }
     assign { } { }
     assign $0\dest2_o[63:0] $1\dest2_o[63:0]
-    attribute \src "libresoc.v:198508.5-198508.29"
+    attribute \src "libresoc.v:198516.5-198516.29"
     switch \initial
-      attribute \src "libresoc.v:198508.9-198508.17"
+      attribute \src "libresoc.v:198516.9-198516.17"
       case 1'1
       case 
     end
@@ -416289,14 +416297,14 @@ module \trap0
     sync always
       update \dest2_o $0\dest2_o[63:0]
   end
-  attribute \src "libresoc.v:198517.3-198526.6"
-  process $proc$libresoc.v:198517$14532
+  attribute \src "libresoc.v:198525.3-198534.6"
+  process $proc$libresoc.v:198525$14532
     assign { } { }
     assign { } { }
     assign $0\dest3_o[63:0] $1\dest3_o[63:0]
-    attribute \src "libresoc.v:198518.5-198518.29"
+    attribute \src "libresoc.v:198526.5-198526.29"
     switch \initial
-      attribute \src "libresoc.v:198518.9-198518.17"
+      attribute \src "libresoc.v:198526.9-198526.17"
       case 1'1
       case 
     end
@@ -416312,14 +416320,14 @@ module \trap0
     sync always
       update \dest3_o $0\dest3_o[63:0]
   end
-  attribute \src "libresoc.v:198527.3-198536.6"
-  process $proc$libresoc.v:198527$14533
+  attribute \src "libresoc.v:198535.3-198544.6"
+  process $proc$libresoc.v:198535$14533
     assign { } { }
     assign { } { }
     assign $0\dest4_o[63:0] $1\dest4_o[63:0]
-    attribute \src "libresoc.v:198528.5-198528.29"
+    attribute \src "libresoc.v:198536.5-198536.29"
     switch \initial
-      attribute \src "libresoc.v:198528.9-198528.17"
+      attribute \src "libresoc.v:198536.9-198536.17"
       case 1'1
       case 
     end
@@ -416335,14 +416343,14 @@ module \trap0
     sync always
       update \dest4_o $0\dest4_o[63:0]
   end
-  attribute \src "libresoc.v:198537.3-198546.6"
-  process $proc$libresoc.v:198537$14534
+  attribute \src "libresoc.v:198545.3-198554.6"
+  process $proc$libresoc.v:198545$14534
     assign { } { }
     assign { } { }
     assign $0\dest5_o[63:0] $1\dest5_o[63:0]
-    attribute \src "libresoc.v:198538.5-198538.29"
+    attribute \src "libresoc.v:198546.5-198546.29"
     switch \initial
-      attribute \src "libresoc.v:198538.9-198538.17"
+      attribute \src "libresoc.v:198546.9-198546.17"
       case 1'1
       case 
     end
@@ -416358,14 +416366,14 @@ module \trap0
     sync always
       update \dest5_o $0\dest5_o[63:0]
   end
-  attribute \src "libresoc.v:198547.3-198555.6"
-  process $proc$libresoc.v:198547$14535
+  attribute \src "libresoc.v:198555.3-198563.6"
+  process $proc$libresoc.v:198555$14535
     assign { } { }
     assign { } { }
     assign $0\prev_wr_go$next[4:0]$14536 $1\prev_wr_go$next[4:0]$14537
-    attribute \src "libresoc.v:198548.5-198548.29"
+    attribute \src "libresoc.v:198556.5-198556.29"
     switch \initial
-      attribute \src "libresoc.v:198548.9-198548.17"
+      attribute \src "libresoc.v:198556.9-198556.17"
       case 1'1
       case 
     end
@@ -416381,67 +416389,67 @@ module \trap0
     sync always
       update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14536
   end
-  connect \$5 $reduce_and$libresoc.v:197995$14323_Y
-  connect \$99 $and$libresoc.v:197996$14324_Y
-  connect \$101 $and$libresoc.v:197997$14325_Y
-  connect \$103 $and$libresoc.v:197998$14326_Y
-  connect \$105 $and$libresoc.v:197999$14327_Y
-  connect \$107 $and$libresoc.v:198000$14328_Y
-  connect \$109 $and$libresoc.v:198001$14329_Y
-  connect \$111 $and$libresoc.v:198002$14330_Y
-  connect \$113 $and$libresoc.v:198003$14331_Y
-  connect \$115 $and$libresoc.v:198004$14332_Y
-  connect \$117 $and$libresoc.v:198005$14333_Y
-  connect \$11 $and$libresoc.v:198006$14334_Y
-  connect \$119 $and$libresoc.v:198007$14335_Y
-  connect \$121 $and$libresoc.v:198008$14336_Y
-  connect \$123 $and$libresoc.v:198009$14337_Y
-  connect \$13 $not$libresoc.v:198010$14338_Y
-  connect \$15 $and$libresoc.v:198011$14339_Y
-  connect \$17 $not$libresoc.v:198012$14340_Y
-  connect \$19 $and$libresoc.v:198013$14341_Y
-  connect \$21 $and$libresoc.v:198014$14342_Y
-  connect \$25 $not$libresoc.v:198015$14343_Y
-  connect \$27 $and$libresoc.v:198016$14344_Y
-  connect \$24 $reduce_or$libresoc.v:198017$14345_Y
-  connect \$23 $not$libresoc.v:198018$14346_Y
-  connect \$31 $and$libresoc.v:198019$14347_Y
-  connect \$33 $reduce_or$libresoc.v:198020$14348_Y
-  connect \$35 $reduce_or$libresoc.v:198021$14349_Y
-  connect \$37 $or$libresoc.v:198022$14350_Y
-  connect \$3 $and$libresoc.v:198023$14351_Y
-  connect \$39 $not$libresoc.v:198024$14352_Y
-  connect \$41 $and$libresoc.v:198025$14353_Y
-  connect \$43 $and$libresoc.v:198026$14354_Y
-  connect \$45 $eq$libresoc.v:198027$14355_Y
-  connect \$47 $and$libresoc.v:198028$14356_Y
-  connect \$49 $eq$libresoc.v:198029$14357_Y
-  connect \$51 $and$libresoc.v:198030$14358_Y
-  connect \$53 $and$libresoc.v:198031$14359_Y
-  connect \$55 $and$libresoc.v:198032$14360_Y
-  connect \$57 $or$libresoc.v:198033$14361_Y
-  connect \$59 $or$libresoc.v:198034$14362_Y
-  connect \$61 $or$libresoc.v:198035$14363_Y
-  connect \$63 $or$libresoc.v:198036$14364_Y
-  connect \$65 $and$libresoc.v:198037$14365_Y
-  connect \$67 $and$libresoc.v:198038$14366_Y
-  connect \$6 $not$libresoc.v:198039$14367_Y
-  connect \$69 $or$libresoc.v:198040$14368_Y
-  connect \$71 $and$libresoc.v:198041$14369_Y
-  connect \$73 $and$libresoc.v:198042$14370_Y
-  connect \$75 $and$libresoc.v:198043$14371_Y
-  connect \$77 $and$libresoc.v:198044$14372_Y
-  connect \$79 $and$libresoc.v:198045$14373_Y
-  connect \$81 $ternary$libresoc.v:198046$14374_Y
-  connect \$83 $ternary$libresoc.v:198047$14375_Y
-  connect \$85 $ternary$libresoc.v:198048$14376_Y
-  connect \$87 $ternary$libresoc.v:198049$14377_Y
-  connect \$8 $or$libresoc.v:198050$14378_Y
-  connect \$89 $and$libresoc.v:198051$14379_Y
-  connect \$91 $and$libresoc.v:198052$14380_Y
-  connect \$93 $and$libresoc.v:198053$14381_Y
-  connect \$95 $and$libresoc.v:198054$14382_Y
-  connect \$97 $not$libresoc.v:198055$14383_Y
+  connect \$5 $reduce_and$libresoc.v:198003$14323_Y
+  connect \$99 $and$libresoc.v:198004$14324_Y
+  connect \$101 $and$libresoc.v:198005$14325_Y
+  connect \$103 $and$libresoc.v:198006$14326_Y
+  connect \$105 $and$libresoc.v:198007$14327_Y
+  connect \$107 $and$libresoc.v:198008$14328_Y
+  connect \$109 $and$libresoc.v:198009$14329_Y
+  connect \$111 $and$libresoc.v:198010$14330_Y
+  connect \$113 $and$libresoc.v:198011$14331_Y
+  connect \$115 $and$libresoc.v:198012$14332_Y
+  connect \$117 $and$libresoc.v:198013$14333_Y
+  connect \$11 $and$libresoc.v:198014$14334_Y
+  connect \$119 $and$libresoc.v:198015$14335_Y
+  connect \$121 $and$libresoc.v:198016$14336_Y
+  connect \$123 $and$libresoc.v:198017$14337_Y
+  connect \$13 $not$libresoc.v:198018$14338_Y
+  connect \$15 $and$libresoc.v:198019$14339_Y
+  connect \$17 $not$libresoc.v:198020$14340_Y
+  connect \$19 $and$libresoc.v:198021$14341_Y
+  connect \$21 $and$libresoc.v:198022$14342_Y
+  connect \$25 $not$libresoc.v:198023$14343_Y
+  connect \$27 $and$libresoc.v:198024$14344_Y
+  connect \$24 $reduce_or$libresoc.v:198025$14345_Y
+  connect \$23 $not$libresoc.v:198026$14346_Y
+  connect \$31 $and$libresoc.v:198027$14347_Y
+  connect \$33 $reduce_or$libresoc.v:198028$14348_Y
+  connect \$35 $reduce_or$libresoc.v:198029$14349_Y
+  connect \$37 $or$libresoc.v:198030$14350_Y
+  connect \$3 $and$libresoc.v:198031$14351_Y
+  connect \$39 $not$libresoc.v:198032$14352_Y
+  connect \$41 $and$libresoc.v:198033$14353_Y
+  connect \$43 $and$libresoc.v:198034$14354_Y
+  connect \$45 $eq$libresoc.v:198035$14355_Y
+  connect \$47 $and$libresoc.v:198036$14356_Y
+  connect \$49 $eq$libresoc.v:198037$14357_Y
+  connect \$51 $and$libresoc.v:198038$14358_Y
+  connect \$53 $and$libresoc.v:198039$14359_Y
+  connect \$55 $and$libresoc.v:198040$14360_Y
+  connect \$57 $or$libresoc.v:198041$14361_Y
+  connect \$59 $or$libresoc.v:198042$14362_Y
+  connect \$61 $or$libresoc.v:198043$14363_Y
+  connect \$63 $or$libresoc.v:198044$14364_Y
+  connect \$65 $and$libresoc.v:198045$14365_Y
+  connect \$67 $and$libresoc.v:198046$14366_Y
+  connect \$6 $not$libresoc.v:198047$14367_Y
+  connect \$69 $or$libresoc.v:198048$14368_Y
+  connect \$71 $and$libresoc.v:198049$14369_Y
+  connect \$73 $and$libresoc.v:198050$14370_Y
+  connect \$75 $and$libresoc.v:198051$14371_Y
+  connect \$77 $and$libresoc.v:198052$14372_Y
+  connect \$79 $and$libresoc.v:198053$14373_Y
+  connect \$81 $ternary$libresoc.v:198054$14374_Y
+  connect \$83 $ternary$libresoc.v:198055$14375_Y
+  connect \$85 $ternary$libresoc.v:198056$14376_Y
+  connect \$87 $ternary$libresoc.v:198057$14377_Y
+  connect \$8 $or$libresoc.v:198058$14378_Y
+  connect \$89 $and$libresoc.v:198059$14379_Y
+  connect \$91 $and$libresoc.v:198060$14380_Y
+  connect \$93 $and$libresoc.v:198061$14381_Y
+  connect \$95 $and$libresoc.v:198062$14382_Y
+  connect \$97 $not$libresoc.v:198063$14383_Y
   connect \cu_go_die_i 1'0
   connect \cu_shadown_i 1'1
   connect \cu_wr__rel_o \$113
@@ -416472,37 +416480,37 @@ module \trap0
   connect \all_rd_dly$next \all_rd
   connect \all_rd \$11
 end
-attribute \src "libresoc.v:198589.1-198647.10"
+attribute \src "libresoc.v:198597.1-198655.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l"
 attribute \generator "nMigen"
 module \upd_l
-  attribute \src "libresoc.v:198590.7-198590.20"
+  attribute \src "libresoc.v:198598.7-198598.20"
   wire $0\initial[0:0]
-  attribute \src "libresoc.v:198635.3-198643.6"
+  attribute \src "libresoc.v:198643.3-198651.6"
   wire $0\q_int$next[0:0]$14587
-  attribute \src "libresoc.v:198633.3-198634.27"
+  attribute \src "libresoc.v:198641.3-198642.27"
   wire $0\q_int[0:0]
-  attribute \src "libresoc.v:198635.3-198643.6"
+  attribute \src "libresoc.v:198643.3-198651.6"
   wire $1\q_int$next[0:0]$14588
-  attribute \src "libresoc.v:198612.7-198612.19"
+  attribute \src "libresoc.v:198620.7-198620.19"
   wire $1\q_int[0:0]
-  attribute \src "libresoc.v:198625.17-198625.96"
-  wire $and$libresoc.v:198625$14577_Y
-  attribute \src "libresoc.v:198630.17-198630.96"
-  wire $and$libresoc.v:198630$14582_Y
-  attribute \src "libresoc.v:198627.18-198627.93"
-  wire $not$libresoc.v:198627$14579_Y
-  attribute \src "libresoc.v:198629.17-198629.92"
-  wire $not$libresoc.v:198629$14581_Y
-  attribute \src "libresoc.v:198632.17-198632.92"
-  wire $not$libresoc.v:198632$14584_Y
-  attribute \src "libresoc.v:198626.18-198626.98"
-  wire $or$libresoc.v:198626$14578_Y
-  attribute \src "libresoc.v:198628.18-198628.99"
-  wire $or$libresoc.v:198628$14580_Y
-  attribute \src "libresoc.v:198631.17-198631.97"
-  wire $or$libresoc.v:198631$14583_Y
+  attribute \src "libresoc.v:198633.17-198633.96"
+  wire $and$libresoc.v:198633$14577_Y
+  attribute \src "libresoc.v:198638.17-198638.96"
+  wire $and$libresoc.v:198638$14582_Y
+  attribute \src "libresoc.v:198635.18-198635.93"
+  wire $not$libresoc.v:198635$14579_Y
+  attribute \src "libresoc.v:198637.17-198637.92"
+  wire $not$libresoc.v:198637$14581_Y
+  attribute \src "libresoc.v:198640.17-198640.92"
+  wire $not$libresoc.v:198640$14584_Y
+  attribute \src "libresoc.v:198634.18-198634.98"
+  wire $or$libresoc.v:198634$14578_Y
+  attribute \src "libresoc.v:198636.18-198636.99"
+  wire $or$libresoc.v:198636$14580_Y
+  attribute \src "libresoc.v:198639.17-198639.97"
+  wire $or$libresoc.v:198639$14583_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
   wire \$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
@@ -416519,11 +416527,11 @@ module \upd_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
-  attribute \src "libresoc.v:198590.7-198590.15"
+  attribute \src "libresoc.v:198598.7-198598.15"
   wire \initial
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
   wire \q_int
@@ -416540,7 +416548,7 @@ module \upd_l
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
   wire input 2 \s_upd
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
-  cell $and $and$libresoc.v:198625$14577
+  cell $and $and$libresoc.v:198633$14577
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -416548,10 +416556,10 @@ module \upd_l
     parameter \Y_WIDTH 1
     connect \A \q_int
     connect \B \$7
-    connect \Y $and$libresoc.v:198625$14577_Y
+    connect \Y $and$libresoc.v:198633$14577_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
-  cell $and $and$libresoc.v:198630$14582
+  cell $and $and$libresoc.v:198638$14582
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -416559,34 +416567,34 @@ module \upd_l
     parameter \Y_WIDTH 1
     connect \A \q_int
     connect \B \$1
-    connect \Y $and$libresoc.v:198630$14582_Y
+    connect \Y $and$libresoc.v:198638$14582_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
-  cell $not $not$libresoc.v:198627$14579
+  cell $not $not$libresoc.v:198635$14579
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \q_upd
-    connect \Y $not$libresoc.v:198627$14579_Y
+    connect \Y $not$libresoc.v:198635$14579_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
-  cell $not $not$libresoc.v:198629$14581
+  cell $not $not$libresoc.v:198637$14581
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \r_upd
-    connect \Y $not$libresoc.v:198629$14581_Y
+    connect \Y $not$libresoc.v:198637$14581_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
-  cell $not $not$libresoc.v:198632$14584
+  cell $not $not$libresoc.v:198640$14584
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \r_upd
-    connect \Y $not$libresoc.v:198632$14584_Y
+    connect \Y $not$libresoc.v:198640$14584_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
-  cell $or $or$libresoc.v:198626$14578
+  cell $or $or$libresoc.v:198634$14578
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -416594,10 +416602,10 @@ module \upd_l
     parameter \Y_WIDTH 1
     connect \A \$9
     connect \B \s_upd
-    connect \Y $or$libresoc.v:198626$14578_Y
+    connect \Y $or$libresoc.v:198634$14578_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
-  cell $or $or$libresoc.v:198628$14580
+  cell $or $or$libresoc.v:198636$14580
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -416605,10 +416613,10 @@ module \upd_l
     parameter \Y_WIDTH 1
     connect \A \q_upd
     connect \B \q_int
-    connect \Y $or$libresoc.v:198628$14580_Y
+    connect \Y $or$libresoc.v:198636$14580_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
-  cell $or $or$libresoc.v:198631$14583
+  cell $or $or$libresoc.v:198639$14583
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -416616,39 +416624,39 @@ module \upd_l
     parameter \Y_WIDTH 1
     connect \A \$3
     connect \B \s_upd
-    connect \Y $or$libresoc.v:198631$14583_Y
+    connect \Y $or$libresoc.v:198639$14583_Y
   end
-  attribute \src "libresoc.v:198590.7-198590.20"
-  process $proc$libresoc.v:198590$14589
+  attribute \src "libresoc.v:198598.7-198598.20"
+  process $proc$libresoc.v:198598$14589
     assign { } { }
     assign $0\initial[0:0] 1'0
     sync always
       update \initial $0\initial[0:0]
     sync init
   end
-  attribute \src "libresoc.v:198612.7-198612.19"
-  process $proc$libresoc.v:198612$14590
+  attribute \src "libresoc.v:198620.7-198620.19"
+  process $proc$libresoc.v:198620$14590
     assign { } { }
     assign $1\q_int[0:0] 1'0
     sync always
     sync init
       update \q_int $1\q_int[0:0]
   end
-  attribute \src "libresoc.v:198633.3-198634.27"
-  process $proc$libresoc.v:198633$14585
+  attribute \src "libresoc.v:198641.3-198642.27"
+  process $proc$libresoc.v:198641$14585
     assign { } { }
     assign $0\q_int[0:0] \q_int$next
     sync posedge \coresync_clk
       update \q_int $0\q_int[0:0]
   end
-  attribute \src "libresoc.v:198635.3-198643.6"
-  process $proc$libresoc.v:198635$14586
+  attribute \src "libresoc.v:198643.3-198651.6"
+  process $proc$libresoc.v:198643$14586
     assign { } { }
     assign { } { }
     assign $0\q_int$next[0:0]$14587 $1\q_int$next[0:0]$14588
-    attribute \src "libresoc.v:198636.5-198636.29"
+    attribute \src "libresoc.v:198644.5-198644.29"
     switch \initial
-      attribute \src "libresoc.v:198636.9-198636.17"
+      attribute \src "libresoc.v:198644.9-198644.17"
       case 1'1
       case 
     end
@@ -416664,49 +416672,49 @@ module \upd_l
     sync always
       update \q_int$next $0\q_int$next[0:0]$14587
   end
-  connect \$9 $and$libresoc.v:198625$14577_Y
-  connect \$11 $or$libresoc.v:198626$14578_Y
-  connect \$13 $not$libresoc.v:198627$14579_Y
-  connect \$15 $or$libresoc.v:198628$14580_Y
-  connect \$1 $not$libresoc.v:198629$14581_Y
-  connect \$3 $and$libresoc.v:198630$14582_Y
-  connect \$5 $or$libresoc.v:198631$14583_Y
-  connect \$7 $not$libresoc.v:198632$14584_Y
+  connect \$9 $and$libresoc.v:198633$14577_Y
+  connect \$11 $or$libresoc.v:198634$14578_Y
+  connect \$13 $not$libresoc.v:198635$14579_Y
+  connect \$15 $or$libresoc.v:198636$14580_Y
+  connect \$1 $not$libresoc.v:198637$14581_Y
+  connect \$3 $and$libresoc.v:198638$14582_Y
+  connect \$5 $or$libresoc.v:198639$14583_Y
+  connect \$7 $not$libresoc.v:198640$14584_Y
   connect \qlq_upd \$15
   connect \qn_upd \$13
   connect \q_upd \$11
 end
-attribute \src "libresoc.v:198651.1-198709.10"
+attribute \src "libresoc.v:198659.1-198717.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l"
 attribute \generator "nMigen"
 module \valid_l
-  attribute \src "libresoc.v:198652.7-198652.20"
+  attribute \src "libresoc.v:198660.7-198660.20"
   wire $0\initial[0:0]
-  attribute \src "libresoc.v:198697.3-198705.6"
+  attribute \src "libresoc.v:198705.3-198713.6"
   wire $0\q_int$next[0:0]$14601
-  attribute \src "libresoc.v:198695.3-198696.27"
+  attribute \src "libresoc.v:198703.3-198704.27"
   wire $0\q_int[0:0]
-  attribute \src "libresoc.v:198697.3-198705.6"
+  attribute \src "libresoc.v:198705.3-198713.6"
   wire $1\q_int$next[0:0]$14602
-  attribute \src "libresoc.v:198674.7-198674.19"
+  attribute \src "libresoc.v:198682.7-198682.19"
   wire $1\q_int[0:0]
-  attribute \src "libresoc.v:198687.17-198687.96"
-  wire $and$libresoc.v:198687$14591_Y
-  attribute \src "libresoc.v:198692.17-198692.96"
-  wire $and$libresoc.v:198692$14596_Y
-  attribute \src "libresoc.v:198689.18-198689.95"
-  wire $not$libresoc.v:198689$14593_Y
-  attribute \src "libresoc.v:198691.17-198691.94"
-  wire $not$libresoc.v:198691$14595_Y
-  attribute \src "libresoc.v:198694.17-198694.94"
-  wire $not$libresoc.v:198694$14598_Y
-  attribute \src "libresoc.v:198688.18-198688.100"
-  wire $or$libresoc.v:198688$14592_Y
-  attribute \src "libresoc.v:198690.18-198690.101"
-  wire $or$libresoc.v:198690$14594_Y
-  attribute \src "libresoc.v:198693.17-198693.99"
-  wire $or$libresoc.v:198693$14597_Y
+  attribute \src "libresoc.v:198695.17-198695.96"
+  wire $and$libresoc.v:198695$14591_Y
+  attribute \src "libresoc.v:198700.17-198700.96"
+  wire $and$libresoc.v:198700$14596_Y
+  attribute \src "libresoc.v:198697.18-198697.95"
+  wire $not$libresoc.v:198697$14593_Y
+  attribute \src "libresoc.v:198699.17-198699.94"
+  wire $not$libresoc.v:198699$14595_Y
+  attribute \src "libresoc.v:198702.17-198702.94"
+  wire $not$libresoc.v:198702$14598_Y
+  attribute \src "libresoc.v:198696.18-198696.100"
+  wire $or$libresoc.v:198696$14592_Y
+  attribute \src "libresoc.v:198698.18-198698.101"
+  wire $or$libresoc.v:198698$14594_Y
+  attribute \src "libresoc.v:198701.17-198701.99"
+  wire $or$libresoc.v:198701$14597_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
   wire \$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
@@ -416723,11 +416731,11 @@ module \valid_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
-  attribute \src "libresoc.v:198652.7-198652.15"
+  attribute \src "libresoc.v:198660.7-198660.15"
   wire \initial
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
   wire \q_int
@@ -416744,7 +416752,7 @@ module \valid_l
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
   wire input 2 \s_valid
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
-  cell $and $and$libresoc.v:198687$14591
+  cell $and $and$libresoc.v:198695$14591
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -416752,10 +416760,10 @@ module \valid_l
     parameter \Y_WIDTH 1
     connect \A \q_int
     connect \B \$7
-    connect \Y $and$libresoc.v:198687$14591_Y
+    connect \Y $and$libresoc.v:198695$14591_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
-  cell $and $and$libresoc.v:198692$14596
+  cell $and $and$libresoc.v:198700$14596
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -416763,34 +416771,34 @@ module \valid_l
     parameter \Y_WIDTH 1
     connect \A \q_int
     connect \B \$1
-    connect \Y $and$libresoc.v:198692$14596_Y
+    connect \Y $and$libresoc.v:198700$14596_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
-  cell $not $not$libresoc.v:198689$14593
+  cell $not $not$libresoc.v:198697$14593
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \q_valid
-    connect \Y $not$libresoc.v:198689$14593_Y
+    connect \Y $not$libresoc.v:198697$14593_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
-  cell $not $not$libresoc.v:198691$14595
+  cell $not $not$libresoc.v:198699$14595
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \r_valid
-    connect \Y $not$libresoc.v:198691$14595_Y
+    connect \Y $not$libresoc.v:198699$14595_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
-  cell $not $not$libresoc.v:198694$14598
+  cell $not $not$libresoc.v:198702$14598
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \r_valid
-    connect \Y $not$libresoc.v:198694$14598_Y
+    connect \Y $not$libresoc.v:198702$14598_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
-  cell $or $or$libresoc.v:198688$14592
+  cell $or $or$libresoc.v:198696$14592
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -416798,10 +416806,10 @@ module \valid_l
     parameter \Y_WIDTH 1
     connect \A \$9
     connect \B \s_valid
-    connect \Y $or$libresoc.v:198688$14592_Y
+    connect \Y $or$libresoc.v:198696$14592_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
-  cell $or $or$libresoc.v:198690$14594
+  cell $or $or$libresoc.v:198698$14594
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -416809,10 +416817,10 @@ module \valid_l
     parameter \Y_WIDTH 1
     connect \A \q_valid
     connect \B \q_int
-    connect \Y $or$libresoc.v:198690$14594_Y
+    connect \Y $or$libresoc.v:198698$14594_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
-  cell $or $or$libresoc.v:198693$14597
+  cell $or $or$libresoc.v:198701$14597
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -416820,39 +416828,39 @@ module \valid_l
     parameter \Y_WIDTH 1
     connect \A \$3
     connect \B \s_valid
-    connect \Y $or$libresoc.v:198693$14597_Y
+    connect \Y $or$libresoc.v:198701$14597_Y
   end
-  attribute \src "libresoc.v:198652.7-198652.20"
-  process $proc$libresoc.v:198652$14603
+  attribute \src "libresoc.v:198660.7-198660.20"
+  process $proc$libresoc.v:198660$14603
     assign { } { }
     assign $0\initial[0:0] 1'0
     sync always
       update \initial $0\initial[0:0]
     sync init
   end
-  attribute \src "libresoc.v:198674.7-198674.19"
-  process $proc$libresoc.v:198674$14604
+  attribute \src "libresoc.v:198682.7-198682.19"
+  process $proc$libresoc.v:198682$14604
     assign { } { }
     assign $1\q_int[0:0] 1'0
     sync always
     sync init
       update \q_int $1\q_int[0:0]
   end
-  attribute \src "libresoc.v:198695.3-198696.27"
-  process $proc$libresoc.v:198695$14599
+  attribute \src "libresoc.v:198703.3-198704.27"
+  process $proc$libresoc.v:198703$14599
     assign { } { }
     assign $0\q_int[0:0] \q_int$next
     sync posedge \coresync_clk
       update \q_int $0\q_int[0:0]
   end
-  attribute \src "libresoc.v:198697.3-198705.6"
-  process $proc$libresoc.v:198697$14600
+  attribute \src "libresoc.v:198705.3-198713.6"
+  process $proc$libresoc.v:198705$14600
     assign { } { }
     assign { } { }
     assign $0\q_int$next[0:0]$14601 $1\q_int$next[0:0]$14602
-    attribute \src "libresoc.v:198698.5-198698.29"
+    attribute \src "libresoc.v:198706.5-198706.29"
     switch \initial
-      attribute \src "libresoc.v:198698.9-198698.17"
+      attribute \src "libresoc.v:198706.9-198706.17"
       case 1'1
       case 
     end
@@ -416868,49 +416876,49 @@ module \valid_l
     sync always
       update \q_int$next $0\q_int$next[0:0]$14601
   end
-  connect \$9 $and$libresoc.v:198687$14591_Y
-  connect \$11 $or$libresoc.v:198688$14592_Y
-  connect \$13 $not$libresoc.v:198689$14593_Y
-  connect \$15 $or$libresoc.v:198690$14594_Y
-  connect \$1 $not$libresoc.v:198691$14595_Y
-  connect \$3 $and$libresoc.v:198692$14596_Y
-  connect \$5 $or$libresoc.v:198693$14597_Y
-  connect \$7 $not$libresoc.v:198694$14598_Y
+  connect \$9 $and$libresoc.v:198695$14591_Y
+  connect \$11 $or$libresoc.v:198696$14592_Y
+  connect \$13 $not$libresoc.v:198697$14593_Y
+  connect \$15 $or$libresoc.v:198698$14594_Y
+  connect \$1 $not$libresoc.v:198699$14595_Y
+  connect \$3 $and$libresoc.v:198700$14596_Y
+  connect \$5 $or$libresoc.v:198701$14597_Y
+  connect \$7 $not$libresoc.v:198702$14598_Y
   connect \qlq_valid \$15
   connect \qn_valid \$13
   connect \q_valid \$11
 end
-attribute \src "libresoc.v:198713.1-198771.10"
+attribute \src "libresoc.v:198721.1-198779.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l"
 attribute \generator "nMigen"
 module \wri_l
-  attribute \src "libresoc.v:198714.7-198714.20"
+  attribute \src "libresoc.v:198722.7-198722.20"
   wire $0\initial[0:0]
-  attribute \src "libresoc.v:198759.3-198767.6"
+  attribute \src "libresoc.v:198767.3-198775.6"
   wire $0\q_int$next[0:0]$14615
-  attribute \src "libresoc.v:198757.3-198758.27"
+  attribute \src "libresoc.v:198765.3-198766.27"
   wire $0\q_int[0:0]
-  attribute \src "libresoc.v:198759.3-198767.6"
+  attribute \src "libresoc.v:198767.3-198775.6"
   wire $1\q_int$next[0:0]$14616
-  attribute \src "libresoc.v:198736.7-198736.19"
+  attribute \src "libresoc.v:198744.7-198744.19"
   wire $1\q_int[0:0]
-  attribute \src "libresoc.v:198749.17-198749.96"
-  wire $and$libresoc.v:198749$14605_Y
-  attribute \src "libresoc.v:198754.17-198754.96"
-  wire $and$libresoc.v:198754$14610_Y
-  attribute \src "libresoc.v:198751.18-198751.93"
-  wire $not$libresoc.v:198751$14607_Y
-  attribute \src "libresoc.v:198753.17-198753.92"
-  wire $not$libresoc.v:198753$14609_Y
-  attribute \src "libresoc.v:198756.17-198756.92"
-  wire $not$libresoc.v:198756$14612_Y
-  attribute \src "libresoc.v:198750.18-198750.98"
-  wire $or$libresoc.v:198750$14606_Y
-  attribute \src "libresoc.v:198752.18-198752.99"
-  wire $or$libresoc.v:198752$14608_Y
-  attribute \src "libresoc.v:198755.17-198755.97"
-  wire $or$libresoc.v:198755$14611_Y
+  attribute \src "libresoc.v:198757.17-198757.96"
+  wire $and$libresoc.v:198757$14605_Y
+  attribute \src "libresoc.v:198762.17-198762.96"
+  wire $and$libresoc.v:198762$14610_Y
+  attribute \src "libresoc.v:198759.18-198759.93"
+  wire $not$libresoc.v:198759$14607_Y
+  attribute \src "libresoc.v:198761.17-198761.92"
+  wire $not$libresoc.v:198761$14609_Y
+  attribute \src "libresoc.v:198764.17-198764.92"
+  wire $not$libresoc.v:198764$14612_Y
+  attribute \src "libresoc.v:198758.18-198758.98"
+  wire $or$libresoc.v:198758$14606_Y
+  attribute \src "libresoc.v:198760.18-198760.99"
+  wire $or$libresoc.v:198760$14608_Y
+  attribute \src "libresoc.v:198763.17-198763.97"
+  wire $or$libresoc.v:198763$14611_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
   wire \$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
@@ -416927,11 +416935,11 @@ module \wri_l
   wire \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
   wire \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 5 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
-  attribute \src "libresoc.v:198714.7-198714.15"
+  attribute \src "libresoc.v:198722.7-198722.15"
   wire \initial
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
   wire \q_int
@@ -416948,7 +416956,7 @@ module \wri_l
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
   wire input 2 \s_wri
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
-  cell $and $and$libresoc.v:198749$14605
+  cell $and $and$libresoc.v:198757$14605
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -416956,10 +416964,10 @@ module \wri_l
     parameter \Y_WIDTH 1
     connect \A \q_int
     connect \B \$7
-    connect \Y $and$libresoc.v:198749$14605_Y
+    connect \Y $and$libresoc.v:198757$14605_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
-  cell $and $and$libresoc.v:198754$14610
+  cell $and $and$libresoc.v:198762$14610
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -416967,34 +416975,34 @@ module \wri_l
     parameter \Y_WIDTH 1
     connect \A \q_int
     connect \B \$1
-    connect \Y $and$libresoc.v:198754$14610_Y
+    connect \Y $and$libresoc.v:198762$14610_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
-  cell $not $not$libresoc.v:198751$14607
+  cell $not $not$libresoc.v:198759$14607
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \q_wri
-    connect \Y $not$libresoc.v:198751$14607_Y
+    connect \Y $not$libresoc.v:198759$14607_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
-  cell $not $not$libresoc.v:198753$14609
+  cell $not $not$libresoc.v:198761$14609
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \r_wri
-    connect \Y $not$libresoc.v:198753$14609_Y
+    connect \Y $not$libresoc.v:198761$14609_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
-  cell $not $not$libresoc.v:198756$14612
+  cell $not $not$libresoc.v:198764$14612
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \r_wri
-    connect \Y $not$libresoc.v:198756$14612_Y
+    connect \Y $not$libresoc.v:198764$14612_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
-  cell $or $or$libresoc.v:198750$14606
+  cell $or $or$libresoc.v:198758$14606
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -417002,10 +417010,10 @@ module \wri_l
     parameter \Y_WIDTH 1
     connect \A \$9
     connect \B \s_wri
-    connect \Y $or$libresoc.v:198750$14606_Y
+    connect \Y $or$libresoc.v:198758$14606_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
-  cell $or $or$libresoc.v:198752$14608
+  cell $or $or$libresoc.v:198760$14608
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -417013,10 +417021,10 @@ module \wri_l
     parameter \Y_WIDTH 1
     connect \A \q_wri
     connect \B \q_int
-    connect \Y $or$libresoc.v:198752$14608_Y
+    connect \Y $or$libresoc.v:198760$14608_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
-  cell $or $or$libresoc.v:198755$14611
+  cell $or $or$libresoc.v:198763$14611
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -417024,39 +417032,39 @@ module \wri_l
     parameter \Y_WIDTH 1
     connect \A \$3
     connect \B \s_wri
-    connect \Y $or$libresoc.v:198755$14611_Y
+    connect \Y $or$libresoc.v:198763$14611_Y
   end
-  attribute \src "libresoc.v:198714.7-198714.20"
-  process $proc$libresoc.v:198714$14617
+  attribute \src "libresoc.v:198722.7-198722.20"
+  process $proc$libresoc.v:198722$14617
     assign { } { }
     assign $0\initial[0:0] 1'0
     sync always
       update \initial $0\initial[0:0]
     sync init
   end
-  attribute \src "libresoc.v:198736.7-198736.19"
-  process $proc$libresoc.v:198736$14618
+  attribute \src "libresoc.v:198744.7-198744.19"
+  process $proc$libresoc.v:198744$14618
     assign { } { }
     assign $1\q_int[0:0] 1'0
     sync always
     sync init
       update \q_int $1\q_int[0:0]
   end
-  attribute \src "libresoc.v:198757.3-198758.27"
-  process $proc$libresoc.v:198757$14613
+  attribute \src "libresoc.v:198765.3-198766.27"
+  process $proc$libresoc.v:198765$14613
     assign { } { }
     assign $0\q_int[0:0] \q_int$next
     sync posedge \coresync_clk
       update \q_int $0\q_int[0:0]
   end
-  attribute \src "libresoc.v:198759.3-198767.6"
-  process $proc$libresoc.v:198759$14614
+  attribute \src "libresoc.v:198767.3-198775.6"
+  process $proc$libresoc.v:198767$14614
     assign { } { }
     assign { } { }
     assign $0\q_int$next[0:0]$14615 $1\q_int$next[0:0]$14616
-    attribute \src "libresoc.v:198760.5-198760.29"
+    attribute \src "libresoc.v:198768.5-198768.29"
     switch \initial
-      attribute \src "libresoc.v:198760.9-198760.17"
+      attribute \src "libresoc.v:198768.9-198768.17"
       case 1'1
       case 
     end
@@ -417072,47 +417080,47 @@ module \wri_l
     sync always
       update \q_int$next $0\q_int$next[0:0]$14615
   end
-  connect \$9 $and$libresoc.v:198749$14605_Y
-  connect \$11 $or$libresoc.v:198750$14606_Y
-  connect \$13 $not$libresoc.v:198751$14607_Y
-  connect \$15 $or$libresoc.v:198752$14608_Y
-  connect \$1 $not$libresoc.v:198753$14609_Y
-  connect \$3 $and$libresoc.v:198754$14610_Y
-  connect \$5 $or$libresoc.v:198755$14611_Y
-  connect \$7 $not$libresoc.v:198756$14612_Y
+  connect \$9 $and$libresoc.v:198757$14605_Y
+  connect \$11 $or$libresoc.v:198758$14606_Y
+  connect \$13 $not$libresoc.v:198759$14607_Y
+  connect \$15 $or$libresoc.v:198760$14608_Y
+  connect \$1 $not$libresoc.v:198761$14609_Y
+  connect \$3 $and$libresoc.v:198762$14610_Y
+  connect \$5 $or$libresoc.v:198763$14611_Y
+  connect \$7 $not$libresoc.v:198764$14612_Y
   connect \qlq_wri \$15
   connect \qn_wri \$13
   connect \q_wri \$11
 end
-attribute \src "libresoc.v:198775.1-198841.10"
+attribute \src "libresoc.v:198783.1-198849.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a"
 attribute \generator "nMigen"
 module \wrpick_CR_cr_a
-  attribute \src "libresoc.v:198820.17-198820.91"
-  wire $not$libresoc.v:198820$14619_Y
-  attribute \src "libresoc.v:198822.18-198822.93"
-  wire $not$libresoc.v:198822$14621_Y
-  attribute \src "libresoc.v:198824.18-198824.93"
-  wire $not$libresoc.v:198824$14623_Y
-  attribute \src "libresoc.v:198825.17-198825.89"
-  wire width 6 $not$libresoc.v:198825$14624_Y
-  attribute \src "libresoc.v:198827.18-198827.93"
-  wire $not$libresoc.v:198827$14626_Y
-  attribute \src "libresoc.v:198830.17-198830.91"
-  wire $not$libresoc.v:198830$14629_Y
-  attribute \src "libresoc.v:198821.18-198821.106"
-  wire $reduce_or$libresoc.v:198821$14620_Y
-  attribute \src "libresoc.v:198823.18-198823.106"
-  wire $reduce_or$libresoc.v:198823$14622_Y
-  attribute \src "libresoc.v:198826.18-198826.106"
-  wire $reduce_or$libresoc.v:198826$14625_Y
-  attribute \src "libresoc.v:198828.18-198828.90"
-  wire $reduce_or$libresoc.v:198828$14627_Y
-  attribute \src "libresoc.v:198829.17-198829.103"
-  wire $reduce_or$libresoc.v:198829$14628_Y
-  attribute \src "libresoc.v:198831.17-198831.105"
-  wire $reduce_or$libresoc.v:198831$14630_Y
+  attribute \src "libresoc.v:198828.17-198828.91"
+  wire $not$libresoc.v:198828$14619_Y
+  attribute \src "libresoc.v:198830.18-198830.93"
+  wire $not$libresoc.v:198830$14621_Y
+  attribute \src "libresoc.v:198832.18-198832.93"
+  wire $not$libresoc.v:198832$14623_Y
+  attribute \src "libresoc.v:198833.17-198833.89"
+  wire width 6 $not$libresoc.v:198833$14624_Y
+  attribute \src "libresoc.v:198835.18-198835.93"
+  wire $not$libresoc.v:198835$14626_Y
+  attribute \src "libresoc.v:198838.17-198838.91"
+  wire $not$libresoc.v:198838$14629_Y
+  attribute \src "libresoc.v:198829.18-198829.106"
+  wire $reduce_or$libresoc.v:198829$14620_Y
+  attribute \src "libresoc.v:198831.18-198831.106"
+  wire $reduce_or$libresoc.v:198831$14622_Y
+  attribute \src "libresoc.v:198834.18-198834.106"
+  wire $reduce_or$libresoc.v:198834$14625_Y
+  attribute \src "libresoc.v:198836.18-198836.90"
+  wire $reduce_or$libresoc.v:198836$14627_Y
+  attribute \src "libresoc.v:198837.17-198837.103"
+  wire $reduce_or$libresoc.v:198837$14628_Y
+  attribute \src "libresoc.v:198839.17-198839.105"
+  wire $reduce_or$libresoc.v:198839$14630_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
   wire width 6 \$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
@@ -417158,113 +417166,113 @@ module \wrpick_CR_cr_a
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
   wire \t5
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:198820$14619
+  cell $not $not$libresoc.v:198828$14619
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$8
-    connect \Y $not$libresoc.v:198820$14619_Y
+    connect \Y $not$libresoc.v:198828$14619_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:198822$14621
+  cell $not $not$libresoc.v:198830$14621
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$12
-    connect \Y $not$libresoc.v:198822$14621_Y
+    connect \Y $not$libresoc.v:198830$14621_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:198824$14623
+  cell $not $not$libresoc.v:198832$14623
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$16
-    connect \Y $not$libresoc.v:198824$14623_Y
+    connect \Y $not$libresoc.v:198832$14623_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
-  cell $not $not$libresoc.v:198825$14624
+  cell $not $not$libresoc.v:198833$14624
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 6
     connect \A \i
-    connect \Y $not$libresoc.v:198825$14624_Y
+    connect \Y $not$libresoc.v:198833$14624_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:198827$14626
+  cell $not $not$libresoc.v:198835$14626
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$20
-    connect \Y $not$libresoc.v:198827$14626_Y
+    connect \Y $not$libresoc.v:198835$14626_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:198830$14629
+  cell $not $not$libresoc.v:198838$14629
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$4
-    connect \Y $not$libresoc.v:198830$14629_Y
+    connect \Y $not$libresoc.v:198838$14629_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:198821$14620
+  cell $reduce_or $reduce_or$libresoc.v:198829$14620
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
     connect \A { \i [2:0] \ni [3] }
-    connect \Y $reduce_or$libresoc.v:198821$14620_Y
+    connect \Y $reduce_or$libresoc.v:198829$14620_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:198823$14622
+  cell $reduce_or $reduce_or$libresoc.v:198831$14622
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
     connect \A { \i [3:0] \ni [4] }
-    connect \Y $reduce_or$libresoc.v:198823$14622_Y
+    connect \Y $reduce_or$libresoc.v:198831$14622_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:198826$14625
+  cell $reduce_or $reduce_or$libresoc.v:198834$14625
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 1
     connect \A { \i [4:0] \ni [5] }
-    connect \Y $reduce_or$libresoc.v:198826$14625_Y
+    connect \Y $reduce_or$libresoc.v:198834$14625_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
-  cell $reduce_or $reduce_or$libresoc.v:198828$14627
+  cell $reduce_or $reduce_or$libresoc.v:198836$14627
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $reduce_or$libresoc.v:198828$14627_Y
+    connect \Y $reduce_or$libresoc.v:198836$14627_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:198829$14628
+  cell $reduce_or $reduce_or$libresoc.v:198837$14628
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
     connect \A { \i [0] \ni [1] }
-    connect \Y $reduce_or$libresoc.v:198829$14628_Y
+    connect \Y $reduce_or$libresoc.v:198837$14628_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:198831$14630
+  cell $reduce_or $reduce_or$libresoc.v:198839$14630
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
     connect \A { \i [1:0] \ni [2] }
-    connect \Y $reduce_or$libresoc.v:198831$14630_Y
-  end
-  connect \$7 $not$libresoc.v:198820$14619_Y
-  connect \$12 $reduce_or$libresoc.v:198821$14620_Y
-  connect \$11 $not$libresoc.v:198822$14621_Y
-  connect \$16 $reduce_or$libresoc.v:198823$14622_Y
-  connect \$15 $not$libresoc.v:198824$14623_Y
-  connect \$1 $not$libresoc.v:198825$14624_Y
-  connect \$20 $reduce_or$libresoc.v:198826$14625_Y
-  connect \$19 $not$libresoc.v:198827$14626_Y
-  connect \$23 $reduce_or$libresoc.v:198828$14627_Y
-  connect \$4 $reduce_or$libresoc.v:198829$14628_Y
-  connect \$3 $not$libresoc.v:198830$14629_Y
-  connect \$8 $reduce_or$libresoc.v:198831$14630_Y
+    connect \Y $reduce_or$libresoc.v:198839$14630_Y
+  end
+  connect \$7 $not$libresoc.v:198828$14619_Y
+  connect \$12 $reduce_or$libresoc.v:198829$14620_Y
+  connect \$11 $not$libresoc.v:198830$14621_Y
+  connect \$16 $reduce_or$libresoc.v:198831$14622_Y
+  connect \$15 $not$libresoc.v:198832$14623_Y
+  connect \$1 $not$libresoc.v:198833$14624_Y
+  connect \$20 $reduce_or$libresoc.v:198834$14625_Y
+  connect \$19 $not$libresoc.v:198835$14626_Y
+  connect \$23 $reduce_or$libresoc.v:198836$14627_Y
+  connect \$4 $reduce_or$libresoc.v:198837$14628_Y
+  connect \$3 $not$libresoc.v:198838$14629_Y
+  connect \$8 $reduce_or$libresoc.v:198839$14630_Y
   connect \en_o \$23
   connect \o { \t5 \t4 \t3 \t2 \t1 \t0 }
   connect \t5 \$19
@@ -417275,15 +417283,15 @@ module \wrpick_CR_cr_a
   connect \t0 \i [0]
   connect \ni \$1
 end
-attribute \src "libresoc.v:198845.1-198866.10"
+attribute \src "libresoc.v:198853.1-198874.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr"
 attribute \generator "nMigen"
 module \wrpick_CR_full_cr
-  attribute \src "libresoc.v:198860.17-198860.89"
-  wire $not$libresoc.v:198860$14631_Y
-  attribute \src "libresoc.v:198861.17-198861.89"
-  wire $reduce_or$libresoc.v:198861$14632_Y
+  attribute \src "libresoc.v:198868.17-198868.89"
+  wire $not$libresoc.v:198868$14631_Y
+  attribute \src "libresoc.v:198869.17-198869.89"
+  wire $reduce_or$libresoc.v:198869$14632_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
   wire \$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
@@ -417299,53 +417307,53 @@ module \wrpick_CR_full_cr
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
   wire \t0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
-  cell $not $not$libresoc.v:198860$14631
+  cell $not $not$libresoc.v:198868$14631
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \i
-    connect \Y $not$libresoc.v:198860$14631_Y
+    connect \Y $not$libresoc.v:198868$14631_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
-  cell $reduce_or $reduce_or$libresoc.v:198861$14632
+  cell $reduce_or $reduce_or$libresoc.v:198869$14632
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $reduce_or$libresoc.v:198861$14632_Y
+    connect \Y $reduce_or$libresoc.v:198869$14632_Y
   end
-  connect \$1 $not$libresoc.v:198860$14631_Y
-  connect \$3 $reduce_or$libresoc.v:198861$14632_Y
+  connect \$1 $not$libresoc.v:198868$14631_Y
+  connect \$3 $reduce_or$libresoc.v:198869$14632_Y
   connect \en_o \$3
   connect \o \t0
   connect \t0 \i
   connect \ni \$1
 end
-attribute \src "libresoc.v:198870.1-198927.10"
+attribute \src "libresoc.v:198878.1-198935.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1"
 attribute \generator "nMigen"
 module \wrpick_FAST_fast1
-  attribute \src "libresoc.v:198909.17-198909.91"
-  wire $not$libresoc.v:198909$14633_Y
-  attribute \src "libresoc.v:198911.18-198911.93"
-  wire $not$libresoc.v:198911$14635_Y
-  attribute \src "libresoc.v:198913.18-198913.93"
-  wire $not$libresoc.v:198913$14637_Y
-  attribute \src "libresoc.v:198914.17-198914.89"
-  wire width 5 $not$libresoc.v:198914$14638_Y
   attribute \src "libresoc.v:198917.17-198917.91"
-  wire $not$libresoc.v:198917$14641_Y
-  attribute \src "libresoc.v:198910.18-198910.106"
-  wire $reduce_or$libresoc.v:198910$14634_Y
-  attribute \src "libresoc.v:198912.18-198912.106"
-  wire $reduce_or$libresoc.v:198912$14636_Y
-  attribute \src "libresoc.v:198915.18-198915.90"
-  wire $reduce_or$libresoc.v:198915$14639_Y
-  attribute \src "libresoc.v:198916.17-198916.103"
-  wire $reduce_or$libresoc.v:198916$14640_Y
-  attribute \src "libresoc.v:198918.17-198918.105"
-  wire $reduce_or$libresoc.v:198918$14642_Y
+  wire $not$libresoc.v:198917$14633_Y
+  attribute \src "libresoc.v:198919.18-198919.93"
+  wire $not$libresoc.v:198919$14635_Y
+  attribute \src "libresoc.v:198921.18-198921.93"
+  wire $not$libresoc.v:198921$14637_Y
+  attribute \src "libresoc.v:198922.17-198922.89"
+  wire width 5 $not$libresoc.v:198922$14638_Y
+  attribute \src "libresoc.v:198925.17-198925.91"
+  wire $not$libresoc.v:198925$14641_Y
+  attribute \src "libresoc.v:198918.18-198918.106"
+  wire $reduce_or$libresoc.v:198918$14634_Y
+  attribute \src "libresoc.v:198920.18-198920.106"
+  wire $reduce_or$libresoc.v:198920$14636_Y
+  attribute \src "libresoc.v:198923.18-198923.90"
+  wire $reduce_or$libresoc.v:198923$14639_Y
+  attribute \src "libresoc.v:198924.17-198924.103"
+  wire $reduce_or$libresoc.v:198924$14640_Y
+  attribute \src "libresoc.v:198926.17-198926.105"
+  wire $reduce_or$libresoc.v:198926$14642_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
   wire width 5 \$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
@@ -417385,95 +417393,95 @@ module \wrpick_FAST_fast1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
   wire \t4
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:198909$14633
+  cell $not $not$libresoc.v:198917$14633
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$8
-    connect \Y $not$libresoc.v:198909$14633_Y
+    connect \Y $not$libresoc.v:198917$14633_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:198911$14635
+  cell $not $not$libresoc.v:198919$14635
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$12
-    connect \Y $not$libresoc.v:198911$14635_Y
+    connect \Y $not$libresoc.v:198919$14635_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:198913$14637
+  cell $not $not$libresoc.v:198921$14637
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$16
-    connect \Y $not$libresoc.v:198913$14637_Y
+    connect \Y $not$libresoc.v:198921$14637_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
-  cell $not $not$libresoc.v:198914$14638
+  cell $not $not$libresoc.v:198922$14638
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 5
     connect \A \i
-    connect \Y $not$libresoc.v:198914$14638_Y
+    connect \Y $not$libresoc.v:198922$14638_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:198917$14641
+  cell $not $not$libresoc.v:198925$14641
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$4
-    connect \Y $not$libresoc.v:198917$14641_Y
+    connect \Y $not$libresoc.v:198925$14641_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:198910$14634
+  cell $reduce_or $reduce_or$libresoc.v:198918$14634
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
     connect \A { \i [2:0] \ni [3] }
-    connect \Y $reduce_or$libresoc.v:198910$14634_Y
+    connect \Y $reduce_or$libresoc.v:198918$14634_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:198912$14636
+  cell $reduce_or $reduce_or$libresoc.v:198920$14636
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
     connect \A { \i [3:0] \ni [4] }
-    connect \Y $reduce_or$libresoc.v:198912$14636_Y
+    connect \Y $reduce_or$libresoc.v:198920$14636_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
-  cell $reduce_or $reduce_or$libresoc.v:198915$14639
+  cell $reduce_or $reduce_or$libresoc.v:198923$14639
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $reduce_or$libresoc.v:198915$14639_Y
+    connect \Y $reduce_or$libresoc.v:198923$14639_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:198916$14640
+  cell $reduce_or $reduce_or$libresoc.v:198924$14640
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
     connect \A { \i [0] \ni [1] }
-    connect \Y $reduce_or$libresoc.v:198916$14640_Y
+    connect \Y $reduce_or$libresoc.v:198924$14640_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:198918$14642
+  cell $reduce_or $reduce_or$libresoc.v:198926$14642
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
     connect \A { \i [1:0] \ni [2] }
-    connect \Y $reduce_or$libresoc.v:198918$14642_Y
-  end
-  connect \$7 $not$libresoc.v:198909$14633_Y
-  connect \$12 $reduce_or$libresoc.v:198910$14634_Y
-  connect \$11 $not$libresoc.v:198911$14635_Y
-  connect \$16 $reduce_or$libresoc.v:198912$14636_Y
-  connect \$15 $not$libresoc.v:198913$14637_Y
-  connect \$1 $not$libresoc.v:198914$14638_Y
-  connect \$19 $reduce_or$libresoc.v:198915$14639_Y
-  connect \$4 $reduce_or$libresoc.v:198916$14640_Y
-  connect \$3 $not$libresoc.v:198917$14641_Y
-  connect \$8 $reduce_or$libresoc.v:198918$14642_Y
+    connect \Y $reduce_or$libresoc.v:198926$14642_Y
+  end
+  connect \$7 $not$libresoc.v:198917$14633_Y
+  connect \$12 $reduce_or$libresoc.v:198918$14634_Y
+  connect \$11 $not$libresoc.v:198919$14635_Y
+  connect \$16 $reduce_or$libresoc.v:198920$14636_Y
+  connect \$15 $not$libresoc.v:198921$14637_Y
+  connect \$1 $not$libresoc.v:198922$14638_Y
+  connect \$19 $reduce_or$libresoc.v:198923$14639_Y
+  connect \$4 $reduce_or$libresoc.v:198924$14640_Y
+  connect \$3 $not$libresoc.v:198925$14641_Y
+  connect \$8 $reduce_or$libresoc.v:198926$14642_Y
   connect \en_o \$19
   connect \o { \t4 \t3 \t2 \t1 \t0 }
   connect \t4 \$15
@@ -417483,51 +417491,51 @@ module \wrpick_FAST_fast1
   connect \t0 \i [0]
   connect \ni \$1
 end
-attribute \src "libresoc.v:198931.1-199033.10"
+attribute \src "libresoc.v:198939.1-199041.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o"
 attribute \generator "nMigen"
 module \wrpick_INT_o
-  attribute \src "libresoc.v:199000.17-199000.91"
-  wire $not$libresoc.v:199000$14643_Y
-  attribute \src "libresoc.v:199002.18-199002.93"
-  wire $not$libresoc.v:199002$14645_Y
-  attribute \src "libresoc.v:199004.18-199004.93"
-  wire $not$libresoc.v:199004$14647_Y
-  attribute \src "libresoc.v:199005.17-199005.89"
-  wire width 10 $not$libresoc.v:199005$14648_Y
-  attribute \src "libresoc.v:199007.18-199007.93"
-  wire $not$libresoc.v:199007$14650_Y
-  attribute \src "libresoc.v:199009.18-199009.93"
-  wire $not$libresoc.v:199009$14652_Y
-  attribute \src "libresoc.v:199011.18-199011.93"
-  wire $not$libresoc.v:199011$14654_Y
-  attribute \src "libresoc.v:199013.18-199013.93"
-  wire $not$libresoc.v:199013$14656_Y
+  attribute \src "libresoc.v:199008.17-199008.91"
+  wire $not$libresoc.v:199008$14643_Y
+  attribute \src "libresoc.v:199010.18-199010.93"
+  wire $not$libresoc.v:199010$14645_Y
+  attribute \src "libresoc.v:199012.18-199012.93"
+  wire $not$libresoc.v:199012$14647_Y
+  attribute \src "libresoc.v:199013.17-199013.89"
+  wire width 10 $not$libresoc.v:199013$14648_Y
   attribute \src "libresoc.v:199015.18-199015.93"
-  wire $not$libresoc.v:199015$14658_Y
-  attribute \src "libresoc.v:199018.17-199018.91"
-  wire $not$libresoc.v:199018$14661_Y
-  attribute \src "libresoc.v:199001.18-199001.106"
-  wire $reduce_or$libresoc.v:199001$14644_Y
-  attribute \src "libresoc.v:199003.18-199003.106"
-  wire $reduce_or$libresoc.v:199003$14646_Y
-  attribute \src "libresoc.v:199006.18-199006.106"
-  wire $reduce_or$libresoc.v:199006$14649_Y
-  attribute \src "libresoc.v:199008.18-199008.106"
-  wire $reduce_or$libresoc.v:199008$14651_Y
-  attribute \src "libresoc.v:199010.18-199010.106"
-  wire $reduce_or$libresoc.v:199010$14653_Y
-  attribute \src "libresoc.v:199012.18-199012.106"
-  wire $reduce_or$libresoc.v:199012$14655_Y
+  wire $not$libresoc.v:199015$14650_Y
+  attribute \src "libresoc.v:199017.18-199017.93"
+  wire $not$libresoc.v:199017$14652_Y
+  attribute \src "libresoc.v:199019.18-199019.93"
+  wire $not$libresoc.v:199019$14654_Y
+  attribute \src "libresoc.v:199021.18-199021.93"
+  wire $not$libresoc.v:199021$14656_Y
+  attribute \src "libresoc.v:199023.18-199023.93"
+  wire $not$libresoc.v:199023$14658_Y
+  attribute \src "libresoc.v:199026.17-199026.91"
+  wire $not$libresoc.v:199026$14661_Y
+  attribute \src "libresoc.v:199009.18-199009.106"
+  wire $reduce_or$libresoc.v:199009$14644_Y
+  attribute \src "libresoc.v:199011.18-199011.106"
+  wire $reduce_or$libresoc.v:199011$14646_Y
   attribute \src "libresoc.v:199014.18-199014.106"
-  wire $reduce_or$libresoc.v:199014$14657_Y
-  attribute \src "libresoc.v:199016.18-199016.90"
-  wire $reduce_or$libresoc.v:199016$14659_Y
-  attribute \src "libresoc.v:199017.17-199017.103"
-  wire $reduce_or$libresoc.v:199017$14660_Y
-  attribute \src "libresoc.v:199019.17-199019.105"
-  wire $reduce_or$libresoc.v:199019$14662_Y
+  wire $reduce_or$libresoc.v:199014$14649_Y
+  attribute \src "libresoc.v:199016.18-199016.106"
+  wire $reduce_or$libresoc.v:199016$14651_Y
+  attribute \src "libresoc.v:199018.18-199018.106"
+  wire $reduce_or$libresoc.v:199018$14653_Y
+  attribute \src "libresoc.v:199020.18-199020.106"
+  wire $reduce_or$libresoc.v:199020$14655_Y
+  attribute \src "libresoc.v:199022.18-199022.106"
+  wire $reduce_or$libresoc.v:199022$14657_Y
+  attribute \src "libresoc.v:199024.18-199024.90"
+  wire $reduce_or$libresoc.v:199024$14659_Y
+  attribute \src "libresoc.v:199025.17-199025.103"
+  wire $reduce_or$libresoc.v:199025$14660_Y
+  attribute \src "libresoc.v:199027.17-199027.105"
+  wire $reduce_or$libresoc.v:199027$14662_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
   wire width 10 \$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
@@ -417597,185 +417605,185 @@ module \wrpick_INT_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
   wire \t9
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199000$14643
+  cell $not $not$libresoc.v:199008$14643
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$8
-    connect \Y $not$libresoc.v:199000$14643_Y
+    connect \Y $not$libresoc.v:199008$14643_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199002$14645
+  cell $not $not$libresoc.v:199010$14645
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$12
-    connect \Y $not$libresoc.v:199002$14645_Y
+    connect \Y $not$libresoc.v:199010$14645_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199004$14647
+  cell $not $not$libresoc.v:199012$14647
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$16
-    connect \Y $not$libresoc.v:199004$14647_Y
+    connect \Y $not$libresoc.v:199012$14647_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
-  cell $not $not$libresoc.v:199005$14648
+  cell $not $not$libresoc.v:199013$14648
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \Y_WIDTH 10
     connect \A \i
-    connect \Y $not$libresoc.v:199005$14648_Y
+    connect \Y $not$libresoc.v:199013$14648_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199007$14650
+  cell $not $not$libresoc.v:199015$14650
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$20
-    connect \Y $not$libresoc.v:199007$14650_Y
+    connect \Y $not$libresoc.v:199015$14650_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199009$14652
+  cell $not $not$libresoc.v:199017$14652
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$24
-    connect \Y $not$libresoc.v:199009$14652_Y
+    connect \Y $not$libresoc.v:199017$14652_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199011$14654
+  cell $not $not$libresoc.v:199019$14654
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$28
-    connect \Y $not$libresoc.v:199011$14654_Y
+    connect \Y $not$libresoc.v:199019$14654_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199013$14656
+  cell $not $not$libresoc.v:199021$14656
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$32
-    connect \Y $not$libresoc.v:199013$14656_Y
+    connect \Y $not$libresoc.v:199021$14656_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199015$14658
+  cell $not $not$libresoc.v:199023$14658
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$36
-    connect \Y $not$libresoc.v:199015$14658_Y
+    connect \Y $not$libresoc.v:199023$14658_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199018$14661
+  cell $not $not$libresoc.v:199026$14661
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$4
-    connect \Y $not$libresoc.v:199018$14661_Y
+    connect \Y $not$libresoc.v:199026$14661_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199001$14644
+  cell $reduce_or $reduce_or$libresoc.v:199009$14644
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
     connect \A { \i [2:0] \ni [3] }
-    connect \Y $reduce_or$libresoc.v:199001$14644_Y
+    connect \Y $reduce_or$libresoc.v:199009$14644_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199003$14646
+  cell $reduce_or $reduce_or$libresoc.v:199011$14646
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
     connect \A { \i [3:0] \ni [4] }
-    connect \Y $reduce_or$libresoc.v:199003$14646_Y
+    connect \Y $reduce_or$libresoc.v:199011$14646_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199006$14649
+  cell $reduce_or $reduce_or$libresoc.v:199014$14649
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 1
     connect \A { \i [4:0] \ni [5] }
-    connect \Y $reduce_or$libresoc.v:199006$14649_Y
+    connect \Y $reduce_or$libresoc.v:199014$14649_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199008$14651
+  cell $reduce_or $reduce_or$libresoc.v:199016$14651
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \Y_WIDTH 1
     connect \A { \i [5:0] \ni [6] }
-    connect \Y $reduce_or$libresoc.v:199008$14651_Y
+    connect \Y $reduce_or$libresoc.v:199016$14651_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199010$14653
+  cell $reduce_or $reduce_or$libresoc.v:199018$14653
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \Y_WIDTH 1
     connect \A { \i [6:0] \ni [7] }
-    connect \Y $reduce_or$libresoc.v:199010$14653_Y
+    connect \Y $reduce_or$libresoc.v:199018$14653_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199012$14655
+  cell $reduce_or $reduce_or$libresoc.v:199020$14655
     parameter \A_SIGNED 0
     parameter \A_WIDTH 9
     parameter \Y_WIDTH 1
     connect \A { \i [7:0] \ni [8] }
-    connect \Y $reduce_or$libresoc.v:199012$14655_Y
+    connect \Y $reduce_or$libresoc.v:199020$14655_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199014$14657
+  cell $reduce_or $reduce_or$libresoc.v:199022$14657
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \Y_WIDTH 1
     connect \A { \i [8:0] \ni [9] }
-    connect \Y $reduce_or$libresoc.v:199014$14657_Y
+    connect \Y $reduce_or$libresoc.v:199022$14657_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
-  cell $reduce_or $reduce_or$libresoc.v:199016$14659
+  cell $reduce_or $reduce_or$libresoc.v:199024$14659
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $reduce_or$libresoc.v:199016$14659_Y
+    connect \Y $reduce_or$libresoc.v:199024$14659_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199017$14660
+  cell $reduce_or $reduce_or$libresoc.v:199025$14660
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
     connect \A { \i [0] \ni [1] }
-    connect \Y $reduce_or$libresoc.v:199017$14660_Y
+    connect \Y $reduce_or$libresoc.v:199025$14660_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199019$14662
+  cell $reduce_or $reduce_or$libresoc.v:199027$14662
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
     connect \A { \i [1:0] \ni [2] }
-    connect \Y $reduce_or$libresoc.v:199019$14662_Y
-  end
-  connect \$7 $not$libresoc.v:199000$14643_Y
-  connect \$12 $reduce_or$libresoc.v:199001$14644_Y
-  connect \$11 $not$libresoc.v:199002$14645_Y
-  connect \$16 $reduce_or$libresoc.v:199003$14646_Y
-  connect \$15 $not$libresoc.v:199004$14647_Y
-  connect \$1 $not$libresoc.v:199005$14648_Y
-  connect \$20 $reduce_or$libresoc.v:199006$14649_Y
-  connect \$19 $not$libresoc.v:199007$14650_Y
-  connect \$24 $reduce_or$libresoc.v:199008$14651_Y
-  connect \$23 $not$libresoc.v:199009$14652_Y
-  connect \$28 $reduce_or$libresoc.v:199010$14653_Y
-  connect \$27 $not$libresoc.v:199011$14654_Y
-  connect \$32 $reduce_or$libresoc.v:199012$14655_Y
-  connect \$31 $not$libresoc.v:199013$14656_Y
-  connect \$36 $reduce_or$libresoc.v:199014$14657_Y
-  connect \$35 $not$libresoc.v:199015$14658_Y
-  connect \$39 $reduce_or$libresoc.v:199016$14659_Y
-  connect \$4 $reduce_or$libresoc.v:199017$14660_Y
-  connect \$3 $not$libresoc.v:199018$14661_Y
-  connect \$8 $reduce_or$libresoc.v:199019$14662_Y
+    connect \Y $reduce_or$libresoc.v:199027$14662_Y
+  end
+  connect \$7 $not$libresoc.v:199008$14643_Y
+  connect \$12 $reduce_or$libresoc.v:199009$14644_Y
+  connect \$11 $not$libresoc.v:199010$14645_Y
+  connect \$16 $reduce_or$libresoc.v:199011$14646_Y
+  connect \$15 $not$libresoc.v:199012$14647_Y
+  connect \$1 $not$libresoc.v:199013$14648_Y
+  connect \$20 $reduce_or$libresoc.v:199014$14649_Y
+  connect \$19 $not$libresoc.v:199015$14650_Y
+  connect \$24 $reduce_or$libresoc.v:199016$14651_Y
+  connect \$23 $not$libresoc.v:199017$14652_Y
+  connect \$28 $reduce_or$libresoc.v:199018$14653_Y
+  connect \$27 $not$libresoc.v:199019$14654_Y
+  connect \$32 $reduce_or$libresoc.v:199020$14655_Y
+  connect \$31 $not$libresoc.v:199021$14656_Y
+  connect \$36 $reduce_or$libresoc.v:199022$14657_Y
+  connect \$35 $not$libresoc.v:199023$14658_Y
+  connect \$39 $reduce_or$libresoc.v:199024$14659_Y
+  connect \$4 $reduce_or$libresoc.v:199025$14660_Y
+  connect \$3 $not$libresoc.v:199026$14661_Y
+  connect \$8 $reduce_or$libresoc.v:199027$14662_Y
   connect \en_o \$39
   connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
   connect \t9 \$35
@@ -417790,15 +417798,15 @@ module \wrpick_INT_o
   connect \t0 \i [0]
   connect \ni \$1
 end
-attribute \src "libresoc.v:199037.1-199058.10"
+attribute \src "libresoc.v:199045.1-199066.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1"
 attribute \generator "nMigen"
 module \wrpick_SPR_spr1
-  attribute \src "libresoc.v:199052.17-199052.89"
-  wire $not$libresoc.v:199052$14663_Y
-  attribute \src "libresoc.v:199053.17-199053.89"
-  wire $reduce_or$libresoc.v:199053$14664_Y
+  attribute \src "libresoc.v:199060.17-199060.89"
+  wire $not$libresoc.v:199060$14663_Y
+  attribute \src "libresoc.v:199061.17-199061.89"
+  wire $reduce_or$libresoc.v:199061$14664_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
   wire \$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
@@ -417814,37 +417822,37 @@ module \wrpick_SPR_spr1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
   wire \t0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
-  cell $not $not$libresoc.v:199052$14663
+  cell $not $not$libresoc.v:199060$14663
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \i
-    connect \Y $not$libresoc.v:199052$14663_Y
+    connect \Y $not$libresoc.v:199060$14663_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
-  cell $reduce_or $reduce_or$libresoc.v:199053$14664
+  cell $reduce_or $reduce_or$libresoc.v:199061$14664
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $reduce_or$libresoc.v:199053$14664_Y
+    connect \Y $reduce_or$libresoc.v:199061$14664_Y
   end
-  connect \$1 $not$libresoc.v:199052$14663_Y
-  connect \$3 $reduce_or$libresoc.v:199053$14664_Y
+  connect \$1 $not$libresoc.v:199060$14663_Y
+  connect \$3 $reduce_or$libresoc.v:199061$14664_Y
   connect \en_o \$3
   connect \o \t0
   connect \t0 \i
   connect \ni \$1
 end
-attribute \src "libresoc.v:199062.1-199083.10"
+attribute \src "libresoc.v:199070.1-199091.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr"
 attribute \generator "nMigen"
 module \wrpick_STATE_msr
-  attribute \src "libresoc.v:199077.17-199077.89"
-  wire $not$libresoc.v:199077$14665_Y
-  attribute \src "libresoc.v:199078.17-199078.89"
-  wire $reduce_or$libresoc.v:199078$14666_Y
+  attribute \src "libresoc.v:199085.17-199085.89"
+  wire $not$libresoc.v:199085$14665_Y
+  attribute \src "libresoc.v:199086.17-199086.89"
+  wire $reduce_or$libresoc.v:199086$14666_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
   wire \$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
@@ -417860,41 +417868,41 @@ module \wrpick_STATE_msr
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
   wire \t0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
-  cell $not $not$libresoc.v:199077$14665
+  cell $not $not$libresoc.v:199085$14665
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \i
-    connect \Y $not$libresoc.v:199077$14665_Y
+    connect \Y $not$libresoc.v:199085$14665_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
-  cell $reduce_or $reduce_or$libresoc.v:199078$14666
+  cell $reduce_or $reduce_or$libresoc.v:199086$14666
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $reduce_or$libresoc.v:199078$14666_Y
+    connect \Y $reduce_or$libresoc.v:199086$14666_Y
   end
-  connect \$1 $not$libresoc.v:199077$14665_Y
-  connect \$3 $reduce_or$libresoc.v:199078$14666_Y
+  connect \$1 $not$libresoc.v:199085$14665_Y
+  connect \$3 $reduce_or$libresoc.v:199086$14666_Y
   connect \en_o \$3
   connect \o \t0
   connect \t0 \i
   connect \ni \$1
 end
-attribute \src "libresoc.v:199087.1-199117.10"
+attribute \src "libresoc.v:199095.1-199125.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia"
 attribute \generator "nMigen"
 module \wrpick_STATE_nia
-  attribute \src "libresoc.v:199108.17-199108.89"
-  wire width 2 $not$libresoc.v:199108$14667_Y
-  attribute \src "libresoc.v:199110.17-199110.91"
-  wire $not$libresoc.v:199110$14669_Y
-  attribute \src "libresoc.v:199109.17-199109.103"
-  wire $reduce_or$libresoc.v:199109$14668_Y
-  attribute \src "libresoc.v:199111.17-199111.89"
-  wire $reduce_or$libresoc.v:199111$14670_Y
+  attribute \src "libresoc.v:199116.17-199116.89"
+  wire width 2 $not$libresoc.v:199116$14667_Y
+  attribute \src "libresoc.v:199118.17-199118.91"
+  wire $not$libresoc.v:199118$14669_Y
+  attribute \src "libresoc.v:199117.17-199117.103"
+  wire $reduce_or$libresoc.v:199117$14668_Y
+  attribute \src "libresoc.v:199119.17-199119.89"
+  wire $reduce_or$libresoc.v:199119$14670_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
   wire width 2 \$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
@@ -417916,64 +417924,64 @@ module \wrpick_STATE_nia
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
   wire \t1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
-  cell $not $not$libresoc.v:199108$14667
+  cell $not $not$libresoc.v:199116$14667
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 2
     connect \A \i
-    connect \Y $not$libresoc.v:199108$14667_Y
+    connect \Y $not$libresoc.v:199116$14667_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199110$14669
+  cell $not $not$libresoc.v:199118$14669
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$4
-    connect \Y $not$libresoc.v:199110$14669_Y
+    connect \Y $not$libresoc.v:199118$14669_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199109$14668
+  cell $reduce_or $reduce_or$libresoc.v:199117$14668
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
     connect \A { \i [0] \ni [1] }
-    connect \Y $reduce_or$libresoc.v:199109$14668_Y
+    connect \Y $reduce_or$libresoc.v:199117$14668_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
-  cell $reduce_or $reduce_or$libresoc.v:199111$14670
+  cell $reduce_or $reduce_or$libresoc.v:199119$14670
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $reduce_or$libresoc.v:199111$14670_Y
+    connect \Y $reduce_or$libresoc.v:199119$14670_Y
   end
-  connect \$1 $not$libresoc.v:199108$14667_Y
-  connect \$4 $reduce_or$libresoc.v:199109$14668_Y
-  connect \$3 $not$libresoc.v:199110$14669_Y
-  connect \$7 $reduce_or$libresoc.v:199111$14670_Y
+  connect \$1 $not$libresoc.v:199116$14667_Y
+  connect \$4 $reduce_or$libresoc.v:199117$14668_Y
+  connect \$3 $not$libresoc.v:199118$14669_Y
+  connect \$7 $reduce_or$libresoc.v:199119$14670_Y
   connect \en_o \$7
   connect \o { \t1 \t0 }
   connect \t1 \$3
   connect \t0 \i [0]
   connect \ni \$1
 end
-attribute \src "libresoc.v:199121.1-199160.10"
+attribute \src "libresoc.v:199129.1-199168.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca"
 attribute \generator "nMigen"
 module \wrpick_XER_xer_ca
-  attribute \src "libresoc.v:199148.17-199148.91"
-  wire $not$libresoc.v:199148$14671_Y
-  attribute \src "libresoc.v:199150.17-199150.89"
-  wire width 3 $not$libresoc.v:199150$14673_Y
-  attribute \src "libresoc.v:199152.17-199152.91"
-  wire $not$libresoc.v:199152$14675_Y
-  attribute \src "libresoc.v:199149.18-199149.90"
-  wire $reduce_or$libresoc.v:199149$14672_Y
-  attribute \src "libresoc.v:199151.17-199151.103"
-  wire $reduce_or$libresoc.v:199151$14674_Y
-  attribute \src "libresoc.v:199153.17-199153.105"
-  wire $reduce_or$libresoc.v:199153$14676_Y
+  attribute \src "libresoc.v:199156.17-199156.91"
+  wire $not$libresoc.v:199156$14671_Y
+  attribute \src "libresoc.v:199158.17-199158.89"
+  wire width 3 $not$libresoc.v:199158$14673_Y
+  attribute \src "libresoc.v:199160.17-199160.91"
+  wire $not$libresoc.v:199160$14675_Y
+  attribute \src "libresoc.v:199157.18-199157.90"
+  wire $reduce_or$libresoc.v:199157$14672_Y
+  attribute \src "libresoc.v:199159.17-199159.103"
+  wire $reduce_or$libresoc.v:199159$14674_Y
+  attribute \src "libresoc.v:199161.17-199161.105"
+  wire $reduce_or$libresoc.v:199161$14676_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
   wire width 3 \$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
@@ -418001,59 +418009,59 @@ module \wrpick_XER_xer_ca
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
   wire \t2
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199148$14671
+  cell $not $not$libresoc.v:199156$14671
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$8
-    connect \Y $not$libresoc.v:199148$14671_Y
+    connect \Y $not$libresoc.v:199156$14671_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
-  cell $not $not$libresoc.v:199150$14673
+  cell $not $not$libresoc.v:199158$14673
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A \i
-    connect \Y $not$libresoc.v:199150$14673_Y
+    connect \Y $not$libresoc.v:199158$14673_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199152$14675
+  cell $not $not$libresoc.v:199160$14675
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$4
-    connect \Y $not$libresoc.v:199152$14675_Y
+    connect \Y $not$libresoc.v:199160$14675_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
-  cell $reduce_or $reduce_or$libresoc.v:199149$14672
+  cell $reduce_or $reduce_or$libresoc.v:199157$14672
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $reduce_or$libresoc.v:199149$14672_Y
+    connect \Y $reduce_or$libresoc.v:199157$14672_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199151$14674
+  cell $reduce_or $reduce_or$libresoc.v:199159$14674
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
     connect \A { \i [0] \ni [1] }
-    connect \Y $reduce_or$libresoc.v:199151$14674_Y
+    connect \Y $reduce_or$libresoc.v:199159$14674_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199153$14676
+  cell $reduce_or $reduce_or$libresoc.v:199161$14676
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
     connect \A { \i [1:0] \ni [2] }
-    connect \Y $reduce_or$libresoc.v:199153$14676_Y
-  end
-  connect \$7 $not$libresoc.v:199148$14671_Y
-  connect \$11 $reduce_or$libresoc.v:199149$14672_Y
-  connect \$1 $not$libresoc.v:199150$14673_Y
-  connect \$4 $reduce_or$libresoc.v:199151$14674_Y
-  connect \$3 $not$libresoc.v:199152$14675_Y
-  connect \$8 $reduce_or$libresoc.v:199153$14676_Y
+    connect \Y $reduce_or$libresoc.v:199161$14676_Y
+  end
+  connect \$7 $not$libresoc.v:199156$14671_Y
+  connect \$11 $reduce_or$libresoc.v:199157$14672_Y
+  connect \$1 $not$libresoc.v:199158$14673_Y
+  connect \$4 $reduce_or$libresoc.v:199159$14674_Y
+  connect \$3 $not$libresoc.v:199160$14675_Y
+  connect \$8 $reduce_or$libresoc.v:199161$14676_Y
   connect \en_o \$11
   connect \o { \t2 \t1 \t0 }
   connect \t2 \$7
@@ -418061,27 +418069,27 @@ module \wrpick_XER_xer_ca
   connect \t0 \i [0]
   connect \ni \$1
 end
-attribute \src "libresoc.v:199164.1-199212.10"
+attribute \src "libresoc.v:199172.1-199220.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov"
 attribute \generator "nMigen"
 module \wrpick_XER_xer_ov
-  attribute \src "libresoc.v:199197.17-199197.91"
-  wire $not$libresoc.v:199197$14677_Y
-  attribute \src "libresoc.v:199199.18-199199.93"
-  wire $not$libresoc.v:199199$14679_Y
-  attribute \src "libresoc.v:199201.17-199201.89"
-  wire width 4 $not$libresoc.v:199201$14681_Y
-  attribute \src "libresoc.v:199203.17-199203.91"
-  wire $not$libresoc.v:199203$14683_Y
-  attribute \src "libresoc.v:199198.18-199198.106"
-  wire $reduce_or$libresoc.v:199198$14678_Y
-  attribute \src "libresoc.v:199200.18-199200.90"
-  wire $reduce_or$libresoc.v:199200$14680_Y
-  attribute \src "libresoc.v:199202.17-199202.103"
-  wire $reduce_or$libresoc.v:199202$14682_Y
-  attribute \src "libresoc.v:199204.17-199204.105"
-  wire $reduce_or$libresoc.v:199204$14684_Y
+  attribute \src "libresoc.v:199205.17-199205.91"
+  wire $not$libresoc.v:199205$14677_Y
+  attribute \src "libresoc.v:199207.18-199207.93"
+  wire $not$libresoc.v:199207$14679_Y
+  attribute \src "libresoc.v:199209.17-199209.89"
+  wire width 4 $not$libresoc.v:199209$14681_Y
+  attribute \src "libresoc.v:199211.17-199211.91"
+  wire $not$libresoc.v:199211$14683_Y
+  attribute \src "libresoc.v:199206.18-199206.106"
+  wire $reduce_or$libresoc.v:199206$14678_Y
+  attribute \src "libresoc.v:199208.18-199208.90"
+  wire $reduce_or$libresoc.v:199208$14680_Y
+  attribute \src "libresoc.v:199210.17-199210.103"
+  wire $reduce_or$libresoc.v:199210$14682_Y
+  attribute \src "libresoc.v:199212.17-199212.105"
+  wire $reduce_or$libresoc.v:199212$14684_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
   wire width 4 \$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
@@ -418115,77 +418123,77 @@ module \wrpick_XER_xer_ov
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
   wire \t3
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199197$14677
+  cell $not $not$libresoc.v:199205$14677
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$8
-    connect \Y $not$libresoc.v:199197$14677_Y
+    connect \Y $not$libresoc.v:199205$14677_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199199$14679
+  cell $not $not$libresoc.v:199207$14679
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$12
-    connect \Y $not$libresoc.v:199199$14679_Y
+    connect \Y $not$libresoc.v:199207$14679_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
-  cell $not $not$libresoc.v:199201$14681
+  cell $not $not$libresoc.v:199209$14681
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
     connect \A \i
-    connect \Y $not$libresoc.v:199201$14681_Y
+    connect \Y $not$libresoc.v:199209$14681_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199203$14683
+  cell $not $not$libresoc.v:199211$14683
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$4
-    connect \Y $not$libresoc.v:199203$14683_Y
+    connect \Y $not$libresoc.v:199211$14683_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199198$14678
+  cell $reduce_or $reduce_or$libresoc.v:199206$14678
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
     connect \A { \i [2:0] \ni [3] }
-    connect \Y $reduce_or$libresoc.v:199198$14678_Y
+    connect \Y $reduce_or$libresoc.v:199206$14678_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
-  cell $reduce_or $reduce_or$libresoc.v:199200$14680
+  cell $reduce_or $reduce_or$libresoc.v:199208$14680
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $reduce_or$libresoc.v:199200$14680_Y
+    connect \Y $reduce_or$libresoc.v:199208$14680_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199202$14682
+  cell $reduce_or $reduce_or$libresoc.v:199210$14682
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
     connect \A { \i [0] \ni [1] }
-    connect \Y $reduce_or$libresoc.v:199202$14682_Y
+    connect \Y $reduce_or$libresoc.v:199210$14682_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199204$14684
+  cell $reduce_or $reduce_or$libresoc.v:199212$14684
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
     connect \A { \i [1:0] \ni [2] }
-    connect \Y $reduce_or$libresoc.v:199204$14684_Y
-  end
-  connect \$7 $not$libresoc.v:199197$14677_Y
-  connect \$12 $reduce_or$libresoc.v:199198$14678_Y
-  connect \$11 $not$libresoc.v:199199$14679_Y
-  connect \$15 $reduce_or$libresoc.v:199200$14680_Y
-  connect \$1 $not$libresoc.v:199201$14681_Y
-  connect \$4 $reduce_or$libresoc.v:199202$14682_Y
-  connect \$3 $not$libresoc.v:199203$14683_Y
-  connect \$8 $reduce_or$libresoc.v:199204$14684_Y
+    connect \Y $reduce_or$libresoc.v:199212$14684_Y
+  end
+  connect \$7 $not$libresoc.v:199205$14677_Y
+  connect \$12 $reduce_or$libresoc.v:199206$14678_Y
+  connect \$11 $not$libresoc.v:199207$14679_Y
+  connect \$15 $reduce_or$libresoc.v:199208$14680_Y
+  connect \$1 $not$libresoc.v:199209$14681_Y
+  connect \$4 $reduce_or$libresoc.v:199210$14682_Y
+  connect \$3 $not$libresoc.v:199211$14683_Y
+  connect \$8 $reduce_or$libresoc.v:199212$14684_Y
   connect \en_o \$15
   connect \o { \t3 \t2 \t1 \t0 }
   connect \t3 \$11
@@ -418194,27 +418202,27 @@ module \wrpick_XER_xer_ov
   connect \t0 \i [0]
   connect \ni \$1
 end
-attribute \src "libresoc.v:199216.1-199264.10"
+attribute \src "libresoc.v:199224.1-199272.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so"
 attribute \generator "nMigen"
 module \wrpick_XER_xer_so
-  attribute \src "libresoc.v:199249.17-199249.91"
-  wire $not$libresoc.v:199249$14685_Y
-  attribute \src "libresoc.v:199251.18-199251.93"
-  wire $not$libresoc.v:199251$14687_Y
-  attribute \src "libresoc.v:199253.17-199253.89"
-  wire width 4 $not$libresoc.v:199253$14689_Y
-  attribute \src "libresoc.v:199255.17-199255.91"
-  wire $not$libresoc.v:199255$14691_Y
-  attribute \src "libresoc.v:199250.18-199250.106"
-  wire $reduce_or$libresoc.v:199250$14686_Y
-  attribute \src "libresoc.v:199252.18-199252.90"
-  wire $reduce_or$libresoc.v:199252$14688_Y
-  attribute \src "libresoc.v:199254.17-199254.103"
-  wire $reduce_or$libresoc.v:199254$14690_Y
-  attribute \src "libresoc.v:199256.17-199256.105"
-  wire $reduce_or$libresoc.v:199256$14692_Y
+  attribute \src "libresoc.v:199257.17-199257.91"
+  wire $not$libresoc.v:199257$14685_Y
+  attribute \src "libresoc.v:199259.18-199259.93"
+  wire $not$libresoc.v:199259$14687_Y
+  attribute \src "libresoc.v:199261.17-199261.89"
+  wire width 4 $not$libresoc.v:199261$14689_Y
+  attribute \src "libresoc.v:199263.17-199263.91"
+  wire $not$libresoc.v:199263$14691_Y
+  attribute \src "libresoc.v:199258.18-199258.106"
+  wire $reduce_or$libresoc.v:199258$14686_Y
+  attribute \src "libresoc.v:199260.18-199260.90"
+  wire $reduce_or$libresoc.v:199260$14688_Y
+  attribute \src "libresoc.v:199262.17-199262.103"
+  wire $reduce_or$libresoc.v:199262$14690_Y
+  attribute \src "libresoc.v:199264.17-199264.105"
+  wire $reduce_or$libresoc.v:199264$14692_Y
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
   wire width 4 \$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
@@ -418248,77 +418256,77 @@ module \wrpick_XER_xer_so
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
   wire \t3
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199249$14685
+  cell $not $not$libresoc.v:199257$14685
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$8
-    connect \Y $not$libresoc.v:199249$14685_Y
+    connect \Y $not$libresoc.v:199257$14685_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199251$14687
+  cell $not $not$libresoc.v:199259$14687
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$12
-    connect \Y $not$libresoc.v:199251$14687_Y
+    connect \Y $not$libresoc.v:199259$14687_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
-  cell $not $not$libresoc.v:199253$14689
+  cell $not $not$libresoc.v:199261$14689
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
     connect \A \i
-    connect \Y $not$libresoc.v:199253$14689_Y
+    connect \Y $not$libresoc.v:199261$14689_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $not $not$libresoc.v:199255$14691
+  cell $not $not$libresoc.v:199263$14691
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \$4
-    connect \Y $not$libresoc.v:199255$14691_Y
+    connect \Y $not$libresoc.v:199263$14691_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199250$14686
+  cell $reduce_or $reduce_or$libresoc.v:199258$14686
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
     connect \A { \i [2:0] \ni [3] }
-    connect \Y $reduce_or$libresoc.v:199250$14686_Y
+    connect \Y $reduce_or$libresoc.v:199258$14686_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
-  cell $reduce_or $reduce_or$libresoc.v:199252$14688
+  cell $reduce_or $reduce_or$libresoc.v:199260$14688
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $reduce_or$libresoc.v:199252$14688_Y
+    connect \Y $reduce_or$libresoc.v:199260$14688_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199254$14690
+  cell $reduce_or $reduce_or$libresoc.v:199262$14690
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
     connect \A { \i [0] \ni [1] }
-    connect \Y $reduce_or$libresoc.v:199254$14690_Y
+    connect \Y $reduce_or$libresoc.v:199262$14690_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
-  cell $reduce_or $reduce_or$libresoc.v:199256$14692
+  cell $reduce_or $reduce_or$libresoc.v:199264$14692
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
     connect \A { \i [1:0] \ni [2] }
-    connect \Y $reduce_or$libresoc.v:199256$14692_Y
-  end
-  connect \$7 $not$libresoc.v:199249$14685_Y
-  connect \$12 $reduce_or$libresoc.v:199250$14686_Y
-  connect \$11 $not$libresoc.v:199251$14687_Y
-  connect \$15 $reduce_or$libresoc.v:199252$14688_Y
-  connect \$1 $not$libresoc.v:199253$14689_Y
-  connect \$4 $reduce_or$libresoc.v:199254$14690_Y
-  connect \$3 $not$libresoc.v:199255$14691_Y
-  connect \$8 $reduce_or$libresoc.v:199256$14692_Y
+    connect \Y $reduce_or$libresoc.v:199264$14692_Y
+  end
+  connect \$7 $not$libresoc.v:199257$14685_Y
+  connect \$12 $reduce_or$libresoc.v:199258$14686_Y
+  connect \$11 $not$libresoc.v:199259$14687_Y
+  connect \$15 $reduce_or$libresoc.v:199260$14688_Y
+  connect \$1 $not$libresoc.v:199261$14689_Y
+  connect \$4 $reduce_or$libresoc.v:199262$14690_Y
+  connect \$3 $not$libresoc.v:199263$14691_Y
+  connect \$8 $reduce_or$libresoc.v:199264$14692_Y
   connect \en_o \$15
   connect \o { \t3 \t2 \t1 \t0 }
   connect \t3 \$11
@@ -418327,67 +418335,67 @@ module \wrpick_XER_xer_so
   connect \t0 \i [0]
   connect \ni \$1
 end
-attribute \src "libresoc.v:199268.1-199588.10"
+attribute \src "libresoc.v:199276.1-199596.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.core.xer"
 attribute \generator "nMigen"
 module \xer
-  attribute \src "libresoc.v:199269.7-199269.20"
+  attribute \src "libresoc.v:199277.7-199277.20"
   wire $0\initial[0:0]
-  attribute \src "libresoc.v:199548.3-199556.6"
+  attribute \src "libresoc.v:199556.3-199564.6"
   wire width 3 $0\ren_delay$11$next[2:0]$14716
-  attribute \src "libresoc.v:199446.3-199447.43"
+  attribute \src "libresoc.v:199454.3-199455.43"
   wire width 3 $0\ren_delay$11[2:0]$14705
-  attribute \src "libresoc.v:199405.13-199405.34"
+  attribute \src "libresoc.v:199413.13-199413.34"
   wire width 3 $0\ren_delay$11[2:0]$14722
-  attribute \src "libresoc.v:199510.3-199518.6"
+  attribute \src "libresoc.v:199518.3-199526.6"
   wire width 3 $0\ren_delay$18$next[2:0]$14708
-  attribute \src "libresoc.v:199444.3-199445.43"
+  attribute \src "libresoc.v:199452.3-199453.43"
   wire width 3 $0\ren_delay$18[2:0]$14703
-  attribute \src "libresoc.v:199409.13-199409.34"
+  attribute \src "libresoc.v:199417.13-199417.34"
   wire width 3 $0\ren_delay$18[2:0]$14724
-  attribute \src "libresoc.v:199529.3-199537.6"
+  attribute \src "libresoc.v:199537.3-199545.6"
   wire width 3 $0\ren_delay$next[2:0]$14712
-  attribute \src "libresoc.v:199448.3-199449.35"
+  attribute \src "libresoc.v:199456.3-199457.35"
   wire width 3 $0\ren_delay[2:0]
-  attribute \src "libresoc.v:199538.3-199547.6"
+  attribute \src "libresoc.v:199546.3-199555.6"
   wire width 2 $0\src1__data_o[1:0]
-  attribute \src "libresoc.v:199557.3-199566.6"
+  attribute \src "libresoc.v:199565.3-199574.6"
   wire width 2 $0\src2__data_o[1:0]
-  attribute \src "libresoc.v:199519.3-199528.6"
+  attribute \src "libresoc.v:199527.3-199536.6"
   wire width 2 $0\src3__data_o[1:0]
-  attribute \src "libresoc.v:199548.3-199556.6"
+  attribute \src "libresoc.v:199556.3-199564.6"
   wire width 3 $1\ren_delay$11$next[2:0]$14717
-  attribute \src "libresoc.v:199510.3-199518.6"
+  attribute \src "libresoc.v:199518.3-199526.6"
   wire width 3 $1\ren_delay$18$next[2:0]$14709
-  attribute \src "libresoc.v:199529.3-199537.6"
+  attribute \src "libresoc.v:199537.3-199545.6"
   wire width 3 $1\ren_delay$next[2:0]$14713
-  attribute \src "libresoc.v:199403.13-199403.29"
+  attribute \src "libresoc.v:199411.13-199411.29"
   wire width 3 $1\ren_delay[2:0]
-  attribute \src "libresoc.v:199538.3-199547.6"
+  attribute \src "libresoc.v:199546.3-199555.6"
   wire width 2 $1\src1__data_o[1:0]
-  attribute \src "libresoc.v:199557.3-199566.6"
+  attribute \src "libresoc.v:199565.3-199574.6"
   wire width 2 $1\src2__data_o[1:0]
-  attribute \src "libresoc.v:199519.3-199528.6"
+  attribute \src "libresoc.v:199527.3-199536.6"
   wire width 2 $1\src3__data_o[1:0]
-  attribute \src "libresoc.v:199435.17-199435.109"
-  wire width 2 $or$libresoc.v:199435$14693_Y
-  attribute \src "libresoc.v:199437.18-199437.126"
-  wire width 2 $or$libresoc.v:199437$14695_Y
-  attribute \src "libresoc.v:199438.18-199438.111"
-  wire width 2 $or$libresoc.v:199438$14696_Y
-  attribute \src "libresoc.v:199440.18-199440.126"
-  wire width 2 $or$libresoc.v:199440$14698_Y
-  attribute \src "libresoc.v:199441.18-199441.111"
-  wire width 2 $or$libresoc.v:199441$14699_Y
-  attribute \src "libresoc.v:199443.17-199443.125"
-  wire width 2 $or$libresoc.v:199443$14701_Y
-  attribute \src "libresoc.v:199436.18-199436.100"
-  wire $reduce_or$libresoc.v:199436$14694_Y
-  attribute \src "libresoc.v:199439.18-199439.100"
-  wire $reduce_or$libresoc.v:199439$14697_Y
-  attribute \src "libresoc.v:199442.17-199442.95"
-  wire $reduce_or$libresoc.v:199442$14700_Y
+  attribute \src "libresoc.v:199443.17-199443.109"
+  wire width 2 $or$libresoc.v:199443$14693_Y
+  attribute \src "libresoc.v:199445.18-199445.126"
+  wire width 2 $or$libresoc.v:199445$14695_Y
+  attribute \src "libresoc.v:199446.18-199446.111"
+  wire width 2 $or$libresoc.v:199446$14696_Y
+  attribute \src "libresoc.v:199448.18-199448.126"
+  wire width 2 $or$libresoc.v:199448$14698_Y
+  attribute \src "libresoc.v:199449.18-199449.111"
+  wire width 2 $or$libresoc.v:199449$14699_Y
+  attribute \src "libresoc.v:199451.17-199451.125"
+  wire width 2 $or$libresoc.v:199451$14701_Y
+  attribute \src "libresoc.v:199444.18-199444.100"
+  wire $reduce_or$libresoc.v:199444$14694_Y
+  attribute \src "libresoc.v:199447.18-199447.100"
+  wire $reduce_or$libresoc.v:199447$14697_Y
+  attribute \src "libresoc.v:199450.17-199450.95"
+  wire $reduce_or$libresoc.v:199450$14700_Y
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
   wire \$12
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
@@ -418406,9 +418414,9 @@ module \xer
   wire width 2 \$7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
   wire width 2 \$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 16 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:448"
   wire input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 2 input 10 \data_i
@@ -418424,7 +418432,7 @@ module \xer
   wire width 6 \full_wr__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 3 \full_wr__wen
-  attribute \src "libresoc.v:199269.7-199269.15"
+  attribute \src "libresoc.v:199277.7-199277.15"
   wire \initial
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 2 \reg_0_dest10__data_i
@@ -418553,7 +418561,7 @@ module \xer
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
   wire width 3 input 15 \wen$4
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
-  cell $or $or$libresoc.v:199435$14693
+  cell $or $or$libresoc.v:199443$14693
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -418561,10 +418569,10 @@ module \xer
     parameter \Y_WIDTH 2
     connect \A \reg_0_src10__data_o
     connect \B \$7
-    connect \Y $or$libresoc.v:199435$14693_Y
+    connect \Y $or$libresoc.v:199443$14693_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
-  cell $or $or$libresoc.v:199437$14695
+  cell $or $or$libresoc.v:199445$14695
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -418572,10 +418580,10 @@ module \xer
     parameter \Y_WIDTH 2
     connect \A \reg_1_src21__data_o
     connect \B \reg_2_src22__data_o
-    connect \Y $or$libresoc.v:199437$14695_Y
+    connect \Y $or$libresoc.v:199445$14695_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
-  cell $or $or$libresoc.v:199438$14696
+  cell $or $or$libresoc.v:199446$14696
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -418583,10 +418591,10 @@ module \xer
     parameter \Y_WIDTH 2
     connect \A \reg_0_src20__data_o
     connect \B \$14
-    connect \Y $or$libresoc.v:199438$14696_Y
+    connect \Y $or$libresoc.v:199446$14696_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
-  cell $or $or$libresoc.v:199440$14698
+  cell $or $or$libresoc.v:199448$14698
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -418594,10 +418602,10 @@ module \xer
     parameter \Y_WIDTH 2
     connect \A \reg_1_src31__data_o
     connect \B \reg_2_src32__data_o
-    connect \Y $or$libresoc.v:199440$14698_Y
+    connect \Y $or$libresoc.v:199448$14698_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
-  cell $or $or$libresoc.v:199441$14699
+  cell $or $or$libresoc.v:199449$14699
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -418605,10 +418613,10 @@ module \xer
     parameter \Y_WIDTH 2
     connect \A \reg_0_src30__data_o
     connect \B \$21
-    connect \Y $or$libresoc.v:199441$14699_Y
+    connect \Y $or$libresoc.v:199449$14699_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
-  cell $or $or$libresoc.v:199443$14701
+  cell $or $or$libresoc.v:199451$14701
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -418616,34 +418624,34 @@ module \xer
     parameter \Y_WIDTH 2
     connect \A \reg_1_src11__data_o
     connect \B \reg_2_src12__data_o
-    connect \Y $or$libresoc.v:199443$14701_Y
+    connect \Y $or$libresoc.v:199451$14701_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  cell $reduce_or $reduce_or$libresoc.v:199436$14694
+  cell $reduce_or $reduce_or$libresoc.v:199444$14694
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
     connect \A \ren_delay$11
-    connect \Y $reduce_or$libresoc.v:199436$14694_Y
+    connect \Y $reduce_or$libresoc.v:199444$14694_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  cell $reduce_or $reduce_or$libresoc.v:199439$14697
+  cell $reduce_or $reduce_or$libresoc.v:199447$14697
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
     connect \A \ren_delay$18
-    connect \Y $reduce_or$libresoc.v:199439$14697_Y
+    connect \Y $reduce_or$libresoc.v:199447$14697_Y
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  cell $reduce_or $reduce_or$libresoc.v:199442$14700
+  cell $reduce_or $reduce_or$libresoc.v:199450$14700
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
     connect \A \ren_delay
-    connect \Y $reduce_or$libresoc.v:199442$14700_Y
+    connect \Y $reduce_or$libresoc.v:199450$14700_Y
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:199450.15-199469.4"
+  attribute \src "libresoc.v:199458.15-199477.4"
   cell \reg_0$132 \reg_0
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -418665,7 +418673,7 @@ module \xer
     connect \w0__wen \reg_0_w0__wen
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:199470.15-199489.4"
+  attribute \src "libresoc.v:199478.15-199497.4"
   cell \reg_1$133 \reg_1
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -418687,7 +418695,7 @@ module \xer
     connect \w1__wen \reg_1_w1__wen
   end
   attribute \module_not_derived 1
-  attribute \src "libresoc.v:199490.15-199509.4"
+  attribute \src "libresoc.v:199498.15-199517.4"
   cell \reg_2$134 \reg_2
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -418708,67 +418716,67 @@ module \xer
     connect \w2__data_i \reg_2_w2__data_i
     connect \w2__wen \reg_2_w2__wen
   end
-  attribute \src "libresoc.v:199269.7-199269.20"
-  process $proc$libresoc.v:199269$14719
+  attribute \src "libresoc.v:199277.7-199277.20"
+  process $proc$libresoc.v:199277$14719
     assign { } { }
     assign $0\initial[0:0] 1'0
     sync always
       update \initial $0\initial[0:0]
     sync init
   end
-  attribute \src "libresoc.v:199403.13-199403.29"
-  process $proc$libresoc.v:199403$14720
+  attribute \src "libresoc.v:199411.13-199411.29"
+  process $proc$libresoc.v:199411$14720
     assign { } { }
     assign $1\ren_delay[2:0] 3'000
     sync always
     sync init
       update \ren_delay $1\ren_delay[2:0]
   end
-  attribute \src "libresoc.v:199405.13-199405.34"
-  process $proc$libresoc.v:199405$14721
+  attribute \src "libresoc.v:199413.13-199413.34"
+  process $proc$libresoc.v:199413$14721
     assign { } { }
     assign $0\ren_delay$11[2:0]$14722 3'000
     sync always
     sync init
       update \ren_delay$11 $0\ren_delay$11[2:0]$14722
   end
-  attribute \src "libresoc.v:199409.13-199409.34"
-  process $proc$libresoc.v:199409$14723
+  attribute \src "libresoc.v:199417.13-199417.34"
+  process $proc$libresoc.v:199417$14723
     assign { } { }
     assign $0\ren_delay$18[2:0]$14724 3'000
     sync always
     sync init
       update \ren_delay$18 $0\ren_delay$18[2:0]$14724
   end
-  attribute \src "libresoc.v:199444.3-199445.43"
-  process $proc$libresoc.v:199444$14702
+  attribute \src "libresoc.v:199452.3-199453.43"
+  process $proc$libresoc.v:199452$14702
     assign { } { }
     assign $0\ren_delay$18[2:0]$14703 \ren_delay$18$next
     sync posedge \coresync_clk
       update \ren_delay$18 $0\ren_delay$18[2:0]$14703
   end
-  attribute \src "libresoc.v:199446.3-199447.43"
-  process $proc$libresoc.v:199446$14704
+  attribute \src "libresoc.v:199454.3-199455.43"
+  process $proc$libresoc.v:199454$14704
     assign { } { }
     assign $0\ren_delay$11[2:0]$14705 \ren_delay$11$next
     sync posedge \coresync_clk
       update \ren_delay$11 $0\ren_delay$11[2:0]$14705
   end
-  attribute \src "libresoc.v:199448.3-199449.35"
-  process $proc$libresoc.v:199448$14706
+  attribute \src "libresoc.v:199456.3-199457.35"
+  process $proc$libresoc.v:199456$14706
     assign { } { }
     assign $0\ren_delay[2:0] \ren_delay$next
     sync posedge \coresync_clk
       update \ren_delay $0\ren_delay[2:0]
   end
-  attribute \src "libresoc.v:199510.3-199518.6"
-  process $proc$libresoc.v:199510$14707
+  attribute \src "libresoc.v:199518.3-199526.6"
+  process $proc$libresoc.v:199518$14707
     assign { } { }
     assign { } { }
     assign $0\ren_delay$18$next[2:0]$14708 $1\ren_delay$18$next[2:0]$14709
-    attribute \src "libresoc.v:199511.5-199511.29"
+    attribute \src "libresoc.v:199519.5-199519.29"
     switch \initial
-      attribute \src "libresoc.v:199511.9-199511.17"
+      attribute \src "libresoc.v:199519.9-199519.17"
       case 1'1
       case 
     end
@@ -418784,14 +418792,14 @@ module \xer
     sync always
       update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14708
   end
-  attribute \src "libresoc.v:199519.3-199528.6"
-  process $proc$libresoc.v:199519$14710
+  attribute \src "libresoc.v:199527.3-199536.6"
+  process $proc$libresoc.v:199527$14710
     assign { } { }
     assign { } { }
     assign $0\src3__data_o[1:0] $1\src3__data_o[1:0]
-    attribute \src "libresoc.v:199520.5-199520.29"
+    attribute \src "libresoc.v:199528.5-199528.29"
     switch \initial
-      attribute \src "libresoc.v:199520.9-199520.17"
+      attribute \src "libresoc.v:199528.9-199528.17"
       case 1'1
       case 
     end
@@ -418807,14 +418815,14 @@ module \xer
     sync always
       update \src3__data_o $0\src3__data_o[1:0]
   end
-  attribute \src "libresoc.v:199529.3-199537.6"
-  process $proc$libresoc.v:199529$14711
+  attribute \src "libresoc.v:199537.3-199545.6"
+  process $proc$libresoc.v:199537$14711
     assign { } { }
     assign { } { }
     assign $0\ren_delay$next[2:0]$14712 $1\ren_delay$next[2:0]$14713
-    attribute \src "libresoc.v:199530.5-199530.29"
+    attribute \src "libresoc.v:199538.5-199538.29"
     switch \initial
-      attribute \src "libresoc.v:199530.9-199530.17"
+      attribute \src "libresoc.v:199538.9-199538.17"
       case 1'1
       case 
     end
@@ -418830,14 +418838,14 @@ module \xer
     sync always
       update \ren_delay$next $0\ren_delay$next[2:0]$14712
   end
-  attribute \src "libresoc.v:199538.3-199547.6"
-  process $proc$libresoc.v:199538$14714
+  attribute \src "libresoc.v:199546.3-199555.6"
+  process $proc$libresoc.v:199546$14714
     assign { } { }
     assign { } { }
     assign $0\src1__data_o[1:0] $1\src1__data_o[1:0]
-    attribute \src "libresoc.v:199539.5-199539.29"
+    attribute \src "libresoc.v:199547.5-199547.29"
     switch \initial
-      attribute \src "libresoc.v:199539.9-199539.17"
+      attribute \src "libresoc.v:199547.9-199547.17"
       case 1'1
       case 
     end
@@ -418853,14 +418861,14 @@ module \xer
     sync always
       update \src1__data_o $0\src1__data_o[1:0]
   end
-  attribute \src "libresoc.v:199548.3-199556.6"
-  process $proc$libresoc.v:199548$14715
+  attribute \src "libresoc.v:199556.3-199564.6"
+  process $proc$libresoc.v:199556$14715
     assign { } { }
     assign { } { }
     assign $0\ren_delay$11$next[2:0]$14716 $1\ren_delay$11$next[2:0]$14717
-    attribute \src "libresoc.v:199549.5-199549.29"
+    attribute \src "libresoc.v:199557.5-199557.29"
     switch \initial
-      attribute \src "libresoc.v:199549.9-199549.17"
+      attribute \src "libresoc.v:199557.9-199557.17"
       case 1'1
       case 
     end
@@ -418876,14 +418884,14 @@ module \xer
     sync always
       update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14716
   end
-  attribute \src "libresoc.v:199557.3-199566.6"
-  process $proc$libresoc.v:199557$14718
+  attribute \src "libresoc.v:199565.3-199574.6"
+  process $proc$libresoc.v:199565$14718
     assign { } { }
     assign { } { }
     assign $0\src2__data_o[1:0] $1\src2__data_o[1:0]
-    attribute \src "libresoc.v:199558.5-199558.29"
+    attribute \src "libresoc.v:199566.5-199566.29"
     switch \initial
-      attribute \src "libresoc.v:199558.9-199558.17"
+      attribute \src "libresoc.v:199566.9-199566.17"
       case 1'1
       case 
     end
@@ -418899,15 +418907,15 @@ module \xer
     sync always
       update \src2__data_o $0\src2__data_o[1:0]
   end
-  connect \$9 $or$libresoc.v:199435$14693_Y
-  connect \$12 $reduce_or$libresoc.v:199436$14694_Y
-  connect \$14 $or$libresoc.v:199437$14695_Y
-  connect \$16 $or$libresoc.v:199438$14696_Y
-  connect \$19 $reduce_or$libresoc.v:199439$14697_Y
-  connect \$21 $or$libresoc.v:199440$14698_Y
-  connect \$23 $or$libresoc.v:199441$14699_Y
-  connect \$5 $reduce_or$libresoc.v:199442$14700_Y
-  connect \$7 $or$libresoc.v:199443$14701_Y
+  connect \$9 $or$libresoc.v:199443$14693_Y
+  connect \$12 $reduce_or$libresoc.v:199444$14694_Y
+  connect \$14 $or$libresoc.v:199445$14695_Y
+  connect \$16 $or$libresoc.v:199446$14696_Y
+  connect \$19 $reduce_or$libresoc.v:199447$14697_Y
+  connect \$21 $or$libresoc.v:199448$14698_Y
+  connect \$23 $or$libresoc.v:199449$14699_Y
+  connect \$5 $reduce_or$libresoc.v:199450$14700_Y
+  connect \$7 $or$libresoc.v:199451$14701_Y
   connect \full_wr__data_i 6'000000
   connect \full_wr__wen 3'000
   connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000
@@ -418930,153 +418938,153 @@ module \xer
   connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
   connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
 end
-attribute \src "libresoc.v:199592.1-199906.10"
+attribute \src "libresoc.v:199600.1-199914.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.xics_icp"
 attribute \generator "nMigen"
 module \xics_icp
-  attribute \src "libresoc.v:199770.3-199798.6"
+  attribute \src "libresoc.v:199778.3-199806.6"
   wire width 32 $0\be_out[31:0]
-  attribute \src "libresoc.v:199821.3-199829.6"
+  attribute \src "libresoc.v:199829.3-199837.6"
   wire $0\core_irq_o$next[0:0]$14760
-  attribute \src "libresoc.v:199712.3-199713.37"
+  attribute \src "libresoc.v:199720.3-199721.37"
   wire $0\core_irq_o[0:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire width 8 $0\cppr$10[7:0]$14764
-  attribute \src "libresoc.v:199726.3-199741.6"
+  attribute \src "libresoc.v:199734.3-199749.6"
   wire width 8 $0\cppr$next[7:0]$14743
-  attribute \src "libresoc.v:199716.3-199717.25"
+  attribute \src "libresoc.v:199724.3-199725.25"
   wire width 8 $0\cppr[7:0]
-  attribute \src "libresoc.v:199830.3-199839.6"
+  attribute \src "libresoc.v:199838.3-199847.6"
   wire width 32 $0\icp_wb__dat_r[31:0]
-  attribute \src "libresoc.v:199593.7-199593.20"
+  attribute \src "libresoc.v:199601.7-199601.20"
   wire $0\initial[0:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire $0\irq$12[0:0]$14765
-  attribute \src "libresoc.v:199726.3-199741.6"
+  attribute \src "libresoc.v:199734.3-199749.6"
   wire $0\irq$next[0:0]$14744
-  attribute \src "libresoc.v:199720.3-199721.23"
+  attribute \src "libresoc.v:199728.3-199729.23"
   wire $0\irq[0:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire width 8 $0\mfrr$11[7:0]$14766
-  attribute \src "libresoc.v:199726.3-199741.6"
+  attribute \src "libresoc.v:199734.3-199749.6"
   wire width 8 $0\mfrr$next[7:0]$14745
-  attribute \src "libresoc.v:199718.3-199719.25"
+  attribute \src "libresoc.v:199726.3-199727.25"
   wire width 8 $0\mfrr[7:0]
-  attribute \src "libresoc.v:199809.3-199820.6"
+  attribute \src "libresoc.v:199817.3-199828.6"
   wire width 8 $0\min_pri[7:0]
-  attribute \src "libresoc.v:199799.3-199808.6"
+  attribute \src "libresoc.v:199807.3-199816.6"
   wire width 8 $0\pending_priority[7:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire $0\wb_ack$14[0:0]$14767
-  attribute \src "libresoc.v:199726.3-199741.6"
+  attribute \src "libresoc.v:199734.3-199749.6"
   wire $0\wb_ack$next[0:0]$14746
-  attribute \src "libresoc.v:199724.3-199725.29"
+  attribute \src "libresoc.v:199732.3-199733.29"
   wire $0\wb_ack[0:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire width 32 $0\wb_rd_data$13[31:0]$14768
-  attribute \src "libresoc.v:199726.3-199741.6"
+  attribute \src "libresoc.v:199734.3-199749.6"
   wire width 32 $0\wb_rd_data$next[31:0]$14747
-  attribute \src "libresoc.v:199722.3-199723.37"
+  attribute \src "libresoc.v:199730.3-199731.37"
   wire width 32 $0\wb_rd_data[31:0]
-  attribute \src "libresoc.v:199742.3-199769.6"
+  attribute \src "libresoc.v:199750.3-199777.6"
   wire $0\xirr_accept_rd[0:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire width 24 $0\xisr$9[23:0]$14769
-  attribute \src "libresoc.v:199726.3-199741.6"
+  attribute \src "libresoc.v:199734.3-199749.6"
   wire width 24 $0\xisr$next[23:0]$14748
-  attribute \src "libresoc.v:199714.3-199715.25"
+  attribute \src "libresoc.v:199722.3-199723.25"
   wire width 24 $0\xisr[23:0]
-  attribute \src "libresoc.v:199770.3-199798.6"
+  attribute \src "libresoc.v:199778.3-199806.6"
   wire width 32 $1\be_out[31:0]
-  attribute \src "libresoc.v:199821.3-199829.6"
+  attribute \src "libresoc.v:199829.3-199837.6"
   wire $1\core_irq_o$next[0:0]$14761
-  attribute \src "libresoc.v:199622.7-199622.24"
+  attribute \src "libresoc.v:199630.7-199630.24"
   wire $1\core_irq_o[0:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire width 8 $1\cppr$10[7:0]$14770
-  attribute \src "libresoc.v:199726.3-199741.6"
+  attribute \src "libresoc.v:199734.3-199749.6"
   wire width 8 $1\cppr$next[7:0]$14749
-  attribute \src "libresoc.v:199626.13-199626.25"
+  attribute \src "libresoc.v:199634.13-199634.25"
   wire width 8 $1\cppr[7:0]
-  attribute \src "libresoc.v:199830.3-199839.6"
+  attribute \src "libresoc.v:199838.3-199847.6"
   wire width 32 $1\icp_wb__dat_r[31:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire $1\irq$12[0:0]$14780
-  attribute \src "libresoc.v:199726.3-199741.6"
+  attribute \src "libresoc.v:199734.3-199749.6"
   wire $1\irq$next[0:0]$14750
-  attribute \src "libresoc.v:199655.7-199655.17"
+  attribute \src "libresoc.v:199663.7-199663.17"
   wire $1\irq[0:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire width 8 $1\mfrr$11[7:0]$14771
-  attribute \src "libresoc.v:199726.3-199741.6"
+  attribute \src "libresoc.v:199734.3-199749.6"
   wire width 8 $1\mfrr$next[7:0]$14751
-  attribute \src "libresoc.v:199663.13-199663.25"
+  attribute \src "libresoc.v:199671.13-199671.25"
   wire width 8 $1\mfrr[7:0]
-  attribute \src "libresoc.v:199809.3-199820.6"
+  attribute \src "libresoc.v:199817.3-199828.6"
   wire width 8 $1\min_pri[7:0]
-  attribute \src "libresoc.v:199799.3-199808.6"
+  attribute \src "libresoc.v:199807.3-199816.6"
   wire width 8 $1\pending_priority[7:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire $1\wb_ack$14[0:0]$14772
-  attribute \src "libresoc.v:199726.3-199741.6"
+  attribute \src "libresoc.v:199734.3-199749.6"
   wire $1\wb_ack$next[0:0]$14752
-  attribute \src "libresoc.v:199677.7-199677.20"
+  attribute \src "libresoc.v:199685.7-199685.20"
   wire $1\wb_ack[0:0]
-  attribute \src "libresoc.v:199726.3-199741.6"
+  attribute \src "libresoc.v:199734.3-199749.6"
   wire width 32 $1\wb_rd_data$next[31:0]$14753
-  attribute \src "libresoc.v:199685.14-199685.32"
+  attribute \src "libresoc.v:199693.14-199693.32"
   wire width 32 $1\wb_rd_data[31:0]
-  attribute \src "libresoc.v:199742.3-199769.6"
+  attribute \src "libresoc.v:199750.3-199777.6"
   wire $1\xirr_accept_rd[0:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire width 24 $1\xisr$9[23:0]$14777
-  attribute \src "libresoc.v:199726.3-199741.6"
+  attribute \src "libresoc.v:199734.3-199749.6"
   wire width 24 $1\xisr$next[23:0]$14754
-  attribute \src "libresoc.v:199695.14-199695.31"
+  attribute \src "libresoc.v:199703.14-199703.31"
   wire width 24 $1\xisr[23:0]
-  attribute \src "libresoc.v:199770.3-199798.6"
+  attribute \src "libresoc.v:199778.3-199806.6"
   wire width 32 $2\be_out[31:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire width 8 $2\cppr$10[7:0]$14773
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire width 8 $2\mfrr$11[7:0]$14774
-  attribute \src "libresoc.v:199742.3-199769.6"
+  attribute \src "libresoc.v:199750.3-199777.6"
   wire $2\xirr_accept_rd[0:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire width 24 $2\xisr$9[23:0]$14778
-  attribute \src "libresoc.v:199770.3-199798.6"
+  attribute \src "libresoc.v:199778.3-199806.6"
   wire width 32 $3\be_out[31:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire width 8 $3\cppr$10[7:0]$14775
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire width 8 $3\mfrr$11[7:0]$14776
-  attribute \src "libresoc.v:199742.3-199769.6"
+  attribute \src "libresoc.v:199750.3-199777.6"
   wire $3\xirr_accept_rd[0:0]
-  attribute \src "libresoc.v:199840.3-199902.6"
+  attribute \src "libresoc.v:199848.3-199910.6"
   wire width 8 $4\cppr$10[7:0]$14779
-  attribute \src "libresoc.v:199742.3-199769.6"
+  attribute \src "libresoc.v:199750.3-199777.6"
   wire $4\xirr_accept_rd[0:0]
-  attribute \src "libresoc.v:199702.18-199702.116"
-  wire $and$libresoc.v:199702$14725_Y
-  attribute \src "libresoc.v:199706.18-199706.116"
-  wire $and$libresoc.v:199706$14729_Y
-  attribute \src "libresoc.v:199708.18-199708.116"
-  wire $and$libresoc.v:199708$14731_Y
-  attribute \src "libresoc.v:199711.17-199711.109"
-  wire $and$libresoc.v:199711$14734_Y
-  attribute \src "libresoc.v:199707.18-199707.110"
-  wire $eq$libresoc.v:199707$14730_Y
-  attribute \src "libresoc.v:199704.18-199704.114"
-  wire $lt$libresoc.v:199704$14727_Y
-  attribute \src "libresoc.v:199705.18-199705.109"
-  wire $lt$libresoc.v:199705$14728_Y
-  attribute \src "libresoc.v:199710.18-199710.114"
-  wire $lt$libresoc.v:199710$14733_Y
-  attribute \src "libresoc.v:199703.18-199703.109"
-  wire $ne$libresoc.v:199703$14726_Y
-  attribute \src "libresoc.v:199709.18-199709.109"
-  wire $ne$libresoc.v:199709$14732_Y
+  attribute \src "libresoc.v:199710.18-199710.116"
+  wire $and$libresoc.v:199710$14725_Y
+  attribute \src "libresoc.v:199714.18-199714.116"
+  wire $and$libresoc.v:199714$14729_Y
+  attribute \src "libresoc.v:199716.18-199716.116"
+  wire $and$libresoc.v:199716$14731_Y
+  attribute \src "libresoc.v:199719.17-199719.109"
+  wire $and$libresoc.v:199719$14734_Y
+  attribute \src "libresoc.v:199715.18-199715.110"
+  wire $eq$libresoc.v:199715$14730_Y
+  attribute \src "libresoc.v:199712.18-199712.114"
+  wire $lt$libresoc.v:199712$14727_Y
+  attribute \src "libresoc.v:199713.18-199713.109"
+  wire $lt$libresoc.v:199713$14728_Y
+  attribute \src "libresoc.v:199718.18-199718.114"
+  wire $lt$libresoc.v:199718$14733_Y
+  attribute \src "libresoc.v:199711.18-199711.109"
+  wire $ne$libresoc.v:199711$14726_Y
+  attribute \src "libresoc.v:199717.18-199717.109"
+  wire $ne$libresoc.v:199717$14732_Y
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
   wire \$15
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
@@ -419101,7 +419109,7 @@ module \xics_icp
   wire width 32 \be_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104"
   wire width 32 \be_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 13 \clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
   wire output 4 \core_irq_o
@@ -419135,7 +419143,7 @@ module \xics_icp
   wire width 8 input 3 \ics_i_pri
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
   wire width 4 input 2 \ics_i_src
-  attribute \src "libresoc.v:199593.7-199593.15"
+  attribute \src "libresoc.v:199601.7-199601.15"
   wire \initial
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64"
   wire \irq
@@ -419157,7 +419165,7 @@ module \xics_icp
   wire width 8 \min_pri
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106"
   wire width 8 \pending_priority
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 1 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66"
   wire \wb_ack
@@ -419186,7 +419194,7 @@ module \xics_icp
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61"
   wire width 24 \xisr$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
-  cell $and $and$libresoc.v:199702$14725
+  cell $and $and$libresoc.v:199710$14725
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -419194,10 +419202,10 @@ module \xics_icp
     parameter \Y_WIDTH 1
     connect \A \icp_wb__cyc
     connect \B \icp_wb__stb
-    connect \Y $and$libresoc.v:199702$14725_Y
+    connect \Y $and$libresoc.v:199710$14725_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
-  cell $and $and$libresoc.v:199706$14729
+  cell $and $and$libresoc.v:199714$14729
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -419205,10 +419213,10 @@ module \xics_icp
     parameter \Y_WIDTH 1
     connect \A \icp_wb__cyc
     connect \B \icp_wb__stb
-    connect \Y $and$libresoc.v:199706$14729_Y
+    connect \Y $and$libresoc.v:199714$14729_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
-  cell $and $and$libresoc.v:199708$14731
+  cell $and $and$libresoc.v:199716$14731
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -419216,10 +419224,10 @@ module \xics_icp
     parameter \Y_WIDTH 1
     connect \A \icp_wb__cyc
     connect \B \icp_wb__stb
-    connect \Y $and$libresoc.v:199708$14731_Y
+    connect \Y $and$libresoc.v:199716$14731_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96"
-  cell $and $and$libresoc.v:199711$14734
+  cell $and $and$libresoc.v:199719$14734
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -419227,10 +419235,10 @@ module \xics_icp
     parameter \Y_WIDTH 1
     connect \A \wb_ack
     connect \B \icp_wb__cyc
-    connect \Y $and$libresoc.v:199711$14734_Y
+    connect \Y $and$libresoc.v:199719$14734_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162"
-  cell $eq $eq$libresoc.v:199707$14730
+  cell $eq $eq$libresoc.v:199715$14730
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -419238,10 +419246,10 @@ module \xics_icp
     parameter \Y_WIDTH 1
     connect \A \icp_wb__sel
     connect \B 4'1111
-    connect \Y $eq$libresoc.v:199707$14730_Y
+    connect \Y $eq$libresoc.v:199715$14730_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
-  cell $lt $lt$libresoc.v:199704$14727
+  cell $lt $lt$libresoc.v:199712$14727
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -419249,10 +419257,10 @@ module \xics_icp
     parameter \Y_WIDTH 1
     connect \A \mfrr
     connect \B \pending_priority
-    connect \Y $lt$libresoc.v:199704$14727_Y
+    connect \Y $lt$libresoc.v:199712$14727_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
-  cell $lt $lt$libresoc.v:199705$14728
+  cell $lt $lt$libresoc.v:199713$14728
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -419260,10 +419268,10 @@ module \xics_icp
     parameter \Y_WIDTH 1
     connect \A \min_pri
     connect \B \cppr$10
-    connect \Y $lt$libresoc.v:199705$14728_Y
+    connect \Y $lt$libresoc.v:199713$14728_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
-  cell $lt $lt$libresoc.v:199710$14733
+  cell $lt $lt$libresoc.v:199718$14733
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -419271,10 +419279,10 @@ module \xics_icp
     parameter \Y_WIDTH 1
     connect \A \mfrr
     connect \B \pending_priority
-    connect \Y $lt$libresoc.v:199710$14733_Y
+    connect \Y $lt$libresoc.v:199718$14733_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
-  cell $ne $ne$libresoc.v:199703$14726
+  cell $ne $ne$libresoc.v:199711$14726
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -419282,10 +419290,10 @@ module \xics_icp
     parameter \Y_WIDTH 1
     connect \A \ics_i_pri
     connect \B 8'11111111
-    connect \Y $ne$libresoc.v:199703$14726_Y
+    connect \Y $ne$libresoc.v:199711$14726_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
-  cell $ne $ne$libresoc.v:199709$14732
+  cell $ne $ne$libresoc.v:199717$14732
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -419293,123 +419301,123 @@ module \xics_icp
     parameter \Y_WIDTH 1
     connect \A \ics_i_pri
     connect \B 8'11111111
-    connect \Y $ne$libresoc.v:199709$14732_Y
+    connect \Y $ne$libresoc.v:199717$14732_Y
   end
-  attribute \src "libresoc.v:199593.7-199593.20"
-  process $proc$libresoc.v:199593$14781
+  attribute \src "libresoc.v:199601.7-199601.20"
+  process $proc$libresoc.v:199601$14781
     assign { } { }
     assign $0\initial[0:0] 1'0
     sync always
       update \initial $0\initial[0:0]
     sync init
   end
-  attribute \src "libresoc.v:199622.7-199622.24"
-  process $proc$libresoc.v:199622$14782
+  attribute \src "libresoc.v:199630.7-199630.24"
+  process $proc$libresoc.v:199630$14782
     assign { } { }
     assign $1\core_irq_o[0:0] 1'0
     sync always
     sync init
       update \core_irq_o $1\core_irq_o[0:0]
   end
-  attribute \src "libresoc.v:199626.13-199626.25"
-  process $proc$libresoc.v:199626$14783
+  attribute \src "libresoc.v:199634.13-199634.25"
+  process $proc$libresoc.v:199634$14783
     assign { } { }
     assign $1\cppr[7:0] 8'00000000
     sync always
     sync init
       update \cppr $1\cppr[7:0]
   end
-  attribute \src "libresoc.v:199655.7-199655.17"
-  process $proc$libresoc.v:199655$14784
+  attribute \src "libresoc.v:199663.7-199663.17"
+  process $proc$libresoc.v:199663$14784
     assign { } { }
     assign $1\irq[0:0] 1'0
     sync always
     sync init
       update \irq $1\irq[0:0]
   end
-  attribute \src "libresoc.v:199663.13-199663.25"
-  process $proc$libresoc.v:199663$14785
+  attribute \src "libresoc.v:199671.13-199671.25"
+  process $proc$libresoc.v:199671$14785
     assign { } { }
     assign $1\mfrr[7:0] 8'11111111
     sync always
     sync init
       update \mfrr $1\mfrr[7:0]
   end
-  attribute \src "libresoc.v:199677.7-199677.20"
-  process $proc$libresoc.v:199677$14786
+  attribute \src "libresoc.v:199685.7-199685.20"
+  process $proc$libresoc.v:199685$14786
     assign { } { }
     assign $1\wb_ack[0:0] 1'0
     sync always
     sync init
       update \wb_ack $1\wb_ack[0:0]
   end
-  attribute \src "libresoc.v:199685.14-199685.32"
-  process $proc$libresoc.v:199685$14787
+  attribute \src "libresoc.v:199693.14-199693.32"
+  process $proc$libresoc.v:199693$14787
     assign { } { }
     assign $1\wb_rd_data[31:0] 0
     sync always
     sync init
       update \wb_rd_data $1\wb_rd_data[31:0]
   end
-  attribute \src "libresoc.v:199695.14-199695.31"
-  process $proc$libresoc.v:199695$14788
+  attribute \src "libresoc.v:199703.14-199703.31"
+  process $proc$libresoc.v:199703$14788
     assign { } { }
     assign $1\xisr[23:0] 24'000000000000000000000000
     sync always
     sync init
       update \xisr $1\xisr[23:0]
   end
-  attribute \src "libresoc.v:199712.3-199713.37"
-  process $proc$libresoc.v:199712$14735
+  attribute \src "libresoc.v:199720.3-199721.37"
+  process $proc$libresoc.v:199720$14735
     assign { } { }
     assign $0\core_irq_o[0:0] \core_irq_o$next
     sync posedge \clk
       update \core_irq_o $0\core_irq_o[0:0]
   end
-  attribute \src "libresoc.v:199714.3-199715.25"
-  process $proc$libresoc.v:199714$14736
+  attribute \src "libresoc.v:199722.3-199723.25"
+  process $proc$libresoc.v:199722$14736
     assign { } { }
     assign $0\xisr[23:0] \xisr$next
     sync posedge \clk
       update \xisr $0\xisr[23:0]
   end
-  attribute \src "libresoc.v:199716.3-199717.25"
-  process $proc$libresoc.v:199716$14737
+  attribute \src "libresoc.v:199724.3-199725.25"
+  process $proc$libresoc.v:199724$14737
     assign { } { }
     assign $0\cppr[7:0] \cppr$next
     sync posedge \clk
       update \cppr $0\cppr[7:0]
   end
-  attribute \src "libresoc.v:199718.3-199719.25"
-  process $proc$libresoc.v:199718$14738
+  attribute \src "libresoc.v:199726.3-199727.25"
+  process $proc$libresoc.v:199726$14738
     assign { } { }
     assign $0\mfrr[7:0] \mfrr$next
     sync posedge \clk
       update \mfrr $0\mfrr[7:0]
   end
-  attribute \src "libresoc.v:199720.3-199721.23"
-  process $proc$libresoc.v:199720$14739
+  attribute \src "libresoc.v:199728.3-199729.23"
+  process $proc$libresoc.v:199728$14739
     assign { } { }
     assign $0\irq[0:0] \irq$next
     sync posedge \clk
       update \irq $0\irq[0:0]
   end
-  attribute \src "libresoc.v:199722.3-199723.37"
-  process $proc$libresoc.v:199722$14740
+  attribute \src "libresoc.v:199730.3-199731.37"
+  process $proc$libresoc.v:199730$14740
     assign { } { }
     assign $0\wb_rd_data[31:0] \wb_rd_data$next
     sync posedge \clk
       update \wb_rd_data $0\wb_rd_data[31:0]
   end
-  attribute \src "libresoc.v:199724.3-199725.29"
-  process $proc$libresoc.v:199724$14741
+  attribute \src "libresoc.v:199732.3-199733.29"
+  process $proc$libresoc.v:199732$14741
     assign { } { }
     assign $0\wb_ack[0:0] \wb_ack$next
     sync posedge \clk
       update \wb_ack $0\wb_ack[0:0]
   end
-  attribute \src "libresoc.v:199726.3-199741.6"
-  process $proc$libresoc.v:199726$14742
+  attribute \src "libresoc.v:199734.3-199749.6"
+  process $proc$libresoc.v:199734$14742
     assign { } { }
     assign { } { }
     assign { } { }
@@ -419423,9 +419431,9 @@ module \xics_icp
     assign $0\wb_ack$next[0:0]$14746 $1\wb_ack$next[0:0]$14752
     assign $0\wb_rd_data$next[31:0]$14747 $1\wb_rd_data$next[31:0]$14753
     assign $0\xisr$next[23:0]$14748 $1\xisr$next[23:0]$14754
-    attribute \src "libresoc.v:199727.5-199727.29"
+    attribute \src "libresoc.v:199735.5-199735.29"
     switch \initial
-      attribute \src "libresoc.v:199727.9-199727.17"
+      attribute \src "libresoc.v:199735.9-199735.17"
       case 1'1
       case 
     end
@@ -419461,14 +419469,14 @@ module \xics_icp
       update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14747
       update \xisr$next $0\xisr$next[23:0]$14748
   end
-  attribute \src "libresoc.v:199742.3-199769.6"
-  process $proc$libresoc.v:199742$14755
+  attribute \src "libresoc.v:199750.3-199777.6"
+  process $proc$libresoc.v:199750$14755
     assign { } { }
     assign { } { }
     assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0]
-    attribute \src "libresoc.v:199743.5-199743.29"
+    attribute \src "libresoc.v:199751.5-199751.29"
     switch \initial
-      attribute \src "libresoc.v:199743.9-199743.17"
+      attribute \src "libresoc.v:199751.9-199751.17"
       case 1'1
       case 
     end
@@ -419512,14 +419520,14 @@ module \xics_icp
     sync always
       update \xirr_accept_rd $0\xirr_accept_rd[0:0]
   end
-  attribute \src "libresoc.v:199770.3-199798.6"
-  process $proc$libresoc.v:199770$14756
+  attribute \src "libresoc.v:199778.3-199806.6"
+  process $proc$libresoc.v:199778$14756
     assign { } { }
     assign { } { }
     assign $0\be_out[31:0] $1\be_out[31:0]
-    attribute \src "libresoc.v:199771.5-199771.29"
+    attribute \src "libresoc.v:199779.5-199779.29"
     switch \initial
-      attribute \src "libresoc.v:199771.9-199771.17"
+      attribute \src "libresoc.v:199779.9-199779.17"
       case 1'1
       case 
     end
@@ -419562,14 +419570,14 @@ module \xics_icp
     sync always
       update \be_out $0\be_out[31:0]
   end
-  attribute \src "libresoc.v:199799.3-199808.6"
-  process $proc$libresoc.v:199799$14757
+  attribute \src "libresoc.v:199807.3-199816.6"
+  process $proc$libresoc.v:199807$14757
     assign { } { }
     assign { } { }
     assign $0\pending_priority[7:0] $1\pending_priority[7:0]
-    attribute \src "libresoc.v:199800.5-199800.29"
+    attribute \src "libresoc.v:199808.5-199808.29"
     switch \initial
-      attribute \src "libresoc.v:199800.9-199800.17"
+      attribute \src "libresoc.v:199808.9-199808.17"
       case 1'1
       case 
     end
@@ -419585,13 +419593,13 @@ module \xics_icp
     sync always
       update \pending_priority $0\pending_priority[7:0]
   end
-  attribute \src "libresoc.v:199809.3-199820.6"
-  process $proc$libresoc.v:199809$14758
+  attribute \src "libresoc.v:199817.3-199828.6"
+  process $proc$libresoc.v:199817$14758
     assign { } { }
     assign $0\min_pri[7:0] $1\min_pri[7:0]
-    attribute \src "libresoc.v:199810.5-199810.29"
+    attribute \src "libresoc.v:199818.5-199818.29"
     switch \initial
-      attribute \src "libresoc.v:199810.9-199810.17"
+      attribute \src "libresoc.v:199818.9-199818.17"
       case 1'1
       case 
     end
@@ -419609,14 +419617,14 @@ module \xics_icp
     sync always
       update \min_pri $0\min_pri[7:0]
   end
-  attribute \src "libresoc.v:199821.3-199829.6"
-  process $proc$libresoc.v:199821$14759
+  attribute \src "libresoc.v:199829.3-199837.6"
+  process $proc$libresoc.v:199829$14759
     assign { } { }
     assign { } { }
     assign $0\core_irq_o$next[0:0]$14760 $1\core_irq_o$next[0:0]$14761
-    attribute \src "libresoc.v:199822.5-199822.29"
+    attribute \src "libresoc.v:199830.5-199830.29"
     switch \initial
-      attribute \src "libresoc.v:199822.9-199822.17"
+      attribute \src "libresoc.v:199830.9-199830.17"
       case 1'1
       case 
     end
@@ -419632,14 +419640,14 @@ module \xics_icp
     sync always
       update \core_irq_o$next $0\core_irq_o$next[0:0]$14760
   end
-  attribute \src "libresoc.v:199830.3-199839.6"
-  process $proc$libresoc.v:199830$14762
+  attribute \src "libresoc.v:199838.3-199847.6"
+  process $proc$libresoc.v:199838$14762
     assign { } { }
     assign { } { }
     assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0]
-    attribute \src "libresoc.v:199831.5-199831.29"
+    attribute \src "libresoc.v:199839.5-199839.29"
     switch \initial
-      attribute \src "libresoc.v:199831.9-199831.17"
+      attribute \src "libresoc.v:199839.9-199839.17"
       case 1'1
       case 
     end
@@ -419655,8 +419663,8 @@ module \xics_icp
     sync always
       update \icp_wb__dat_r $0\icp_wb__dat_r[31:0]
   end
-  attribute \src "libresoc.v:199840.3-199902.6"
-  process $proc$libresoc.v:199840$14763
+  attribute \src "libresoc.v:199848.3-199910.6"
+  process $proc$libresoc.v:199848$14763
     assign { } { }
     assign { } { }
     assign { } { }
@@ -419675,9 +419683,9 @@ module \xics_icp
     assign $0\cppr$10[7:0]$14764 $4\cppr$10[7:0]$14779
     assign $0\wb_rd_data$13[31:0]$14768 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
     assign $0\irq$12[0:0]$14765 $1\irq$12[0:0]$14780
-    attribute \src "libresoc.v:199841.5-199841.29"
+    attribute \src "libresoc.v:199849.5-199849.29"
     switch \initial
-      attribute \src "libresoc.v:199841.9-199841.17"
+      attribute \src "libresoc.v:199849.9-199849.17"
       case 1'1
       case 
     end
@@ -419773,627 +419781,627 @@ module \xics_icp
       update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14768
       update \xisr$9 $0\xisr$9[23:0]$14769
   end
-  connect \$15 $and$libresoc.v:199702$14725_Y
-  connect \$17 $ne$libresoc.v:199703$14726_Y
-  connect \$19 $lt$libresoc.v:199704$14727_Y
-  connect \$21 $lt$libresoc.v:199705$14728_Y
-  connect \$23 $and$libresoc.v:199706$14729_Y
-  connect \$25 $eq$libresoc.v:199707$14730_Y
-  connect \$27 $and$libresoc.v:199708$14731_Y
-  connect \$29 $ne$libresoc.v:199709$14732_Y
-  connect \$31 $lt$libresoc.v:199710$14733_Y
-  connect \$7 $and$libresoc.v:199711$14734_Y
+  connect \$15 $and$libresoc.v:199710$14725_Y
+  connect \$17 $ne$libresoc.v:199711$14726_Y
+  connect \$19 $lt$libresoc.v:199712$14727_Y
+  connect \$21 $lt$libresoc.v:199713$14728_Y
+  connect \$23 $and$libresoc.v:199714$14729_Y
+  connect \$25 $eq$libresoc.v:199715$14730_Y
+  connect \$27 $and$libresoc.v:199716$14731_Y
+  connect \$29 $ne$libresoc.v:199717$14732_Y
+  connect \$31 $lt$libresoc.v:199718$14733_Y
+  connect \$7 $and$libresoc.v:199719$14734_Y
   connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 }
   connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] }
   connect \icp_wb__ack \$7
 end
-attribute \src "libresoc.v:199910.1-200959.10"
+attribute \src "libresoc.v:199918.1-200967.10"
 attribute \cells_not_processed 1
 attribute \nmigen.hierarchy "test_issuer.ti.xics_ics"
 attribute \generator "nMigen"
 module \xics_ics
-  attribute \src "libresoc.v:200840.3-200889.6"
+  attribute \src "libresoc.v:200848.3-200897.6"
   wire width 32 $0\be_out[31:0]
-  attribute \src "libresoc.v:200551.3-200560.6"
+  attribute \src "libresoc.v:200559.3-200568.6"
   wire width 4 $0\cur_idx0[3:0]
-  attribute \src "libresoc.v:200760.3-200769.6"
+  attribute \src "libresoc.v:200768.3-200777.6"
   wire width 4 $0\cur_idx10[3:0]
-  attribute \src "libresoc.v:200780.3-200789.6"
+  attribute \src "libresoc.v:200788.3-200797.6"
   wire width 4 $0\cur_idx11[3:0]
-  attribute \src "libresoc.v:200800.3-200809.6"
+  attribute \src "libresoc.v:200808.3-200817.6"
   wire width 4 $0\cur_idx12[3:0]
-  attribute \src "libresoc.v:200820.3-200829.6"
+  attribute \src "libresoc.v:200828.3-200837.6"
   wire width 4 $0\cur_idx13[3:0]
-  attribute \src "libresoc.v:200890.3-200899.6"
+  attribute \src "libresoc.v:200898.3-200907.6"
   wire width 4 $0\cur_idx14[3:0]
-  attribute \src "libresoc.v:200910.3-200919.6"
+  attribute \src "libresoc.v:200918.3-200927.6"
   wire width 4 $0\cur_idx15[3:0]
-  attribute \src "libresoc.v:200571.3-200580.6"
+  attribute \src "libresoc.v:200579.3-200588.6"
   wire width 4 $0\cur_idx1[3:0]
-  attribute \src "libresoc.v:200591.3-200600.6"
+  attribute \src "libresoc.v:200599.3-200608.6"
   wire width 4 $0\cur_idx2[3:0]
-  attribute \src "libresoc.v:200611.3-200620.6"
+  attribute \src "libresoc.v:200619.3-200628.6"
   wire width 4 $0\cur_idx3[3:0]
-  attribute \src "libresoc.v:200640.3-200649.6"
+  attribute \src "libresoc.v:200648.3-200657.6"
   wire width 4 $0\cur_idx4[3:0]
-  attribute \src "libresoc.v:200660.3-200669.6"
+  attribute \src "libresoc.v:200668.3-200677.6"
   wire width 4 $0\cur_idx5[3:0]
-  attribute \src "libresoc.v:200680.3-200689.6"
+  attribute \src "libresoc.v:200688.3-200697.6"
   wire width 4 $0\cur_idx6[3:0]
-  attribute \src "libresoc.v:200700.3-200709.6"
+  attribute \src "libresoc.v:200708.3-200717.6"
   wire width 4 $0\cur_idx7[3:0]
-  attribute \src "libresoc.v:200720.3-200729.6"
+  attribute \src "libresoc.v:200728.3-200737.6"
   wire width 4 $0\cur_idx8[3:0]
-  attribute \src "libresoc.v:200740.3-200749.6"
+  attribute \src "libresoc.v:200748.3-200757.6"
   wire width 4 $0\cur_idx9[3:0]
-  attribute \src "libresoc.v:200541.3-200550.6"
+  attribute \src "libresoc.v:200549.3-200558.6"
   wire width 8 $0\cur_pri0[7:0]
-  attribute \src "libresoc.v:200750.3-200759.6"
+  attribute \src "libresoc.v:200758.3-200767.6"
   wire width 8 $0\cur_pri10[7:0]
-  attribute \src "libresoc.v:200770.3-200779.6"
+  attribute \src "libresoc.v:200778.3-200787.6"
   wire width 8 $0\cur_pri11[7:0]
-  attribute \src "libresoc.v:200790.3-200799.6"
+  attribute \src "libresoc.v:200798.3-200807.6"
   wire width 8 $0\cur_pri12[7:0]
-  attribute \src "libresoc.v:200810.3-200819.6"
+  attribute \src "libresoc.v:200818.3-200827.6"
   wire width 8 $0\cur_pri13[7:0]
-  attribute \src "libresoc.v:200830.3-200839.6"
+  attribute \src "libresoc.v:200838.3-200847.6"
   wire width 8 $0\cur_pri14[7:0]
-  attribute \src "libresoc.v:200900.3-200909.6"
+  attribute \src "libresoc.v:200908.3-200917.6"
   wire width 8 $0\cur_pri15[7:0]
-  attribute \src "libresoc.v:200561.3-200570.6"
+  attribute \src "libresoc.v:200569.3-200578.6"
   wire width 8 $0\cur_pri1[7:0]
-  attribute \src "libresoc.v:200581.3-200590.6"
+  attribute \src "libresoc.v:200589.3-200598.6"
   wire width 8 $0\cur_pri2[7:0]
-  attribute \src "libresoc.v:200601.3-200610.6"
+  attribute \src "libresoc.v:200609.3-200618.6"
   wire width 8 $0\cur_pri3[7:0]
-  attribute \src "libresoc.v:200621.3-200630.6"
+  attribute \src "libresoc.v:200629.3-200638.6"
   wire width 8 $0\cur_pri4[7:0]
-  attribute \src "libresoc.v:200650.3-200659.6"
+  attribute \src "libresoc.v:200658.3-200667.6"
   wire width 8 $0\cur_pri5[7:0]
-  attribute \src "libresoc.v:200670.3-200679.6"
+  attribute \src "libresoc.v:200678.3-200687.6"
   wire width 8 $0\cur_pri6[7:0]
-  attribute \src "libresoc.v:200690.3-200699.6"
+  attribute \src "libresoc.v:200698.3-200707.6"
   wire width 8 $0\cur_pri7[7:0]
-  attribute \src "libresoc.v:200710.3-200719.6"
+  attribute \src "libresoc.v:200718.3-200727.6"
   wire width 8 $0\cur_pri8[7:0]
-  attribute \src "libresoc.v:200730.3-200739.6"
+  attribute \src "libresoc.v:200738.3-200747.6"
   wire width 8 $0\cur_pri9[7:0]
-  attribute \src "libresoc.v:200920.3-200929.6"
+  attribute \src "libresoc.v:200928.3-200937.6"
   wire $0\ibit[0:0]
-  attribute \src "libresoc.v:200415.3-200416.25"
+  attribute \src "libresoc.v:200423.3-200424.25"
   wire width 8 $0\icp_o_pri[7:0]
-  attribute \src "libresoc.v:200413.3-200414.28"
+  attribute \src "libresoc.v:200421.3-200422.28"
   wire width 4 $0\icp_o_src[3:0]
-  attribute \src "libresoc.v:200939.3-200947.6"
+  attribute \src "libresoc.v:200947.3-200955.6"
   wire $0\ics_wb__ack$next[0:0]$15035
-  attribute \src "libresoc.v:200449.3-200450.39"
+  attribute \src "libresoc.v:200457.3-200458.39"
   wire $0\ics_wb__ack[0:0]
-  attribute \src "libresoc.v:200930.3-200938.6"
+  attribute \src "libresoc.v:200938.3-200946.6"
   wire width 32 $0\ics_wb__dat_r$next[31:0]$15032
-  attribute \src "libresoc.v:200451.3-200452.43"
+  attribute \src "libresoc.v:200459.3-200460.43"
   wire width 32 $0\ics_wb__dat_r[31:0]
-  attribute \src "libresoc.v:199911.7-199911.20"
+  attribute \src "libresoc.v:199919.7-199919.20"
   wire $0\initial[0:0]
-  attribute \src "libresoc.v:200631.3-200639.6"
+  attribute \src "libresoc.v:200639.3-200647.6"
   wire width 16 $0\int_level_l$next[15:0]$15004
-  attribute \src "libresoc.v:200453.3-200454.39"
+  attribute \src "libresoc.v:200461.3-200462.39"
   wire width 16 $0\int_level_l[15:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive0_pri$next[7:0]$14914
-  attribute \src "libresoc.v:200417.3-200418.35"
+  attribute \src "libresoc.v:200425.3-200426.35"
   wire width 8 $0\xive0_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive10_pri$next[7:0]$14915
-  attribute \src "libresoc.v:200437.3-200438.37"
+  attribute \src "libresoc.v:200445.3-200446.37"
   wire width 8 $0\xive10_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive11_pri$next[7:0]$14916
-  attribute \src "libresoc.v:200439.3-200440.37"
+  attribute \src "libresoc.v:200447.3-200448.37"
   wire width 8 $0\xive11_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive12_pri$next[7:0]$14917
-  attribute \src "libresoc.v:200441.3-200442.37"
+  attribute \src "libresoc.v:200449.3-200450.37"
   wire width 8 $0\xive12_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive13_pri$next[7:0]$14918
-  attribute \src "libresoc.v:200443.3-200444.37"
+  attribute \src "libresoc.v:200451.3-200452.37"
   wire width 8 $0\xive13_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive14_pri$next[7:0]$14919
-  attribute \src "libresoc.v:200445.3-200446.37"
+  attribute \src "libresoc.v:200453.3-200454.37"
   wire width 8 $0\xive14_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive15_pri$next[7:0]$14920
-  attribute \src "libresoc.v:200447.3-200448.37"
+  attribute \src "libresoc.v:200455.3-200456.37"
   wire width 8 $0\xive15_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive1_pri$next[7:0]$14921
-  attribute \src "libresoc.v:200419.3-200420.35"
+  attribute \src "libresoc.v:200427.3-200428.35"
   wire width 8 $0\xive1_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive2_pri$next[7:0]$14922
-  attribute \src "libresoc.v:200421.3-200422.35"
+  attribute \src "libresoc.v:200429.3-200430.35"
   wire width 8 $0\xive2_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive3_pri$next[7:0]$14923
-  attribute \src "libresoc.v:200423.3-200424.35"
+  attribute \src "libresoc.v:200431.3-200432.35"
   wire width 8 $0\xive3_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive4_pri$next[7:0]$14924
-  attribute \src "libresoc.v:200425.3-200426.35"
+  attribute \src "libresoc.v:200433.3-200434.35"
   wire width 8 $0\xive4_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive5_pri$next[7:0]$14925
-  attribute \src "libresoc.v:200427.3-200428.35"
+  attribute \src "libresoc.v:200435.3-200436.35"
   wire width 8 $0\xive5_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive6_pri$next[7:0]$14926
-  attribute \src "libresoc.v:200429.3-200430.35"
+  attribute \src "libresoc.v:200437.3-200438.35"
   wire width 8 $0\xive6_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive7_pri$next[7:0]$14927
-  attribute \src "libresoc.v:200431.3-200432.35"
+  attribute \src "libresoc.v:200439.3-200440.35"
   wire width 8 $0\xive7_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive8_pri$next[7:0]$14928
-  attribute \src "libresoc.v:200433.3-200434.35"
+  attribute \src "libresoc.v:200441.3-200442.35"
   wire width 8 $0\xive8_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $0\xive9_pri$next[7:0]$14929
-  attribute \src "libresoc.v:200435.3-200436.35"
+  attribute \src "libresoc.v:200443.3-200444.35"
   wire width 8 $0\xive9_pri[7:0]
-  attribute \src "libresoc.v:200840.3-200889.6"
+  attribute \src "libresoc.v:200848.3-200897.6"
   wire width 32 $1\be_out[31:0]
-  attribute \src "libresoc.v:200551.3-200560.6"
+  attribute \src "libresoc.v:200559.3-200568.6"
   wire width 4 $1\cur_idx0[3:0]
-  attribute \src "libresoc.v:200760.3-200769.6"
+  attribute \src "libresoc.v:200768.3-200777.6"
   wire width 4 $1\cur_idx10[3:0]
-  attribute \src "libresoc.v:200780.3-200789.6"
+  attribute \src "libresoc.v:200788.3-200797.6"
   wire width 4 $1\cur_idx11[3:0]
-  attribute \src "libresoc.v:200800.3-200809.6"
+  attribute \src "libresoc.v:200808.3-200817.6"
   wire width 4 $1\cur_idx12[3:0]
-  attribute \src "libresoc.v:200820.3-200829.6"
+  attribute \src "libresoc.v:200828.3-200837.6"
   wire width 4 $1\cur_idx13[3:0]
-  attribute \src "libresoc.v:200890.3-200899.6"
+  attribute \src "libresoc.v:200898.3-200907.6"
   wire width 4 $1\cur_idx14[3:0]
-  attribute \src "libresoc.v:200910.3-200919.6"
+  attribute \src "libresoc.v:200918.3-200927.6"
   wire width 4 $1\cur_idx15[3:0]
-  attribute \src "libresoc.v:200571.3-200580.6"
+  attribute \src "libresoc.v:200579.3-200588.6"
   wire width 4 $1\cur_idx1[3:0]
-  attribute \src "libresoc.v:200591.3-200600.6"
+  attribute \src "libresoc.v:200599.3-200608.6"
   wire width 4 $1\cur_idx2[3:0]
-  attribute \src "libresoc.v:200611.3-200620.6"
+  attribute \src "libresoc.v:200619.3-200628.6"
   wire width 4 $1\cur_idx3[3:0]
-  attribute \src "libresoc.v:200640.3-200649.6"
+  attribute \src "libresoc.v:200648.3-200657.6"
   wire width 4 $1\cur_idx4[3:0]
-  attribute \src "libresoc.v:200660.3-200669.6"
+  attribute \src "libresoc.v:200668.3-200677.6"
   wire width 4 $1\cur_idx5[3:0]
-  attribute \src "libresoc.v:200680.3-200689.6"
+  attribute \src "libresoc.v:200688.3-200697.6"
   wire width 4 $1\cur_idx6[3:0]
-  attribute \src "libresoc.v:200700.3-200709.6"
+  attribute \src "libresoc.v:200708.3-200717.6"
   wire width 4 $1\cur_idx7[3:0]
-  attribute \src "libresoc.v:200720.3-200729.6"
+  attribute \src "libresoc.v:200728.3-200737.6"
   wire width 4 $1\cur_idx8[3:0]
-  attribute \src "libresoc.v:200740.3-200749.6"
+  attribute \src "libresoc.v:200748.3-200757.6"
   wire width 4 $1\cur_idx9[3:0]
-  attribute \src "libresoc.v:200541.3-200550.6"
+  attribute \src "libresoc.v:200549.3-200558.6"
   wire width 8 $1\cur_pri0[7:0]
-  attribute \src "libresoc.v:200750.3-200759.6"
+  attribute \src "libresoc.v:200758.3-200767.6"
   wire width 8 $1\cur_pri10[7:0]
-  attribute \src "libresoc.v:200770.3-200779.6"
+  attribute \src "libresoc.v:200778.3-200787.6"
   wire width 8 $1\cur_pri11[7:0]
-  attribute \src "libresoc.v:200790.3-200799.6"
+  attribute \src "libresoc.v:200798.3-200807.6"
   wire width 8 $1\cur_pri12[7:0]
-  attribute \src "libresoc.v:200810.3-200819.6"
+  attribute \src "libresoc.v:200818.3-200827.6"
   wire width 8 $1\cur_pri13[7:0]
-  attribute \src "libresoc.v:200830.3-200839.6"
+  attribute \src "libresoc.v:200838.3-200847.6"
   wire width 8 $1\cur_pri14[7:0]
-  attribute \src "libresoc.v:200900.3-200909.6"
+  attribute \src "libresoc.v:200908.3-200917.6"
   wire width 8 $1\cur_pri15[7:0]
-  attribute \src "libresoc.v:200561.3-200570.6"
+  attribute \src "libresoc.v:200569.3-200578.6"
   wire width 8 $1\cur_pri1[7:0]
-  attribute \src "libresoc.v:200581.3-200590.6"
+  attribute \src "libresoc.v:200589.3-200598.6"
   wire width 8 $1\cur_pri2[7:0]
-  attribute \src "libresoc.v:200601.3-200610.6"
+  attribute \src "libresoc.v:200609.3-200618.6"
   wire width 8 $1\cur_pri3[7:0]
-  attribute \src "libresoc.v:200621.3-200630.6"
+  attribute \src "libresoc.v:200629.3-200638.6"
   wire width 8 $1\cur_pri4[7:0]
-  attribute \src "libresoc.v:200650.3-200659.6"
+  attribute \src "libresoc.v:200658.3-200667.6"
   wire width 8 $1\cur_pri5[7:0]
-  attribute \src "libresoc.v:200670.3-200679.6"
+  attribute \src "libresoc.v:200678.3-200687.6"
   wire width 8 $1\cur_pri6[7:0]
-  attribute \src "libresoc.v:200690.3-200699.6"
+  attribute \src "libresoc.v:200698.3-200707.6"
   wire width 8 $1\cur_pri7[7:0]
-  attribute \src "libresoc.v:200710.3-200719.6"
+  attribute \src "libresoc.v:200718.3-200727.6"
   wire width 8 $1\cur_pri8[7:0]
-  attribute \src "libresoc.v:200730.3-200739.6"
+  attribute \src "libresoc.v:200738.3-200747.6"
   wire width 8 $1\cur_pri9[7:0]
-  attribute \src "libresoc.v:200920.3-200929.6"
+  attribute \src "libresoc.v:200928.3-200937.6"
   wire $1\ibit[0:0]
-  attribute \src "libresoc.v:200192.13-200192.30"
+  attribute \src "libresoc.v:200200.13-200200.30"
   wire width 8 $1\icp_o_pri[7:0]
-  attribute \src "libresoc.v:200197.13-200197.29"
+  attribute \src "libresoc.v:200205.13-200205.29"
   wire width 4 $1\icp_o_src[3:0]
-  attribute \src "libresoc.v:200939.3-200947.6"
+  attribute \src "libresoc.v:200947.3-200955.6"
   wire $1\ics_wb__ack$next[0:0]$15036
-  attribute \src "libresoc.v:200206.7-200206.25"
+  attribute \src "libresoc.v:200214.7-200214.25"
   wire $1\ics_wb__ack[0:0]
-  attribute \src "libresoc.v:200930.3-200938.6"
+  attribute \src "libresoc.v:200938.3-200946.6"
   wire width 32 $1\ics_wb__dat_r$next[31:0]$15033
-  attribute \src "libresoc.v:200215.14-200215.35"
+  attribute \src "libresoc.v:200223.14-200223.35"
   wire width 32 $1\ics_wb__dat_r[31:0]
-  attribute \src "libresoc.v:200631.3-200639.6"
+  attribute \src "libresoc.v:200639.3-200647.6"
   wire width 16 $1\int_level_l$next[15:0]$15005
-  attribute \src "libresoc.v:200227.14-200227.36"
+  attribute \src "libresoc.v:200235.14-200235.36"
   wire width 16 $1\int_level_l[15:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive0_pri$next[7:0]$14930
-  attribute \src "libresoc.v:200247.13-200247.30"
+  attribute \src "libresoc.v:200255.13-200255.30"
   wire width 8 $1\xive0_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive10_pri$next[7:0]$14931
-  attribute \src "libresoc.v:200251.13-200251.31"
+  attribute \src "libresoc.v:200259.13-200259.31"
   wire width 8 $1\xive10_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive11_pri$next[7:0]$14932
-  attribute \src "libresoc.v:200255.13-200255.31"
+  attribute \src "libresoc.v:200263.13-200263.31"
   wire width 8 $1\xive11_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive12_pri$next[7:0]$14933
-  attribute \src "libresoc.v:200259.13-200259.31"
+  attribute \src "libresoc.v:200267.13-200267.31"
   wire width 8 $1\xive12_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive13_pri$next[7:0]$14934
-  attribute \src "libresoc.v:200263.13-200263.31"
+  attribute \src "libresoc.v:200271.13-200271.31"
   wire width 8 $1\xive13_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive14_pri$next[7:0]$14935
-  attribute \src "libresoc.v:200267.13-200267.31"
+  attribute \src "libresoc.v:200275.13-200275.31"
   wire width 8 $1\xive14_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive15_pri$next[7:0]$14936
-  attribute \src "libresoc.v:200271.13-200271.31"
+  attribute \src "libresoc.v:200279.13-200279.31"
   wire width 8 $1\xive15_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive1_pri$next[7:0]$14937
-  attribute \src "libresoc.v:200275.13-200275.30"
+  attribute \src "libresoc.v:200283.13-200283.30"
   wire width 8 $1\xive1_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive2_pri$next[7:0]$14938
-  attribute \src "libresoc.v:200279.13-200279.30"
+  attribute \src "libresoc.v:200287.13-200287.30"
   wire width 8 $1\xive2_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive3_pri$next[7:0]$14939
-  attribute \src "libresoc.v:200283.13-200283.30"
+  attribute \src "libresoc.v:200291.13-200291.30"
   wire width 8 $1\xive3_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive4_pri$next[7:0]$14940
-  attribute \src "libresoc.v:200287.13-200287.30"
+  attribute \src "libresoc.v:200295.13-200295.30"
   wire width 8 $1\xive4_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive5_pri$next[7:0]$14941
-  attribute \src "libresoc.v:200291.13-200291.30"
+  attribute \src "libresoc.v:200299.13-200299.30"
   wire width 8 $1\xive5_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive6_pri$next[7:0]$14942
-  attribute \src "libresoc.v:200295.13-200295.30"
+  attribute \src "libresoc.v:200303.13-200303.30"
   wire width 8 $1\xive6_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive7_pri$next[7:0]$14943
-  attribute \src "libresoc.v:200299.13-200299.30"
+  attribute \src "libresoc.v:200307.13-200307.30"
   wire width 8 $1\xive7_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive8_pri$next[7:0]$14944
-  attribute \src "libresoc.v:200303.13-200303.30"
+  attribute \src "libresoc.v:200311.13-200311.30"
   wire width 8 $1\xive8_pri[7:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $1\xive9_pri$next[7:0]$14945
-  attribute \src "libresoc.v:200307.13-200307.30"
+  attribute \src "libresoc.v:200315.13-200315.30"
   wire width 8 $1\xive9_pri[7:0]
-  attribute \src "libresoc.v:200840.3-200889.6"
+  attribute \src "libresoc.v:200848.3-200897.6"
   wire width 32 $2\be_out[31:0]
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive0_pri$next[7:0]$14946
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive10_pri$next[7:0]$14947
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive11_pri$next[7:0]$14948
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive12_pri$next[7:0]$14949
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive13_pri$next[7:0]$14950
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive14_pri$next[7:0]$14951
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive15_pri$next[7:0]$14952
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive1_pri$next[7:0]$14953
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive2_pri$next[7:0]$14954
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive3_pri$next[7:0]$14955
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive4_pri$next[7:0]$14956
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive5_pri$next[7:0]$14957
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive6_pri$next[7:0]$14958
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive7_pri$next[7:0]$14959
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive8_pri$next[7:0]$14960
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $2\xive9_pri$next[7:0]$14961
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive0_pri$next[7:0]$14962
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive10_pri$next[7:0]$14963
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive11_pri$next[7:0]$14964
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive12_pri$next[7:0]$14965
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive13_pri$next[7:0]$14966
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive14_pri$next[7:0]$14967
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive15_pri$next[7:0]$14968
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive1_pri$next[7:0]$14969
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive2_pri$next[7:0]$14970
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive3_pri$next[7:0]$14971
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive4_pri$next[7:0]$14972
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive5_pri$next[7:0]$14973
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive6_pri$next[7:0]$14974
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive7_pri$next[7:0]$14975
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive8_pri$next[7:0]$14976
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $3\xive9_pri$next[7:0]$14977
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive0_pri$next[7:0]$14978
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive10_pri$next[7:0]$14979
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive11_pri$next[7:0]$14980
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive12_pri$next[7:0]$14981
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive13_pri$next[7:0]$14982
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive14_pri$next[7:0]$14983
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive15_pri$next[7:0]$14984
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive1_pri$next[7:0]$14985
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive2_pri$next[7:0]$14986
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive3_pri$next[7:0]$14987
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive4_pri$next[7:0]$14988
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive5_pri$next[7:0]$14989
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive6_pri$next[7:0]$14990
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive7_pri$next[7:0]$14991
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive8_pri$next[7:0]$14992
-  attribute \src "libresoc.v:200455.3-200540.6"
+  attribute \src "libresoc.v:200463.3-200548.6"
   wire width 8 $4\xive9_pri$next[7:0]$14993
-  attribute \src "libresoc.v:200312.19-200312.113"
-  wire $and$libresoc.v:200312$14791_Y
-  attribute \src "libresoc.v:200314.19-200314.114"
-  wire $and$libresoc.v:200314$14793_Y
-  attribute \src "libresoc.v:200316.19-200316.114"
-  wire $and$libresoc.v:200316$14795_Y
-  attribute \src "libresoc.v:200318.19-200318.114"
-  wire $and$libresoc.v:200318$14797_Y
-  attribute \src "libresoc.v:200320.19-200320.114"
-  wire $and$libresoc.v:200320$14799_Y
+  attribute \src "libresoc.v:200320.19-200320.113"
+  wire $and$libresoc.v:200320$14791_Y
   attribute \src "libresoc.v:200322.19-200322.114"
-  wire $and$libresoc.v:200322$14801_Y
+  wire $and$libresoc.v:200322$14793_Y
   attribute \src "libresoc.v:200324.19-200324.114"
-  wire $and$libresoc.v:200324$14803_Y
-  attribute \src "libresoc.v:200327.19-200327.114"
-  wire $and$libresoc.v:200327$14806_Y
-  attribute \src "libresoc.v:200329.19-200329.114"
-  wire $and$libresoc.v:200329$14808_Y
-  attribute \src "libresoc.v:200331.19-200331.114"
-  wire $and$libresoc.v:200331$14810_Y
-  attribute \src "libresoc.v:200334.19-200334.114"
-  wire $and$libresoc.v:200334$14813_Y
-  attribute \src "libresoc.v:200336.19-200336.114"
-  wire $and$libresoc.v:200336$14815_Y
-  attribute \src "libresoc.v:200338.19-200338.114"
-  wire $and$libresoc.v:200338$14817_Y
-  attribute \src "libresoc.v:200340.19-200340.114"
-  wire $and$libresoc.v:200340$14819_Y
-  attribute \src "libresoc.v:200342.19-200342.115"
-  wire $and$libresoc.v:200342$14821_Y
-  attribute \src "libresoc.v:200344.19-200344.115"
-  wire $and$libresoc.v:200344$14823_Y
-  attribute \src "libresoc.v:200346.19-200346.115"
-  wire $and$libresoc.v:200346$14825_Y
-  attribute \src "libresoc.v:200349.19-200349.115"
-  wire $and$libresoc.v:200349$14828_Y
-  attribute \src "libresoc.v:200351.19-200351.115"
-  wire $and$libresoc.v:200351$14830_Y
-  attribute \src "libresoc.v:200353.19-200353.115"
-  wire $and$libresoc.v:200353$14832_Y
-  attribute \src "libresoc.v:200356.19-200356.115"
-  wire $and$libresoc.v:200356$14835_Y
-  attribute \src "libresoc.v:200358.19-200358.115"
-  wire $and$libresoc.v:200358$14837_Y
-  attribute \src "libresoc.v:200360.19-200360.115"
-  wire $and$libresoc.v:200360$14839_Y
-  attribute \src "libresoc.v:200362.19-200362.115"
-  wire $and$libresoc.v:200362$14841_Y
+  wire $and$libresoc.v:200324$14795_Y
+  attribute \src "libresoc.v:200326.19-200326.114"
+  wire $and$libresoc.v:200326$14797_Y
+  attribute \src "libresoc.v:200328.19-200328.114"
+  wire $and$libresoc.v:200328$14799_Y
+  attribute \src "libresoc.v:200330.19-200330.114"
+  wire $and$libresoc.v:200330$14801_Y
+  attribute \src "libresoc.v:200332.19-200332.114"
+  wire $and$libresoc.v:200332$14803_Y
+  attribute \src "libresoc.v:200335.19-200335.114"
+  wire $and$libresoc.v:200335$14806_Y
+  attribute \src "libresoc.v:200337.19-200337.114"
+  wire $and$libresoc.v:200337$14808_Y
+  attribute \src "libresoc.v:200339.19-200339.114"
+  wire $and$libresoc.v:200339$14810_Y
+  attribute \src "libresoc.v:200342.19-200342.114"
+  wire $and$libresoc.v:200342$14813_Y
+  attribute \src "libresoc.v:200344.19-200344.114"
+  wire $and$libresoc.v:200344$14815_Y
+  attribute \src "libresoc.v:200346.19-200346.114"
+  wire $and$libresoc.v:200346$14817_Y
+  attribute \src "libresoc.v:200348.19-200348.114"
+  wire $and$libresoc.v:200348$14819_Y
+  attribute \src "libresoc.v:200350.19-200350.115"
+  wire $and$libresoc.v:200350$14821_Y
+  attribute \src "libresoc.v:200352.19-200352.115"
+  wire $and$libresoc.v:200352$14823_Y
+  attribute \src "libresoc.v:200354.19-200354.115"
+  wire $and$libresoc.v:200354$14825_Y
+  attribute \src "libresoc.v:200357.19-200357.115"
+  wire $and$libresoc.v:200357$14828_Y
+  attribute \src "libresoc.v:200359.19-200359.115"
+  wire $and$libresoc.v:200359$14830_Y
+  attribute \src "libresoc.v:200361.19-200361.115"
+  wire $and$libresoc.v:200361$14832_Y
   attribute \src "libresoc.v:200364.19-200364.115"
-  wire $and$libresoc.v:200364$14843_Y
-  attribute \src "libresoc.v:200367.19-200367.115"
-  wire $and$libresoc.v:200367$14846_Y
-  attribute \src "libresoc.v:200391.17-200391.115"
-  wire $and$libresoc.v:200391$14870_Y
-  attribute \src "libresoc.v:200399.18-200399.112"
-  wire $and$libresoc.v:200399$14878_Y
-  attribute \src "libresoc.v:200401.18-200401.112"
-  wire $and$libresoc.v:200401$14880_Y
-  attribute \src "libresoc.v:200403.18-200403.112"
-  wire $and$libresoc.v:200403$14882_Y
-  attribute \src "libresoc.v:200405.18-200405.112"
-  wire $and$libresoc.v:200405$14884_Y
-  attribute \src "libresoc.v:200408.18-200408.112"
-  wire $and$libresoc.v:200408$14887_Y
-  attribute \src "libresoc.v:200410.18-200410.112"
-  wire $and$libresoc.v:200410$14889_Y
-  attribute \src "libresoc.v:200412.18-200412.112"
-  wire $and$libresoc.v:200412$14891_Y
-  attribute \src "libresoc.v:200326.18-200326.109"
-  wire $eq$libresoc.v:200326$14805_Y
-  attribute \src "libresoc.v:200348.18-200348.109"
-  wire $eq$libresoc.v:200348$14827_Y
-  attribute \src "libresoc.v:200365.17-200365.114"
-  wire $eq$libresoc.v:200365$14844_Y
-  attribute \src "libresoc.v:200368.19-200368.110"
-  wire $eq$libresoc.v:200368$14847_Y
-  attribute \src "libresoc.v:200370.18-200370.109"
-  wire $eq$libresoc.v:200370$14849_Y
-  attribute \src "libresoc.v:200372.18-200372.109"
-  wire $eq$libresoc.v:200372$14851_Y
-  attribute \src "libresoc.v:200374.18-200374.109"
-  wire $eq$libresoc.v:200374$14853_Y
-  attribute \src "libresoc.v:200376.18-200376.109"
-  wire $eq$libresoc.v:200376$14855_Y
+  wire $and$libresoc.v:200364$14835_Y
+  attribute \src "libresoc.v:200366.19-200366.115"
+  wire $and$libresoc.v:200366$14837_Y
+  attribute \src "libresoc.v:200368.19-200368.115"
+  wire $and$libresoc.v:200368$14839_Y
+  attribute \src "libresoc.v:200370.19-200370.115"
+  wire $and$libresoc.v:200370$14841_Y
+  attribute \src "libresoc.v:200372.19-200372.115"
+  wire $and$libresoc.v:200372$14843_Y
+  attribute \src "libresoc.v:200375.19-200375.115"
+  wire $and$libresoc.v:200375$14846_Y
+  attribute \src "libresoc.v:200399.17-200399.115"
+  wire $and$libresoc.v:200399$14870_Y
+  attribute \src "libresoc.v:200407.18-200407.112"
+  wire $and$libresoc.v:200407$14878_Y
+  attribute \src "libresoc.v:200409.18-200409.112"
+  wire $and$libresoc.v:200409$14880_Y
+  attribute \src "libresoc.v:200411.18-200411.112"
+  wire $and$libresoc.v:200411$14882_Y
+  attribute \src "libresoc.v:200413.18-200413.112"
+  wire $and$libresoc.v:200413$14884_Y
+  attribute \src "libresoc.v:200416.18-200416.112"
+  wire $and$libresoc.v:200416$14887_Y
+  attribute \src "libresoc.v:200418.18-200418.112"
+  wire $and$libresoc.v:200418$14889_Y
+  attribute \src "libresoc.v:200420.18-200420.112"
+  wire $and$libresoc.v:200420$14891_Y
+  attribute \src "libresoc.v:200334.18-200334.109"
+  wire $eq$libresoc.v:200334$14805_Y
+  attribute \src "libresoc.v:200356.18-200356.109"
+  wire $eq$libresoc.v:200356$14827_Y
+  attribute \src "libresoc.v:200373.17-200373.114"
+  wire $eq$libresoc.v:200373$14844_Y
+  attribute \src "libresoc.v:200376.19-200376.110"
+  wire $eq$libresoc.v:200376$14847_Y
   attribute \src "libresoc.v:200378.18-200378.109"
-  wire $eq$libresoc.v:200378$14857_Y
-  attribute \src "libresoc.v:200380.17-200380.114"
-  wire $eq$libresoc.v:200380$14859_Y
-  attribute \src "libresoc.v:200381.18-200381.109"
-  wire $eq$libresoc.v:200381$14860_Y
-  attribute \src "libresoc.v:200383.18-200383.109"
-  wire $eq$libresoc.v:200383$14862_Y
-  attribute \src "libresoc.v:200385.18-200385.110"
-  wire $eq$libresoc.v:200385$14864_Y
-  attribute \src "libresoc.v:200387.18-200387.110"
-  wire $eq$libresoc.v:200387$14866_Y
-  attribute \src "libresoc.v:200389.18-200389.110"
-  wire $eq$libresoc.v:200389$14868_Y
-  attribute \src "libresoc.v:200392.18-200392.110"
-  wire $eq$libresoc.v:200392$14871_Y
-  attribute \src "libresoc.v:200394.18-200394.110"
-  wire $eq$libresoc.v:200394$14873_Y
-  attribute \src "libresoc.v:200396.18-200396.110"
-  wire $eq$libresoc.v:200396$14875_Y
-  attribute \src "libresoc.v:200407.17-200407.108"
-  wire $eq$libresoc.v:200407$14886_Y
-  attribute \src "libresoc.v:200311.18-200311.111"
-  wire $lt$libresoc.v:200311$14790_Y
-  attribute \src "libresoc.v:200313.19-200313.112"
-  wire $lt$libresoc.v:200313$14792_Y
-  attribute \src "libresoc.v:200315.19-200315.112"
-  wire $lt$libresoc.v:200315$14794_Y
-  attribute \src "libresoc.v:200317.19-200317.112"
-  wire $lt$libresoc.v:200317$14796_Y
-  attribute \src "libresoc.v:200319.19-200319.112"
-  wire $lt$libresoc.v:200319$14798_Y
+  wire $eq$libresoc.v:200378$14849_Y
+  attribute \src "libresoc.v:200380.18-200380.109"
+  wire $eq$libresoc.v:200380$14851_Y
+  attribute \src "libresoc.v:200382.18-200382.109"
+  wire $eq$libresoc.v:200382$14853_Y
+  attribute \src "libresoc.v:200384.18-200384.109"
+  wire $eq$libresoc.v:200384$14855_Y
+  attribute \src "libresoc.v:200386.18-200386.109"
+  wire $eq$libresoc.v:200386$14857_Y
+  attribute \src "libresoc.v:200388.17-200388.114"
+  wire $eq$libresoc.v:200388$14859_Y
+  attribute \src "libresoc.v:200389.18-200389.109"
+  wire $eq$libresoc.v:200389$14860_Y
+  attribute \src "libresoc.v:200391.18-200391.109"
+  wire $eq$libresoc.v:200391$14862_Y
+  attribute \src "libresoc.v:200393.18-200393.110"
+  wire $eq$libresoc.v:200393$14864_Y
+  attribute \src "libresoc.v:200395.18-200395.110"
+  wire $eq$libresoc.v:200395$14866_Y
+  attribute \src "libresoc.v:200397.18-200397.110"
+  wire $eq$libresoc.v:200397$14868_Y
+  attribute \src "libresoc.v:200400.18-200400.110"
+  wire $eq$libresoc.v:200400$14871_Y
+  attribute \src "libresoc.v:200402.18-200402.110"
+  wire $eq$libresoc.v:200402$14873_Y
+  attribute \src "libresoc.v:200404.18-200404.110"
+  wire $eq$libresoc.v:200404$14875_Y
+  attribute \src "libresoc.v:200415.17-200415.108"
+  wire $eq$libresoc.v:200415$14886_Y
+  attribute \src "libresoc.v:200319.18-200319.111"
+  wire $lt$libresoc.v:200319$14790_Y
   attribute \src "libresoc.v:200321.19-200321.112"
-  wire $lt$libresoc.v:200321$14800_Y
+  wire $lt$libresoc.v:200321$14792_Y
   attribute \src "libresoc.v:200323.19-200323.112"
-  wire $lt$libresoc.v:200323$14802_Y
+  wire $lt$libresoc.v:200323$14794_Y
   attribute \src "libresoc.v:200325.19-200325.112"
-  wire $lt$libresoc.v:200325$14804_Y
-  attribute \src "libresoc.v:200328.19-200328.112"
-  wire $lt$libresoc.v:200328$14807_Y
-  attribute \src "libresoc.v:200330.19-200330.112"
-  wire $lt$libresoc.v:200330$14809_Y
+  wire $lt$libresoc.v:200325$14796_Y
+  attribute \src "libresoc.v:200327.19-200327.112"
+  wire $lt$libresoc.v:200327$14798_Y
+  attribute \src "libresoc.v:200329.19-200329.112"
+  wire $lt$libresoc.v:200329$14800_Y
+  attribute \src "libresoc.v:200331.19-200331.112"
+  wire $lt$libresoc.v:200331$14802_Y
   attribute \src "libresoc.v:200333.19-200333.112"
-  wire $lt$libresoc.v:200333$14812_Y
-  attribute \src "libresoc.v:200335.19-200335.112"
-  wire $lt$libresoc.v:200335$14814_Y
-  attribute \src "libresoc.v:200337.19-200337.112"
-  wire $lt$libresoc.v:200337$14816_Y
-  attribute \src "libresoc.v:200339.19-200339.112"
-  wire $lt$libresoc.v:200339$14818_Y
-  attribute \src "libresoc.v:200341.19-200341.113"
-  wire $lt$libresoc.v:200341$14820_Y
-  attribute \src "libresoc.v:200343.19-200343.113"
-  wire $lt$libresoc.v:200343$14822_Y
-  attribute \src "libresoc.v:200345.19-200345.114"
-  wire $lt$libresoc.v:200345$14824_Y
-  attribute \src "libresoc.v:200347.19-200347.114"
-  wire $lt$libresoc.v:200347$14826_Y
-  attribute \src "libresoc.v:200350.19-200350.114"
-  wire $lt$libresoc.v:200350$14829_Y
-  attribute \src "libresoc.v:200352.19-200352.114"
-  wire $lt$libresoc.v:200352$14831_Y
+  wire $lt$libresoc.v:200333$14804_Y
+  attribute \src "libresoc.v:200336.19-200336.112"
+  wire $lt$libresoc.v:200336$14807_Y
+  attribute \src "libresoc.v:200338.19-200338.112"
+  wire $lt$libresoc.v:200338$14809_Y
+  attribute \src "libresoc.v:200341.19-200341.112"
+  wire $lt$libresoc.v:200341$14812_Y
+  attribute \src "libresoc.v:200343.19-200343.112"
+  wire $lt$libresoc.v:200343$14814_Y
+  attribute \src "libresoc.v:200345.19-200345.112"
+  wire $lt$libresoc.v:200345$14816_Y
+  attribute \src "libresoc.v:200347.19-200347.112"
+  wire $lt$libresoc.v:200347$14818_Y
+  attribute \src "libresoc.v:200349.19-200349.113"
+  wire $lt$libresoc.v:200349$14820_Y
+  attribute \src "libresoc.v:200351.19-200351.113"
+  wire $lt$libresoc.v:200351$14822_Y
+  attribute \src "libresoc.v:200353.19-200353.114"
+  wire $lt$libresoc.v:200353$14824_Y
   attribute \src "libresoc.v:200355.19-200355.114"
-  wire $lt$libresoc.v:200355$14834_Y
-  attribute \src "libresoc.v:200357.19-200357.114"
-  wire $lt$libresoc.v:200357$14836_Y
-  attribute \src "libresoc.v:200359.19-200359.114"
-  wire $lt$libresoc.v:200359$14838_Y
-  attribute \src "libresoc.v:200361.19-200361.114"
-  wire $lt$libresoc.v:200361$14840_Y
+  wire $lt$libresoc.v:200355$14826_Y
+  attribute \src "libresoc.v:200358.19-200358.114"
+  wire $lt$libresoc.v:200358$14829_Y
+  attribute \src "libresoc.v:200360.19-200360.114"
+  wire $lt$libresoc.v:200360$14831_Y
   attribute \src "libresoc.v:200363.19-200363.114"
-  wire $lt$libresoc.v:200363$14842_Y
-  attribute \src "libresoc.v:200366.19-200366.114"
-  wire $lt$libresoc.v:200366$14845_Y
-  attribute \src "libresoc.v:200400.18-200400.110"
-  wire $lt$libresoc.v:200400$14879_Y
-  attribute \src "libresoc.v:200402.18-200402.110"
-  wire $lt$libresoc.v:200402$14881_Y
-  attribute \src "libresoc.v:200404.18-200404.111"
-  wire $lt$libresoc.v:200404$14883_Y
-  attribute \src "libresoc.v:200406.18-200406.111"
-  wire $lt$libresoc.v:200406$14885_Y
-  attribute \src "libresoc.v:200409.18-200409.111"
-  wire $lt$libresoc.v:200409$14888_Y
-  attribute \src "libresoc.v:200411.18-200411.111"
-  wire $lt$libresoc.v:200411$14890_Y
-  attribute \src "libresoc.v:200398.18-200398.40"
-  wire width 16 $shr$libresoc.v:200398$14877_Y
-  attribute \src "libresoc.v:200310.17-200310.114"
-  wire width 8 $ternary$libresoc.v:200310$14789_Y
-  attribute \src "libresoc.v:200332.18-200332.116"
-  wire width 8 $ternary$libresoc.v:200332$14811_Y
-  attribute \src "libresoc.v:200354.18-200354.116"
-  wire width 8 $ternary$libresoc.v:200354$14833_Y
-  attribute \src "libresoc.v:200369.19-200369.118"
-  wire width 8 $ternary$libresoc.v:200369$14848_Y
-  attribute \src "libresoc.v:200371.18-200371.116"
-  wire width 8 $ternary$libresoc.v:200371$14850_Y
-  attribute \src "libresoc.v:200373.18-200373.116"
-  wire width 8 $ternary$libresoc.v:200373$14852_Y
-  attribute \src "libresoc.v:200375.18-200375.116"
-  wire width 8 $ternary$libresoc.v:200375$14854_Y
-  attribute \src "libresoc.v:200377.18-200377.116"
-  wire width 8 $ternary$libresoc.v:200377$14856_Y
+  wire $lt$libresoc.v:200363$14834_Y
+  attribute \src "libresoc.v:200365.19-200365.114"
+  wire $lt$libresoc.v:200365$14836_Y
+  attribute \src "libresoc.v:200367.19-200367.114"
+  wire $lt$libresoc.v:200367$14838_Y
+  attribute \src "libresoc.v:200369.19-200369.114"
+  wire $lt$libresoc.v:200369$14840_Y
+  attribute \src "libresoc.v:200371.19-200371.114"
+  wire $lt$libresoc.v:200371$14842_Y
+  attribute \src "libresoc.v:200374.19-200374.114"
+  wire $lt$libresoc.v:200374$14845_Y
+  attribute \src "libresoc.v:200408.18-200408.110"
+  wire $lt$libresoc.v:200408$14879_Y
+  attribute \src "libresoc.v:200410.18-200410.110"
+  wire $lt$libresoc.v:200410$14881_Y
+  attribute \src "libresoc.v:200412.18-200412.111"
+  wire $lt$libresoc.v:200412$14883_Y
+  attribute \src "libresoc.v:200414.18-200414.111"
+  wire $lt$libresoc.v:200414$14885_Y
+  attribute \src "libresoc.v:200417.18-200417.111"
+  wire $lt$libresoc.v:200417$14888_Y
+  attribute \src "libresoc.v:200419.18-200419.111"
+  wire $lt$libresoc.v:200419$14890_Y
+  attribute \src "libresoc.v:200406.18-200406.40"
+  wire width 16 $shr$libresoc.v:200406$14877_Y
+  attribute \src "libresoc.v:200318.17-200318.114"
+  wire width 8 $ternary$libresoc.v:200318$14789_Y
+  attribute \src "libresoc.v:200340.18-200340.116"
+  wire width 8 $ternary$libresoc.v:200340$14811_Y
+  attribute \src "libresoc.v:200362.18-200362.116"
+  wire width 8 $ternary$libresoc.v:200362$14833_Y
+  attribute \src "libresoc.v:200377.19-200377.118"
+  wire width 8 $ternary$libresoc.v:200377$14848_Y
   attribute \src "libresoc.v:200379.18-200379.116"
-  wire width 8 $ternary$libresoc.v:200379$14858_Y
-  attribute \src "libresoc.v:200382.18-200382.116"
-  wire width 8 $ternary$libresoc.v:200382$14861_Y
-  attribute \src "libresoc.v:200384.18-200384.116"
-  wire width 8 $ternary$libresoc.v:200384$14863_Y
-  attribute \src "libresoc.v:200386.18-200386.117"
-  wire width 8 $ternary$libresoc.v:200386$14865_Y
-  attribute \src "libresoc.v:200388.18-200388.117"
-  wire width 8 $ternary$libresoc.v:200388$14867_Y
-  attribute \src "libresoc.v:200390.18-200390.117"
-  wire width 8 $ternary$libresoc.v:200390$14869_Y
-  attribute \src "libresoc.v:200393.18-200393.117"
-  wire width 8 $ternary$libresoc.v:200393$14872_Y
-  attribute \src "libresoc.v:200395.18-200395.117"
-  wire width 8 $ternary$libresoc.v:200395$14874_Y
-  attribute \src "libresoc.v:200397.18-200397.117"
-  wire width 8 $ternary$libresoc.v:200397$14876_Y
+  wire width 8 $ternary$libresoc.v:200379$14850_Y
+  attribute \src "libresoc.v:200381.18-200381.116"
+  wire width 8 $ternary$libresoc.v:200381$14852_Y
+  attribute \src "libresoc.v:200383.18-200383.116"
+  wire width 8 $ternary$libresoc.v:200383$14854_Y
+  attribute \src "libresoc.v:200385.18-200385.116"
+  wire width 8 $ternary$libresoc.v:200385$14856_Y
+  attribute \src "libresoc.v:200387.18-200387.116"
+  wire width 8 $ternary$libresoc.v:200387$14858_Y
+  attribute \src "libresoc.v:200390.18-200390.116"
+  wire width 8 $ternary$libresoc.v:200390$14861_Y
+  attribute \src "libresoc.v:200392.18-200392.116"
+  wire width 8 $ternary$libresoc.v:200392$14863_Y
+  attribute \src "libresoc.v:200394.18-200394.117"
+  wire width 8 $ternary$libresoc.v:200394$14865_Y
+  attribute \src "libresoc.v:200396.18-200396.117"
+  wire width 8 $ternary$libresoc.v:200396$14867_Y
+  attribute \src "libresoc.v:200398.18-200398.117"
+  wire width 8 $ternary$libresoc.v:200398$14869_Y
+  attribute \src "libresoc.v:200401.18-200401.117"
+  wire width 8 $ternary$libresoc.v:200401$14872_Y
+  attribute \src "libresoc.v:200403.18-200403.117"
+  wire width 8 $ternary$libresoc.v:200403$14874_Y
+  attribute \src "libresoc.v:200405.18-200405.117"
+  wire width 8 $ternary$libresoc.v:200405$14876_Y
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
   wire \$1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
@@ -420604,7 +420612,7 @@ module \xics_ics
   wire width 32 \be_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308"
   wire width 32 \be_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 12 \clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
   wire width 4 \cur_idx0
@@ -420702,7 +420710,7 @@ module \xics_ics
   wire input 7 \ics_wb__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
   wire input 11 \ics_wb__we
-  attribute \src "libresoc.v:199911.7-199911.15"
+  attribute \src "libresoc.v:199919.7-199919.15"
   wire \initial
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
   wire width 16 input 5 \int_level_i
@@ -420722,7 +420730,7 @@ module \xics_ics
   wire \reg_is_debug
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286"
   wire \reg_is_xive
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447"
   wire input 1 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260"
   wire \wb_valid
@@ -420791,7 +420799,7 @@ module \xics_ics
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
   wire width 8 \xive9_pri$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200312$14791
+  cell $and $and$libresoc.v:200320$14791
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420799,10 +420807,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [3]
     connect \B \$99
-    connect \Y $and$libresoc.v:200312$14791_Y
+    connect \Y $and$libresoc.v:200320$14791_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200314$14793
+  cell $and $and$libresoc.v:200322$14793
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420810,10 +420818,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [3]
     connect \B \$103
-    connect \Y $and$libresoc.v:200314$14793_Y
+    connect \Y $and$libresoc.v:200322$14793_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200316$14795
+  cell $and $and$libresoc.v:200324$14795
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420821,10 +420829,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [4]
     connect \B \$107
-    connect \Y $and$libresoc.v:200316$14795_Y
+    connect \Y $and$libresoc.v:200324$14795_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200318$14797
+  cell $and $and$libresoc.v:200326$14797
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420832,10 +420840,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [4]
     connect \B \$111
-    connect \Y $and$libresoc.v:200318$14797_Y
+    connect \Y $and$libresoc.v:200326$14797_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200320$14799
+  cell $and $and$libresoc.v:200328$14799
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420843,10 +420851,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [5]
     connect \B \$115
-    connect \Y $and$libresoc.v:200320$14799_Y
+    connect \Y $and$libresoc.v:200328$14799_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200322$14801
+  cell $and $and$libresoc.v:200330$14801
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420854,10 +420862,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [5]
     connect \B \$119
-    connect \Y $and$libresoc.v:200322$14801_Y
+    connect \Y $and$libresoc.v:200330$14801_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200324$14803
+  cell $and $and$libresoc.v:200332$14803
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420865,10 +420873,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [6]
     connect \B \$123
-    connect \Y $and$libresoc.v:200324$14803_Y
+    connect \Y $and$libresoc.v:200332$14803_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200327$14806
+  cell $and $and$libresoc.v:200335$14806
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420876,10 +420884,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [6]
     connect \B \$127
-    connect \Y $and$libresoc.v:200327$14806_Y
+    connect \Y $and$libresoc.v:200335$14806_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200329$14808
+  cell $and $and$libresoc.v:200337$14808
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420887,10 +420895,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [7]
     connect \B \$131
-    connect \Y $and$libresoc.v:200329$14808_Y
+    connect \Y $and$libresoc.v:200337$14808_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200331$14810
+  cell $and $and$libresoc.v:200339$14810
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420898,10 +420906,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [7]
     connect \B \$135
-    connect \Y $and$libresoc.v:200331$14810_Y
+    connect \Y $and$libresoc.v:200339$14810_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200334$14813
+  cell $and $and$libresoc.v:200342$14813
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420909,10 +420917,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [8]
     connect \B \$139
-    connect \Y $and$libresoc.v:200334$14813_Y
+    connect \Y $and$libresoc.v:200342$14813_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200336$14815
+  cell $and $and$libresoc.v:200344$14815
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420920,10 +420928,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [8]
     connect \B \$143
-    connect \Y $and$libresoc.v:200336$14815_Y
+    connect \Y $and$libresoc.v:200344$14815_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200338$14817
+  cell $and $and$libresoc.v:200346$14817
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420931,10 +420939,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [9]
     connect \B \$147
-    connect \Y $and$libresoc.v:200338$14817_Y
+    connect \Y $and$libresoc.v:200346$14817_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200340$14819
+  cell $and $and$libresoc.v:200348$14819
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420942,10 +420950,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [9]
     connect \B \$151
-    connect \Y $and$libresoc.v:200340$14819_Y
+    connect \Y $and$libresoc.v:200348$14819_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200342$14821
+  cell $and $and$libresoc.v:200350$14821
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420953,10 +420961,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [10]
     connect \B \$155
-    connect \Y $and$libresoc.v:200342$14821_Y
+    connect \Y $and$libresoc.v:200350$14821_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200344$14823
+  cell $and $and$libresoc.v:200352$14823
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420964,10 +420972,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [10]
     connect \B \$159
-    connect \Y $and$libresoc.v:200344$14823_Y
+    connect \Y $and$libresoc.v:200352$14823_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200346$14825
+  cell $and $and$libresoc.v:200354$14825
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420975,10 +420983,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [11]
     connect \B \$163
-    connect \Y $and$libresoc.v:200346$14825_Y
+    connect \Y $and$libresoc.v:200354$14825_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200349$14828
+  cell $and $and$libresoc.v:200357$14828
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420986,10 +420994,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [11]
     connect \B \$167
-    connect \Y $and$libresoc.v:200349$14828_Y
+    connect \Y $and$libresoc.v:200357$14828_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200351$14830
+  cell $and $and$libresoc.v:200359$14830
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -420997,10 +421005,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [12]
     connect \B \$171
-    connect \Y $and$libresoc.v:200351$14830_Y
+    connect \Y $and$libresoc.v:200359$14830_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200353$14832
+  cell $and $and$libresoc.v:200361$14832
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421008,10 +421016,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [12]
     connect \B \$175
-    connect \Y $and$libresoc.v:200353$14832_Y
+    connect \Y $and$libresoc.v:200361$14832_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200356$14835
+  cell $and $and$libresoc.v:200364$14835
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421019,10 +421027,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [13]
     connect \B \$179
-    connect \Y $and$libresoc.v:200356$14835_Y
+    connect \Y $and$libresoc.v:200364$14835_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200358$14837
+  cell $and $and$libresoc.v:200366$14837
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421030,10 +421038,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [13]
     connect \B \$183
-    connect \Y $and$libresoc.v:200358$14837_Y
+    connect \Y $and$libresoc.v:200366$14837_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200360$14839
+  cell $and $and$libresoc.v:200368$14839
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421041,10 +421049,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [14]
     connect \B \$187
-    connect \Y $and$libresoc.v:200360$14839_Y
+    connect \Y $and$libresoc.v:200368$14839_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200362$14841
+  cell $and $and$libresoc.v:200370$14841
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421052,10 +421060,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [14]
     connect \B \$191
-    connect \Y $and$libresoc.v:200362$14841_Y
+    connect \Y $and$libresoc.v:200370$14841_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200364$14843
+  cell $and $and$libresoc.v:200372$14843
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421063,10 +421071,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [15]
     connect \B \$195
-    connect \Y $and$libresoc.v:200364$14843_Y
+    connect \Y $and$libresoc.v:200372$14843_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200367$14846
+  cell $and $and$libresoc.v:200375$14846
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421074,10 +421082,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [15]
     connect \B \$199
-    connect \Y $and$libresoc.v:200367$14846_Y
+    connect \Y $and$libresoc.v:200375$14846_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304"
-  cell $and $and$libresoc.v:200391$14870
+  cell $and $and$libresoc.v:200399$14870
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421085,10 +421093,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \ics_wb__cyc
     connect \B \ics_wb__stb
-    connect \Y $and$libresoc.v:200391$14870_Y
+    connect \Y $and$libresoc.v:200399$14870_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341"
-  cell $and $and$libresoc.v:200399$14878
+  cell $and $and$libresoc.v:200407$14878
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421096,10 +421104,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \wb_valid
     connect \B \ics_wb__we
-    connect \Y $and$libresoc.v:200399$14878_Y
+    connect \Y $and$libresoc.v:200407$14878_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200401$14880
+  cell $and $and$libresoc.v:200409$14880
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421107,10 +421115,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [0]
     connect \B \$75
-    connect \Y $and$libresoc.v:200401$14880_Y
+    connect \Y $and$libresoc.v:200409$14880_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200403$14882
+  cell $and $and$libresoc.v:200411$14882
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421118,10 +421126,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [0]
     connect \B \$79
-    connect \Y $and$libresoc.v:200403$14882_Y
+    connect \Y $and$libresoc.v:200411$14882_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200405$14884
+  cell $and $and$libresoc.v:200413$14884
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421129,10 +421137,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [1]
     connect \B \$83
-    connect \Y $and$libresoc.v:200405$14884_Y
+    connect \Y $and$libresoc.v:200413$14884_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200408$14887
+  cell $and $and$libresoc.v:200416$14887
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421140,10 +421148,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [1]
     connect \B \$87
-    connect \Y $and$libresoc.v:200408$14887_Y
+    connect \Y $and$libresoc.v:200416$14887_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200410$14889
+  cell $and $and$libresoc.v:200418$14889
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421151,10 +421159,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [2]
     connect \B \$91
-    connect \Y $and$libresoc.v:200410$14889_Y
+    connect \Y $and$libresoc.v:200418$14889_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
-  cell $and $and$libresoc.v:200412$14891
+  cell $and $and$libresoc.v:200420$14891
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -421162,10 +421170,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \int_level_l [2]
     connect \B \$95
-    connect \Y $and$libresoc.v:200412$14891_Y
+    connect \Y $and$libresoc.v:200420$14891_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200326$14805
+  cell $eq $eq$libresoc.v:200334$14805
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421173,10 +421181,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive1_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200326$14805_Y
+    connect \Y $eq$libresoc.v:200334$14805_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200348$14827
+  cell $eq $eq$libresoc.v:200356$14827
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421184,10 +421192,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive2_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200348$14827_Y
+    connect \Y $eq$libresoc.v:200356$14827_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
-  cell $eq $eq$libresoc.v:200365$14844
+  cell $eq $eq$libresoc.v:200373$14844
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \B_SIGNED 0
@@ -421195,10 +421203,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \ics_wb__adr [9:0]
     connect \B 1'0
-    connect \Y $eq$libresoc.v:200365$14844_Y
+    connect \Y $eq$libresoc.v:200373$14844_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200368$14847
+  cell $eq $eq$libresoc.v:200376$14847
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421206,10 +421214,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \cur_pri15
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200368$14847_Y
+    connect \Y $eq$libresoc.v:200376$14847_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200370$14849
+  cell $eq $eq$libresoc.v:200378$14849
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421217,10 +421225,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive3_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200370$14849_Y
+    connect \Y $eq$libresoc.v:200378$14849_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200372$14851
+  cell $eq $eq$libresoc.v:200380$14851
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421228,10 +421236,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive4_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200372$14851_Y
+    connect \Y $eq$libresoc.v:200380$14851_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200374$14853
+  cell $eq $eq$libresoc.v:200382$14853
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421239,10 +421247,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive5_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200374$14853_Y
+    connect \Y $eq$libresoc.v:200382$14853_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200376$14855
+  cell $eq $eq$libresoc.v:200384$14855
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421250,10 +421258,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive6_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200376$14855_Y
+    connect \Y $eq$libresoc.v:200384$14855_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200378$14857
+  cell $eq $eq$libresoc.v:200386$14857
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421261,10 +421269,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive7_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200378$14857_Y
+    connect \Y $eq$libresoc.v:200386$14857_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294"
-  cell $eq $eq$libresoc.v:200380$14859
+  cell $eq $eq$libresoc.v:200388$14859
     parameter \A_SIGNED 0
     parameter \A_WIDTH 10
     parameter \B_SIGNED 0
@@ -421272,10 +421280,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \ics_wb__adr [9:0]
     connect \B 3'100
-    connect \Y $eq$libresoc.v:200380$14859_Y
+    connect \Y $eq$libresoc.v:200388$14859_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200381$14860
+  cell $eq $eq$libresoc.v:200389$14860
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421283,10 +421291,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive8_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200381$14860_Y
+    connect \Y $eq$libresoc.v:200389$14860_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200383$14862
+  cell $eq $eq$libresoc.v:200391$14862
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421294,10 +421302,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive9_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200383$14862_Y
+    connect \Y $eq$libresoc.v:200391$14862_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200385$14864
+  cell $eq $eq$libresoc.v:200393$14864
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421305,10 +421313,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive10_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200385$14864_Y
+    connect \Y $eq$libresoc.v:200393$14864_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200387$14866
+  cell $eq $eq$libresoc.v:200395$14866
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421316,10 +421324,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive11_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200387$14866_Y
+    connect \Y $eq$libresoc.v:200395$14866_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200389$14868
+  cell $eq $eq$libresoc.v:200397$14868
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421327,10 +421335,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive12_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200389$14868_Y
+    connect \Y $eq$libresoc.v:200397$14868_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200392$14871
+  cell $eq $eq$libresoc.v:200400$14871
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421338,10 +421346,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive13_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200392$14871_Y
+    connect \Y $eq$libresoc.v:200400$14871_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200394$14873
+  cell $eq $eq$libresoc.v:200402$14873
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421349,10 +421357,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive14_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200394$14873_Y
+    connect \Y $eq$libresoc.v:200402$14873_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200396$14875
+  cell $eq $eq$libresoc.v:200404$14875
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421360,10 +421368,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive15_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200396$14875_Y
+    connect \Y $eq$libresoc.v:200404$14875_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $eq $eq$libresoc.v:200407$14886
+  cell $eq $eq$libresoc.v:200415$14886
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421371,10 +421379,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive0_pri
     connect \B 8'11111111
-    connect \Y $eq$libresoc.v:200407$14886_Y
+    connect \Y $eq$libresoc.v:200415$14886_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200311$14790
+  cell $lt $lt$libresoc.v:200319$14790
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421382,10 +421390,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive3_pri
     connect \B \cur_pri2
-    connect \Y $lt$libresoc.v:200311$14790_Y
+    connect \Y $lt$libresoc.v:200319$14790_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200313$14792
+  cell $lt $lt$libresoc.v:200321$14792
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421393,10 +421401,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive3_pri
     connect \B \cur_pri2
-    connect \Y $lt$libresoc.v:200313$14792_Y
+    connect \Y $lt$libresoc.v:200321$14792_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200315$14794
+  cell $lt $lt$libresoc.v:200323$14794
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421404,10 +421412,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive4_pri
     connect \B \cur_pri3
-    connect \Y $lt$libresoc.v:200315$14794_Y
+    connect \Y $lt$libresoc.v:200323$14794_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200317$14796
+  cell $lt $lt$libresoc.v:200325$14796
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421415,10 +421423,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive4_pri
     connect \B \cur_pri3
-    connect \Y $lt$libresoc.v:200317$14796_Y
+    connect \Y $lt$libresoc.v:200325$14796_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200319$14798
+  cell $lt $lt$libresoc.v:200327$14798
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421426,10 +421434,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive5_pri
     connect \B \cur_pri4
-    connect \Y $lt$libresoc.v:200319$14798_Y
+    connect \Y $lt$libresoc.v:200327$14798_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200321$14800
+  cell $lt $lt$libresoc.v:200329$14800
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421437,10 +421445,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive5_pri
     connect \B \cur_pri4
-    connect \Y $lt$libresoc.v:200321$14800_Y
+    connect \Y $lt$libresoc.v:200329$14800_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200323$14802
+  cell $lt $lt$libresoc.v:200331$14802
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421448,10 +421456,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive6_pri
     connect \B \cur_pri5
-    connect \Y $lt$libresoc.v:200323$14802_Y
+    connect \Y $lt$libresoc.v:200331$14802_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200325$14804
+  cell $lt $lt$libresoc.v:200333$14804
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421459,10 +421467,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive6_pri
     connect \B \cur_pri5
-    connect \Y $lt$libresoc.v:200325$14804_Y
+    connect \Y $lt$libresoc.v:200333$14804_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200328$14807
+  cell $lt $lt$libresoc.v:200336$14807
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421470,10 +421478,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive7_pri
     connect \B \cur_pri6
-    connect \Y $lt$libresoc.v:200328$14807_Y
+    connect \Y $lt$libresoc.v:200336$14807_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200330$14809
+  cell $lt $lt$libresoc.v:200338$14809
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421481,10 +421489,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive7_pri
     connect \B \cur_pri6
-    connect \Y $lt$libresoc.v:200330$14809_Y
+    connect \Y $lt$libresoc.v:200338$14809_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200333$14812
+  cell $lt $lt$libresoc.v:200341$14812
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421492,10 +421500,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive8_pri
     connect \B \cur_pri7
-    connect \Y $lt$libresoc.v:200333$14812_Y
+    connect \Y $lt$libresoc.v:200341$14812_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200335$14814
+  cell $lt $lt$libresoc.v:200343$14814
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421503,10 +421511,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive8_pri
     connect \B \cur_pri7
-    connect \Y $lt$libresoc.v:200335$14814_Y
+    connect \Y $lt$libresoc.v:200343$14814_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200337$14816
+  cell $lt $lt$libresoc.v:200345$14816
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421514,10 +421522,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive9_pri
     connect \B \cur_pri8
-    connect \Y $lt$libresoc.v:200337$14816_Y
+    connect \Y $lt$libresoc.v:200345$14816_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200339$14818
+  cell $lt $lt$libresoc.v:200347$14818
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421525,10 +421533,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive9_pri
     connect \B \cur_pri8
-    connect \Y $lt$libresoc.v:200339$14818_Y
+    connect \Y $lt$libresoc.v:200347$14818_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200341$14820
+  cell $lt $lt$libresoc.v:200349$14820
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421536,10 +421544,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive10_pri
     connect \B \cur_pri9
-    connect \Y $lt$libresoc.v:200341$14820_Y
+    connect \Y $lt$libresoc.v:200349$14820_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200343$14822
+  cell $lt $lt$libresoc.v:200351$14822
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421547,10 +421555,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive10_pri
     connect \B \cur_pri9
-    connect \Y $lt$libresoc.v:200343$14822_Y
+    connect \Y $lt$libresoc.v:200351$14822_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200345$14824
+  cell $lt $lt$libresoc.v:200353$14824
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421558,10 +421566,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive11_pri
     connect \B \cur_pri10
-    connect \Y $lt$libresoc.v:200345$14824_Y
+    connect \Y $lt$libresoc.v:200353$14824_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200347$14826
+  cell $lt $lt$libresoc.v:200355$14826
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421569,10 +421577,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive11_pri
     connect \B \cur_pri10
-    connect \Y $lt$libresoc.v:200347$14826_Y
+    connect \Y $lt$libresoc.v:200355$14826_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200350$14829
+  cell $lt $lt$libresoc.v:200358$14829
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421580,10 +421588,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive12_pri
     connect \B \cur_pri11
-    connect \Y $lt$libresoc.v:200350$14829_Y
+    connect \Y $lt$libresoc.v:200358$14829_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200352$14831
+  cell $lt $lt$libresoc.v:200360$14831
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421591,10 +421599,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive12_pri
     connect \B \cur_pri11
-    connect \Y $lt$libresoc.v:200352$14831_Y
+    connect \Y $lt$libresoc.v:200360$14831_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200355$14834
+  cell $lt $lt$libresoc.v:200363$14834
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421602,10 +421610,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive13_pri
     connect \B \cur_pri12
-    connect \Y $lt$libresoc.v:200355$14834_Y
+    connect \Y $lt$libresoc.v:200363$14834_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200357$14836
+  cell $lt $lt$libresoc.v:200365$14836
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421613,10 +421621,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive13_pri
     connect \B \cur_pri12
-    connect \Y $lt$libresoc.v:200357$14836_Y
+    connect \Y $lt$libresoc.v:200365$14836_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200359$14838
+  cell $lt $lt$libresoc.v:200367$14838
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421624,10 +421632,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive14_pri
     connect \B \cur_pri13
-    connect \Y $lt$libresoc.v:200359$14838_Y
+    connect \Y $lt$libresoc.v:200367$14838_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200361$14840
+  cell $lt $lt$libresoc.v:200369$14840
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421635,10 +421643,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive14_pri
     connect \B \cur_pri13
-    connect \Y $lt$libresoc.v:200361$14840_Y
+    connect \Y $lt$libresoc.v:200369$14840_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200363$14842
+  cell $lt $lt$libresoc.v:200371$14842
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421646,10 +421654,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive15_pri
     connect \B \cur_pri14
-    connect \Y $lt$libresoc.v:200363$14842_Y
+    connect \Y $lt$libresoc.v:200371$14842_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200366$14845
+  cell $lt $lt$libresoc.v:200374$14845
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421657,10 +421665,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive15_pri
     connect \B \cur_pri14
-    connect \Y $lt$libresoc.v:200366$14845_Y
+    connect \Y $lt$libresoc.v:200374$14845_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200400$14879
+  cell $lt $lt$libresoc.v:200408$14879
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421668,10 +421676,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive0_pri
     connect \B \max_pri
-    connect \Y $lt$libresoc.v:200400$14879_Y
+    connect \Y $lt$libresoc.v:200408$14879_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200402$14881
+  cell $lt $lt$libresoc.v:200410$14881
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421679,10 +421687,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive0_pri
     connect \B \max_pri
-    connect \Y $lt$libresoc.v:200402$14881_Y
+    connect \Y $lt$libresoc.v:200410$14881_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200404$14883
+  cell $lt $lt$libresoc.v:200412$14883
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421690,10 +421698,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive1_pri
     connect \B \cur_pri0
-    connect \Y $lt$libresoc.v:200404$14883_Y
+    connect \Y $lt$libresoc.v:200412$14883_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200406$14885
+  cell $lt $lt$libresoc.v:200414$14885
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421701,10 +421709,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive1_pri
     connect \B \cur_pri0
-    connect \Y $lt$libresoc.v:200406$14885_Y
+    connect \Y $lt$libresoc.v:200414$14885_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200409$14888
+  cell $lt $lt$libresoc.v:200417$14888
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421712,10 +421720,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive2_pri
     connect \B \cur_pri1
-    connect \Y $lt$libresoc.v:200409$14888_Y
+    connect \Y $lt$libresoc.v:200417$14888_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
-  cell $lt $lt$libresoc.v:200411$14890
+  cell $lt $lt$libresoc.v:200419$14890
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \B_SIGNED 0
@@ -421723,10 +421731,10 @@ module \xics_ics
     parameter \Y_WIDTH 1
     connect \A \xive2_pri
     connect \B \cur_pri1
-    connect \Y $lt$libresoc.v:200411$14890_Y
+    connect \Y $lt$libresoc.v:200419$14890_Y
   end
-  attribute \src "libresoc.v:200398.18-200398.40"
-  cell $shr $shr$libresoc.v:200398$14877
+  attribute \src "libresoc.v:200406.18-200406.40"
+  cell $shr $shr$libresoc.v:200406$14877
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
@@ -421734,469 +421742,469 @@ module \xics_ics
     parameter \Y_WIDTH 16
     connect \A \int_level_l
     connect \B \reg_idx
-    connect \Y $shr$libresoc.v:200398$14877_Y
+    connect \Y $shr$libresoc.v:200406$14877_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200310$14789
+  cell $mux $ternary$libresoc.v:200318$14789
     parameter \WIDTH 8
     connect \A \xive0_pri
     connect \B 8'11111111
     connect \S \$8
-    connect \Y $ternary$libresoc.v:200310$14789_Y
+    connect \Y $ternary$libresoc.v:200318$14789_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200332$14811
+  cell $mux $ternary$libresoc.v:200340$14811
     parameter \WIDTH 8
     connect \A \xive1_pri
     connect \B 8'11111111
     connect \S \$12
-    connect \Y $ternary$libresoc.v:200332$14811_Y
+    connect \Y $ternary$libresoc.v:200340$14811_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200354$14833
+  cell $mux $ternary$libresoc.v:200362$14833
     parameter \WIDTH 8
     connect \A \xive2_pri
     connect \B 8'11111111
     connect \S \$16
-    connect \Y $ternary$libresoc.v:200354$14833_Y
+    connect \Y $ternary$libresoc.v:200362$14833_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200369$14848
+  cell $mux $ternary$libresoc.v:200377$14848
     parameter \WIDTH 8
     connect \A \cur_pri15
     connect \B 8'11111111
     connect \S \$204
-    connect \Y $ternary$libresoc.v:200369$14848_Y
+    connect \Y $ternary$libresoc.v:200377$14848_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200371$14850
+  cell $mux $ternary$libresoc.v:200379$14850
     parameter \WIDTH 8
     connect \A \xive3_pri
     connect \B 8'11111111
     connect \S \$20
-    connect \Y $ternary$libresoc.v:200371$14850_Y
+    connect \Y $ternary$libresoc.v:200379$14850_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200373$14852
+  cell $mux $ternary$libresoc.v:200381$14852
     parameter \WIDTH 8
     connect \A \xive4_pri
     connect \B 8'11111111
     connect \S \$24
-    connect \Y $ternary$libresoc.v:200373$14852_Y
+    connect \Y $ternary$libresoc.v:200381$14852_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200375$14854
+  cell $mux $ternary$libresoc.v:200383$14854
     parameter \WIDTH 8
     connect \A \xive5_pri
     connect \B 8'11111111
     connect \S \$28
-    connect \Y $ternary$libresoc.v:200375$14854_Y
+    connect \Y $ternary$libresoc.v:200383$14854_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200377$14856
+  cell $mux $ternary$libresoc.v:200385$14856
     parameter \WIDTH 8
     connect \A \xive6_pri
     connect \B 8'11111111
     connect \S \$32
-    connect \Y $ternary$libresoc.v:200377$14856_Y
+    connect \Y $ternary$libresoc.v:200385$14856_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200379$14858
+  cell $mux $ternary$libresoc.v:200387$14858
     parameter \WIDTH 8
     connect \A \xive7_pri
     connect \B 8'11111111
     connect \S \$36
-    connect \Y $ternary$libresoc.v:200379$14858_Y
+    connect \Y $ternary$libresoc.v:200387$14858_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200382$14861
+  cell $mux $ternary$libresoc.v:200390$14861
     parameter \WIDTH 8
     connect \A \xive8_pri
     connect \B 8'11111111
     connect \S \$40
-    connect \Y $ternary$libresoc.v:200382$14861_Y
+    connect \Y $ternary$libresoc.v:200390$14861_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200384$14863
+  cell $mux $ternary$libresoc.v:200392$14863
     parameter \WIDTH 8
     connect \A \xive9_pri
     connect \B 8'11111111
     connect \S \$44
-    connect \Y $ternary$libresoc.v:200384$14863_Y
+    connect \Y $ternary$libresoc.v:200392$14863_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200386$14865
+  cell $mux $ternary$libresoc.v:200394$14865
     parameter \WIDTH 8
     connect \A \xive10_pri
     connect \B 8'11111111
     connect \S \$48
-    connect \Y $ternary$libresoc.v:200386$14865_Y
+    connect \Y $ternary$libresoc.v:200394$14865_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200388$14867
+  cell $mux $ternary$libresoc.v:200396$14867
     parameter \WIDTH 8
     connect \A \xive11_pri
     connect \B 8'11111111
     connect \S \$52
-    connect \Y $ternary$libresoc.v:200388$14867_Y
+    connect \Y $ternary$libresoc.v:200396$14867_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200390$14869
+  cell $mux $ternary$libresoc.v:200398$14869
     parameter \WIDTH 8
     connect \A \xive12_pri
     connect \B 8'11111111
     connect \S \$56
-    connect \Y $ternary$libresoc.v:200390$14869_Y
+    connect \Y $ternary$libresoc.v:200398$14869_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200393$14872
+  cell $mux $ternary$libresoc.v:200401$14872
     parameter \WIDTH 8
     connect \A \xive13_pri
     connect \B 8'11111111
     connect \S \$60
-    connect \Y $ternary$libresoc.v:200393$14872_Y
+    connect \Y $ternary$libresoc.v:200401$14872_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200395$14874
+  cell $mux $ternary$libresoc.v:200403$14874
     parameter \WIDTH 8
     connect \A \xive14_pri
     connect \B 8'11111111
     connect \S \$64
-    connect \Y $ternary$libresoc.v:200395$14874_Y
+    connect \Y $ternary$libresoc.v:200403$14874_Y
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
-  cell $mux $ternary$libresoc.v:200397$14876
+  cell $mux $ternary$libresoc.v:200405$14876
     parameter \WIDTH 8
     connect \A \xive15_pri
     connect \B 8'11111111
     connect \S \$68
-    connect \Y $ternary$libresoc.v:200397$14876_Y
+    connect \Y $ternary$libresoc.v:200405$14876_Y
   end
-  attribute \src "libresoc.v:199911.7-199911.20"
-  process $proc$libresoc.v:199911$15037
+  attribute \src "libresoc.v:199919.7-199919.20"
+  process $proc$libresoc.v:199919$15037
     assign { } { }
     assign $0\initial[0:0] 1'0
     sync always
       update \initial $0\initial[0:0]
     sync init
   end
-  attribute \src "libresoc.v:200192.13-200192.30"
-  process $proc$libresoc.v:200192$15038
+  attribute \src "libresoc.v:200200.13-200200.30"
+  process $proc$libresoc.v:200200$15038
     assign { } { }
     assign $1\icp_o_pri[7:0] 8'00000000
     sync always
     sync init
       update \icp_o_pri $1\icp_o_pri[7:0]
   end
-  attribute \src "libresoc.v:200197.13-200197.29"
-  process $proc$libresoc.v:200197$15039
+  attribute \src "libresoc.v:200205.13-200205.29"
+  process $proc$libresoc.v:200205$15039
     assign { } { }
     assign $1\icp_o_src[3:0] 4'0000
     sync always
     sync init
       update \icp_o_src $1\icp_o_src[3:0]
   end
-  attribute \src "libresoc.v:200206.7-200206.25"
-  process $proc$libresoc.v:200206$15040
+  attribute \src "libresoc.v:200214.7-200214.25"
+  process $proc$libresoc.v:200214$15040
     assign { } { }
     assign $1\ics_wb__ack[0:0] 1'0
     sync always
     sync init
       update \ics_wb__ack $1\ics_wb__ack[0:0]
   end
-  attribute \src "libresoc.v:200215.14-200215.35"
-  process $proc$libresoc.v:200215$15041
+  attribute \src "libresoc.v:200223.14-200223.35"
+  process $proc$libresoc.v:200223$15041
     assign { } { }
     assign $1\ics_wb__dat_r[31:0] 0
     sync always
     sync init
       update \ics_wb__dat_r $1\ics_wb__dat_r[31:0]
   end
-  attribute \src "libresoc.v:200227.14-200227.36"
-  process $proc$libresoc.v:200227$15042
+  attribute \src "libresoc.v:200235.14-200235.36"
+  process $proc$libresoc.v:200235$15042
     assign { } { }
     assign $1\int_level_l[15:0] 16'0000000000000000
     sync always
     sync init
       update \int_level_l $1\int_level_l[15:0]
   end
-  attribute \src "libresoc.v:200247.13-200247.30"
-  process $proc$libresoc.v:200247$15043
+  attribute \src "libresoc.v:200255.13-200255.30"
+  process $proc$libresoc.v:200255$15043
     assign { } { }
     assign $1\xive0_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive0_pri $1\xive0_pri[7:0]
   end
-  attribute \src "libresoc.v:200251.13-200251.31"
-  process $proc$libresoc.v:200251$15044
+  attribute \src "libresoc.v:200259.13-200259.31"
+  process $proc$libresoc.v:200259$15044
     assign { } { }
     assign $1\xive10_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive10_pri $1\xive10_pri[7:0]
   end
-  attribute \src "libresoc.v:200255.13-200255.31"
-  process $proc$libresoc.v:200255$15045
+  attribute \src "libresoc.v:200263.13-200263.31"
+  process $proc$libresoc.v:200263$15045
     assign { } { }
     assign $1\xive11_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive11_pri $1\xive11_pri[7:0]
   end
-  attribute \src "libresoc.v:200259.13-200259.31"
-  process $proc$libresoc.v:200259$15046
+  attribute \src "libresoc.v:200267.13-200267.31"
+  process $proc$libresoc.v:200267$15046
     assign { } { }
     assign $1\xive12_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive12_pri $1\xive12_pri[7:0]
   end
-  attribute \src "libresoc.v:200263.13-200263.31"
-  process $proc$libresoc.v:200263$15047
+  attribute \src "libresoc.v:200271.13-200271.31"
+  process $proc$libresoc.v:200271$15047
     assign { } { }
     assign $1\xive13_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive13_pri $1\xive13_pri[7:0]
   end
-  attribute \src "libresoc.v:200267.13-200267.31"
-  process $proc$libresoc.v:200267$15048
+  attribute \src "libresoc.v:200275.13-200275.31"
+  process $proc$libresoc.v:200275$15048
     assign { } { }
     assign $1\xive14_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive14_pri $1\xive14_pri[7:0]
   end
-  attribute \src "libresoc.v:200271.13-200271.31"
-  process $proc$libresoc.v:200271$15049
+  attribute \src "libresoc.v:200279.13-200279.31"
+  process $proc$libresoc.v:200279$15049
     assign { } { }
     assign $1\xive15_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive15_pri $1\xive15_pri[7:0]
   end
-  attribute \src "libresoc.v:200275.13-200275.30"
-  process $proc$libresoc.v:200275$15050
+  attribute \src "libresoc.v:200283.13-200283.30"
+  process $proc$libresoc.v:200283$15050
     assign { } { }
     assign $1\xive1_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive1_pri $1\xive1_pri[7:0]
   end
-  attribute \src "libresoc.v:200279.13-200279.30"
-  process $proc$libresoc.v:200279$15051
+  attribute \src "libresoc.v:200287.13-200287.30"
+  process $proc$libresoc.v:200287$15051
     assign { } { }
     assign $1\xive2_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive2_pri $1\xive2_pri[7:0]
   end
-  attribute \src "libresoc.v:200283.13-200283.30"
-  process $proc$libresoc.v:200283$15052
+  attribute \src "libresoc.v:200291.13-200291.30"
+  process $proc$libresoc.v:200291$15052
     assign { } { }
     assign $1\xive3_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive3_pri $1\xive3_pri[7:0]
   end
-  attribute \src "libresoc.v:200287.13-200287.30"
-  process $proc$libresoc.v:200287$15053
+  attribute \src "libresoc.v:200295.13-200295.30"
+  process $proc$libresoc.v:200295$15053
     assign { } { }
     assign $1\xive4_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive4_pri $1\xive4_pri[7:0]
   end
-  attribute \src "libresoc.v:200291.13-200291.30"
-  process $proc$libresoc.v:200291$15054
+  attribute \src "libresoc.v:200299.13-200299.30"
+  process $proc$libresoc.v:200299$15054
     assign { } { }
     assign $1\xive5_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive5_pri $1\xive5_pri[7:0]
   end
-  attribute \src "libresoc.v:200295.13-200295.30"
-  process $proc$libresoc.v:200295$15055
+  attribute \src "libresoc.v:200303.13-200303.30"
+  process $proc$libresoc.v:200303$15055
     assign { } { }
     assign $1\xive6_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive6_pri $1\xive6_pri[7:0]
   end
-  attribute \src "libresoc.v:200299.13-200299.30"
-  process $proc$libresoc.v:200299$15056
+  attribute \src "libresoc.v:200307.13-200307.30"
+  process $proc$libresoc.v:200307$15056
     assign { } { }
     assign $1\xive7_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive7_pri $1\xive7_pri[7:0]
   end
-  attribute \src "libresoc.v:200303.13-200303.30"
-  process $proc$libresoc.v:200303$15057
+  attribute \src "libresoc.v:200311.13-200311.30"
+  process $proc$libresoc.v:200311$15057
     assign { } { }
     assign $1\xive8_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive8_pri $1\xive8_pri[7:0]
   end
-  attribute \src "libresoc.v:200307.13-200307.30"
-  process $proc$libresoc.v:200307$15058
+  attribute \src "libresoc.v:200315.13-200315.30"
+  process $proc$libresoc.v:200315$15058
     assign { } { }
     assign $1\xive9_pri[7:0] 8'11111111
     sync always
     sync init
       update \xive9_pri $1\xive9_pri[7:0]
   end
-  attribute \src "libresoc.v:200413.3-200414.28"
-  process $proc$libresoc.v:200413$14892
+  attribute \src "libresoc.v:200421.3-200422.28"
+  process $proc$libresoc.v:200421$14892
     assign { } { }
     assign $0\icp_o_src[3:0] \cur_idx15
     sync posedge \clk
       update \icp_o_src $0\icp_o_src[3:0]
   end
-  attribute \src "libresoc.v:200415.3-200416.25"
-  process $proc$libresoc.v:200415$14893
+  attribute \src "libresoc.v:200423.3-200424.25"
+  process $proc$libresoc.v:200423$14893
     assign { } { }
     assign $0\icp_o_pri[7:0] \$203
     sync posedge \clk
       update \icp_o_pri $0\icp_o_pri[7:0]
   end
-  attribute \src "libresoc.v:200417.3-200418.35"
-  process $proc$libresoc.v:200417$14894
+  attribute \src "libresoc.v:200425.3-200426.35"
+  process $proc$libresoc.v:200425$14894
     assign { } { }
     assign $0\xive0_pri[7:0] \xive0_pri$next
     sync posedge \clk
       update \xive0_pri $0\xive0_pri[7:0]
   end
-  attribute \src "libresoc.v:200419.3-200420.35"
-  process $proc$libresoc.v:200419$14895
+  attribute \src "libresoc.v:200427.3-200428.35"
+  process $proc$libresoc.v:200427$14895
     assign { } { }
     assign $0\xive1_pri[7:0] \xive1_pri$next
     sync posedge \clk
       update \xive1_pri $0\xive1_pri[7:0]
   end
-  attribute \src "libresoc.v:200421.3-200422.35"
-  process $proc$libresoc.v:200421$14896
+  attribute \src "libresoc.v:200429.3-200430.35"
+  process $proc$libresoc.v:200429$14896
     assign { } { }
     assign $0\xive2_pri[7:0] \xive2_pri$next
     sync posedge \clk
       update \xive2_pri $0\xive2_pri[7:0]
   end
-  attribute \src "libresoc.v:200423.3-200424.35"
-  process $proc$libresoc.v:200423$14897
+  attribute \src "libresoc.v:200431.3-200432.35"
+  process $proc$libresoc.v:200431$14897
     assign { } { }
     assign $0\xive3_pri[7:0] \xive3_pri$next
     sync posedge \clk
       update \xive3_pri $0\xive3_pri[7:0]
   end
-  attribute \src "libresoc.v:200425.3-200426.35"
-  process $proc$libresoc.v:200425$14898
+  attribute \src "libresoc.v:200433.3-200434.35"
+  process $proc$libresoc.v:200433$14898
     assign { } { }
     assign $0\xive4_pri[7:0] \xive4_pri$next
     sync posedge \clk
       update \xive4_pri $0\xive4_pri[7:0]
   end
-  attribute \src "libresoc.v:200427.3-200428.35"
-  process $proc$libresoc.v:200427$14899
+  attribute \src "libresoc.v:200435.3-200436.35"
+  process $proc$libresoc.v:200435$14899
     assign { } { }
     assign $0\xive5_pri[7:0] \xive5_pri$next
     sync posedge \clk
       update \xive5_pri $0\xive5_pri[7:0]
   end
-  attribute \src "libresoc.v:200429.3-200430.35"
-  process $proc$libresoc.v:200429$14900
+  attribute \src "libresoc.v:200437.3-200438.35"
+  process $proc$libresoc.v:200437$14900
     assign { } { }
     assign $0\xive6_pri[7:0] \xive6_pri$next
     sync posedge \clk
       update \xive6_pri $0\xive6_pri[7:0]
   end
-  attribute \src "libresoc.v:200431.3-200432.35"
-  process $proc$libresoc.v:200431$14901
+  attribute \src "libresoc.v:200439.3-200440.35"
+  process $proc$libresoc.v:200439$14901
     assign { } { }
     assign $0\xive7_pri[7:0] \xive7_pri$next
     sync posedge \clk
       update \xive7_pri $0\xive7_pri[7:0]
   end
-  attribute \src "libresoc.v:200433.3-200434.35"
-  process $proc$libresoc.v:200433$14902
+  attribute \src "libresoc.v:200441.3-200442.35"
+  process $proc$libresoc.v:200441$14902
     assign { } { }
     assign $0\xive8_pri[7:0] \xive8_pri$next
     sync posedge \clk
       update \xive8_pri $0\xive8_pri[7:0]
   end
-  attribute \src "libresoc.v:200435.3-200436.35"
-  process $proc$libresoc.v:200435$14903
+  attribute \src "libresoc.v:200443.3-200444.35"
+  process $proc$libresoc.v:200443$14903
     assign { } { }
     assign $0\xive9_pri[7:0] \xive9_pri$next
     sync posedge \clk
       update \xive9_pri $0\xive9_pri[7:0]
   end
-  attribute \src "libresoc.v:200437.3-200438.37"
-  process $proc$libresoc.v:200437$14904
+  attribute \src "libresoc.v:200445.3-200446.37"
+  process $proc$libresoc.v:200445$14904
     assign { } { }
     assign $0\xive10_pri[7:0] \xive10_pri$next
     sync posedge \clk
       update \xive10_pri $0\xive10_pri[7:0]
   end
-  attribute \src "libresoc.v:200439.3-200440.37"
-  process $proc$libresoc.v:200439$14905
+  attribute \src "libresoc.v:200447.3-200448.37"
+  process $proc$libresoc.v:200447$14905
     assign { } { }
     assign $0\xive11_pri[7:0] \xive11_pri$next
     sync posedge \clk
       update \xive11_pri $0\xive11_pri[7:0]
   end
-  attribute \src "libresoc.v:200441.3-200442.37"
-  process $proc$libresoc.v:200441$14906
+  attribute \src "libresoc.v:200449.3-200450.37"
+  process $proc$libresoc.v:200449$14906
     assign { } { }
     assign $0\xive12_pri[7:0] \xive12_pri$next
     sync posedge \clk
       update \xive12_pri $0\xive12_pri[7:0]
   end
-  attribute \src "libresoc.v:200443.3-200444.37"
-  process $proc$libresoc.v:200443$14907
+  attribute \src "libresoc.v:200451.3-200452.37"
+  process $proc$libresoc.v:200451$14907
     assign { } { }
     assign $0\xive13_pri[7:0] \xive13_pri$next
     sync posedge \clk
       update \xive13_pri $0\xive13_pri[7:0]
   end
-  attribute \src "libresoc.v:200445.3-200446.37"
-  process $proc$libresoc.v:200445$14908
+  attribute \src "libresoc.v:200453.3-200454.37"
+  process $proc$libresoc.v:200453$14908
     assign { } { }
     assign $0\xive14_pri[7:0] \xive14_pri$next
     sync posedge \clk
       update \xive14_pri $0\xive14_pri[7:0]
   end
-  attribute \src "libresoc.v:200447.3-200448.37"
-  process $proc$libresoc.v:200447$14909
+  attribute \src "libresoc.v:200455.3-200456.37"
+  process $proc$libresoc.v:200455$14909
     assign { } { }
     assign $0\xive15_pri[7:0] \xive15_pri$next
     sync posedge \clk
       update \xive15_pri $0\xive15_pri[7:0]
   end
-  attribute \src "libresoc.v:200449.3-200450.39"
-  process $proc$libresoc.v:200449$14910
+  attribute \src "libresoc.v:200457.3-200458.39"
+  process $proc$libresoc.v:200457$14910
     assign { } { }
     assign $0\ics_wb__ack[0:0] \ics_wb__ack$next
     sync posedge \clk
       update \ics_wb__ack $0\ics_wb__ack[0:0]
   end
-  attribute \src "libresoc.v:200451.3-200452.43"
-  process $proc$libresoc.v:200451$14911
+  attribute \src "libresoc.v:200459.3-200460.43"
+  process $proc$libresoc.v:200459$14911
     assign { } { }
     assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next
     sync posedge \clk
       update \ics_wb__dat_r $0\ics_wb__dat_r[31:0]
   end
-  attribute \src "libresoc.v:200453.3-200454.39"
-  process $proc$libresoc.v:200453$14912
+  attribute \src "libresoc.v:200461.3-200462.39"
+  process $proc$libresoc.v:200461$14912
     assign { } { }
     assign $0\int_level_l[15:0] \int_level_l$next
     sync posedge \clk
       update \int_level_l $0\int_level_l[15:0]
   end
-  attribute \src "libresoc.v:200455.3-200540.6"
-  process $proc$libresoc.v:200455$14913
+  attribute \src "libresoc.v:200463.3-200548.6"
+  process $proc$libresoc.v:200463$14913
     assign { } { }
     assign { } { }
     assign { } { }
@@ -422261,9 +422269,9 @@ module \xics_ics
     assign $0\xive7_pri$next[7:0]$14927 $4\xive7_pri$next[7:0]$14991
     assign $0\xive8_pri$next[7:0]$14928 $4\xive8_pri$next[7:0]$14992
     assign $0\xive9_pri$next[7:0]$14929 $4\xive9_pri$next[7:0]$14993
-    attribute \src "libresoc.v:200456.5-200456.29"
+    attribute \src "libresoc.v:200464.5-200464.29"
     switch \initial
-      attribute \src "libresoc.v:200456.9-200456.17"
+      attribute \src "libresoc.v:200464.9-200464.17"
       case 1'1
       case 
     end
@@ -422771,14 +422779,14 @@ module \xics_ics
       update \xive8_pri$next $0\xive8_pri$next[7:0]$14928
       update \xive9_pri$next $0\xive9_pri$next[7:0]$14929
   end
-  attribute \src "libresoc.v:200541.3-200550.6"
-  process $proc$libresoc.v:200541$14994
+  attribute \src "libresoc.v:200549.3-200558.6"
+  process $proc$libresoc.v:200549$14994
     assign { } { }
     assign { } { }
     assign $0\cur_pri0[7:0] $1\cur_pri0[7:0]
-    attribute \src "libresoc.v:200542.5-200542.29"
+    attribute \src "libresoc.v:200550.5-200550.29"
     switch \initial
-      attribute \src "libresoc.v:200542.9-200542.17"
+      attribute \src "libresoc.v:200550.9-200550.17"
       case 1'1
       case 
     end
@@ -422794,14 +422802,14 @@ module \xics_ics
     sync always
       update \cur_pri0 $0\cur_pri0[7:0]
   end
-  attribute \src "libresoc.v:200551.3-200560.6"
-  process $proc$libresoc.v:200551$14995
+  attribute \src "libresoc.v:200559.3-200568.6"
+  process $proc$libresoc.v:200559$14995
     assign { } { }
     assign { } { }
     assign $0\cur_idx0[3:0] $1\cur_idx0[3:0]
-    attribute \src "libresoc.v:200552.5-200552.29"
+    attribute \src "libresoc.v:200560.5-200560.29"
     switch \initial
-      attribute \src "libresoc.v:200552.9-200552.17"
+      attribute \src "libresoc.v:200560.9-200560.17"
       case 1'1
       case 
     end
@@ -422817,14 +422825,14 @@ module \xics_ics
     sync always
       update \cur_idx0 $0\cur_idx0[3:0]
   end
-  attribute \src "libresoc.v:200561.3-200570.6"
-  process $proc$libresoc.v:200561$14996
+  attribute \src "libresoc.v:200569.3-200578.6"
+  process $proc$libresoc.v:200569$14996
     assign { } { }
     assign { } { }
     assign $0\cur_pri1[7:0] $1\cur_pri1[7:0]
-    attribute \src "libresoc.v:200562.5-200562.29"
+    attribute \src "libresoc.v:200570.5-200570.29"
     switch \initial
-      attribute \src "libresoc.v:200562.9-200562.17"
+      attribute \src "libresoc.v:200570.9-200570.17"
       case 1'1
       case 
     end
@@ -422840,14 +422848,14 @@ module \xics_ics
     sync always
       update \cur_pri1 $0\cur_pri1[7:0]
   end
-  attribute \src "libresoc.v:200571.3-200580.6"
-  process $proc$libresoc.v:200571$14997
+  attribute \src "libresoc.v:200579.3-200588.6"
+  process $proc$libresoc.v:200579$14997
     assign { } { }
     assign { } { }
     assign $0\cur_idx1[3:0] $1\cur_idx1[3:0]
-    attribute \src "libresoc.v:200572.5-200572.29"
+    attribute \src "libresoc.v:200580.5-200580.29"
     switch \initial
-      attribute \src "libresoc.v:200572.9-200572.17"
+      attribute \src "libresoc.v:200580.9-200580.17"
       case 1'1
       case 
     end
@@ -422863,14 +422871,14 @@ module \xics_ics
     sync always
       update \cur_idx1 $0\cur_idx1[3:0]
   end
-  attribute \src "libresoc.v:200581.3-200590.6"
-  process $proc$libresoc.v:200581$14998
+  attribute \src "libresoc.v:200589.3-200598.6"
+  process $proc$libresoc.v:200589$14998
     assign { } { }
     assign { } { }
     assign $0\cur_pri2[7:0] $1\cur_pri2[7:0]
-    attribute \src "libresoc.v:200582.5-200582.29"
+    attribute \src "libresoc.v:200590.5-200590.29"
     switch \initial
-      attribute \src "libresoc.v:200582.9-200582.17"
+      attribute \src "libresoc.v:200590.9-200590.17"
       case 1'1
       case 
     end
@@ -422886,14 +422894,14 @@ module \xics_ics
     sync always
       update \cur_pri2 $0\cur_pri2[7:0]
   end
-  attribute \src "libresoc.v:200591.3-200600.6"
-  process $proc$libresoc.v:200591$14999
+  attribute \src "libresoc.v:200599.3-200608.6"
+  process $proc$libresoc.v:200599$14999
     assign { } { }
     assign { } { }
     assign $0\cur_idx2[3:0] $1\cur_idx2[3:0]
-    attribute \src "libresoc.v:200592.5-200592.29"
+    attribute \src "libresoc.v:200600.5-200600.29"
     switch \initial
-      attribute \src "libresoc.v:200592.9-200592.17"
+      attribute \src "libresoc.v:200600.9-200600.17"
       case 1'1
       case 
     end
@@ -422909,14 +422917,14 @@ module \xics_ics
     sync always
       update \cur_idx2 $0\cur_idx2[3:0]
   end
-  attribute \src "libresoc.v:200601.3-200610.6"
-  process $proc$libresoc.v:200601$15000
+  attribute \src "libresoc.v:200609.3-200618.6"
+  process $proc$libresoc.v:200609$15000
     assign { } { }
     assign { } { }
     assign $0\cur_pri3[7:0] $1\cur_pri3[7:0]
-    attribute \src "libresoc.v:200602.5-200602.29"
+    attribute \src "libresoc.v:200610.5-200610.29"
     switch \initial
-      attribute \src "libresoc.v:200602.9-200602.17"
+      attribute \src "libresoc.v:200610.9-200610.17"
       case 1'1
       case 
     end
@@ -422932,14 +422940,14 @@ module \xics_ics
     sync always
       update \cur_pri3 $0\cur_pri3[7:0]
   end
-  attribute \src "libresoc.v:200611.3-200620.6"
-  process $proc$libresoc.v:200611$15001
+  attribute \src "libresoc.v:200619.3-200628.6"
+  process $proc$libresoc.v:200619$15001
     assign { } { }
     assign { } { }
     assign $0\cur_idx3[3:0] $1\cur_idx3[3:0]
-    attribute \src "libresoc.v:200612.5-200612.29"
+    attribute \src "libresoc.v:200620.5-200620.29"
     switch \initial
-      attribute \src "libresoc.v:200612.9-200612.17"
+      attribute \src "libresoc.v:200620.9-200620.17"
       case 1'1
       case 
     end
@@ -422955,14 +422963,14 @@ module \xics_ics
     sync always
       update \cur_idx3 $0\cur_idx3[3:0]
   end
-  attribute \src "libresoc.v:200621.3-200630.6"
-  process $proc$libresoc.v:200621$15002
+  attribute \src "libresoc.v:200629.3-200638.6"
+  process $proc$libresoc.v:200629$15002
     assign { } { }
     assign { } { }
     assign $0\cur_pri4[7:0] $1\cur_pri4[7:0]
-    attribute \src "libresoc.v:200622.5-200622.29"
+    attribute \src "libresoc.v:200630.5-200630.29"
     switch \initial
-      attribute \src "libresoc.v:200622.9-200622.17"
+      attribute \src "libresoc.v:200630.9-200630.17"
       case 1'1
       case 
     end
@@ -422978,14 +422986,14 @@ module \xics_ics
     sync always
       update \cur_pri4 $0\cur_pri4[7:0]
   end
-  attribute \src "libresoc.v:200631.3-200639.6"
-  process $proc$libresoc.v:200631$15003
+  attribute \src "libresoc.v:200639.3-200647.6"
+  process $proc$libresoc.v:200639$15003
     assign { } { }
     assign { } { }
     assign $0\int_level_l$next[15:0]$15004 $1\int_level_l$next[15:0]$15005
-    attribute \src "libresoc.v:200632.5-200632.29"
+    attribute \src "libresoc.v:200640.5-200640.29"
     switch \initial
-      attribute \src "libresoc.v:200632.9-200632.17"
+      attribute \src "libresoc.v:200640.9-200640.17"
       case 1'1
       case 
     end
@@ -423001,14 +423009,14 @@ module \xics_ics
     sync always
       update \int_level_l$next $0\int_level_l$next[15:0]$15004
   end
-  attribute \src "libresoc.v:200640.3-200649.6"
-  process $proc$libresoc.v:200640$15006
+  attribute \src "libresoc.v:200648.3-200657.6"
+  process $proc$libresoc.v:200648$15006
     assign { } { }
     assign { } { }
     assign $0\cur_idx4[3:0] $1\cur_idx4[3:0]
-    attribute \src "libresoc.v:200641.5-200641.29"
+    attribute \src "libresoc.v:200649.5-200649.29"
     switch \initial
-      attribute \src "libresoc.v:200641.9-200641.17"
+      attribute \src "libresoc.v:200649.9-200649.17"
       case 1'1
       case 
     end
@@ -423024,14 +423032,14 @@ module \xics_ics
     sync always
       update \cur_idx4 $0\cur_idx4[3:0]
   end
-  attribute \src "libresoc.v:200650.3-200659.6"
-  process $proc$libresoc.v:200650$15007
+  attribute \src "libresoc.v:200658.3-200667.6"
+  process $proc$libresoc.v:200658$15007
     assign { } { }
     assign { } { }
     assign $0\cur_pri5[7:0] $1\cur_pri5[7:0]
-    attribute \src "libresoc.v:200651.5-200651.29"
+    attribute \src "libresoc.v:200659.5-200659.29"
     switch \initial
-      attribute \src "libresoc.v:200651.9-200651.17"
+      attribute \src "libresoc.v:200659.9-200659.17"
       case 1'1
       case 
     end
@@ -423047,14 +423055,14 @@ module \xics_ics
     sync always
       update \cur_pri5 $0\cur_pri5[7:0]
   end
-  attribute \src "libresoc.v:200660.3-200669.6"
-  process $proc$libresoc.v:200660$15008
+  attribute \src "libresoc.v:200668.3-200677.6"
+  process $proc$libresoc.v:200668$15008
     assign { } { }
     assign { } { }
     assign $0\cur_idx5[3:0] $1\cur_idx5[3:0]
-    attribute \src "libresoc.v:200661.5-200661.29"
+    attribute \src "libresoc.v:200669.5-200669.29"
     switch \initial
-      attribute \src "libresoc.v:200661.9-200661.17"
+      attribute \src "libresoc.v:200669.9-200669.17"
       case 1'1
       case 
     end
@@ -423070,14 +423078,14 @@ module \xics_ics
     sync always
       update \cur_idx5 $0\cur_idx5[3:0]
   end
-  attribute \src "libresoc.v:200670.3-200679.6"
-  process $proc$libresoc.v:200670$15009
+  attribute \src "libresoc.v:200678.3-200687.6"
+  process $proc$libresoc.v:200678$15009
     assign { } { }
     assign { } { }
     assign $0\cur_pri6[7:0] $1\cur_pri6[7:0]
-    attribute \src "libresoc.v:200671.5-200671.29"
+    attribute \src "libresoc.v:200679.5-200679.29"
     switch \initial
-      attribute \src "libresoc.v:200671.9-200671.17"
+      attribute \src "libresoc.v:200679.9-200679.17"
       case 1'1
       case 
     end
@@ -423093,14 +423101,14 @@ module \xics_ics
     sync always
       update \cur_pri6 $0\cur_pri6[7:0]
   end
-  attribute \src "libresoc.v:200680.3-200689.6"
-  process $proc$libresoc.v:200680$15010
+  attribute \src "libresoc.v:200688.3-200697.6"
+  process $proc$libresoc.v:200688$15010
     assign { } { }
     assign { } { }
     assign $0\cur_idx6[3:0] $1\cur_idx6[3:0]
-    attribute \src "libresoc.v:200681.5-200681.29"
+    attribute \src "libresoc.v:200689.5-200689.29"
     switch \initial
-      attribute \src "libresoc.v:200681.9-200681.17"
+      attribute \src "libresoc.v:200689.9-200689.17"
       case 1'1
       case 
     end
@@ -423116,14 +423124,14 @@ module \xics_ics
     sync always
       update \cur_idx6 $0\cur_idx6[3:0]
   end
-  attribute \src "libresoc.v:200690.3-200699.6"
-  process $proc$libresoc.v:200690$15011
+  attribute \src "libresoc.v:200698.3-200707.6"
+  process $proc$libresoc.v:200698$15011
     assign { } { }
     assign { } { }
     assign $0\cur_pri7[7:0] $1\cur_pri7[7:0]
-    attribute \src "libresoc.v:200691.5-200691.29"
+    attribute \src "libresoc.v:200699.5-200699.29"
     switch \initial
-      attribute \src "libresoc.v:200691.9-200691.17"
+      attribute \src "libresoc.v:200699.9-200699.17"
       case 1'1
       case 
     end
@@ -423139,14 +423147,14 @@ module \xics_ics
     sync always
       update \cur_pri7 $0\cur_pri7[7:0]
   end
-  attribute \src "libresoc.v:200700.3-200709.6"
-  process $proc$libresoc.v:200700$15012
+  attribute \src "libresoc.v:200708.3-200717.6"
+  process $proc$libresoc.v:200708$15012
     assign { } { }
     assign { } { }
     assign $0\cur_idx7[3:0] $1\cur_idx7[3:0]
-    attribute \src "libresoc.v:200701.5-200701.29"
+    attribute \src "libresoc.v:200709.5-200709.29"
     switch \initial
-      attribute \src "libresoc.v:200701.9-200701.17"
+      attribute \src "libresoc.v:200709.9-200709.17"
       case 1'1
       case 
     end
@@ -423162,14 +423170,14 @@ module \xics_ics
     sync always
       update \cur_idx7 $0\cur_idx7[3:0]
   end
-  attribute \src "libresoc.v:200710.3-200719.6"
-  process $proc$libresoc.v:200710$15013
+  attribute \src "libresoc.v:200718.3-200727.6"
+  process $proc$libresoc.v:200718$15013
     assign { } { }
     assign { } { }
     assign $0\cur_pri8[7:0] $1\cur_pri8[7:0]
-    attribute \src "libresoc.v:200711.5-200711.29"
+    attribute \src "libresoc.v:200719.5-200719.29"
     switch \initial
-      attribute \src "libresoc.v:200711.9-200711.17"
+      attribute \src "libresoc.v:200719.9-200719.17"
       case 1'1
       case 
     end
@@ -423185,14 +423193,14 @@ module \xics_ics
     sync always
       update \cur_pri8 $0\cur_pri8[7:0]
   end
-  attribute \src "libresoc.v:200720.3-200729.6"
-  process $proc$libresoc.v:200720$15014
+  attribute \src "libresoc.v:200728.3-200737.6"
+  process $proc$libresoc.v:200728$15014
     assign { } { }
     assign { } { }
     assign $0\cur_idx8[3:0] $1\cur_idx8[3:0]
-    attribute \src "libresoc.v:200721.5-200721.29"
+    attribute \src "libresoc.v:200729.5-200729.29"
     switch \initial
-      attribute \src "libresoc.v:200721.9-200721.17"
+      attribute \src "libresoc.v:200729.9-200729.17"
       case 1'1
       case 
     end
@@ -423208,14 +423216,14 @@ module \xics_ics
     sync always
       update \cur_idx8 $0\cur_idx8[3:0]
   end
-  attribute \src "libresoc.v:200730.3-200739.6"
-  process $proc$libresoc.v:200730$15015
+  attribute \src "libresoc.v:200738.3-200747.6"
+  process $proc$libresoc.v:200738$15015
     assign { } { }
     assign { } { }
     assign $0\cur_pri9[7:0] $1\cur_pri9[7:0]
-    attribute \src "libresoc.v:200731.5-200731.29"
+    attribute \src "libresoc.v:200739.5-200739.29"
     switch \initial
-      attribute \src "libresoc.v:200731.9-200731.17"
+      attribute \src "libresoc.v:200739.9-200739.17"
       case 1'1
       case 
     end
@@ -423231,14 +423239,14 @@ module \xics_ics
     sync always
       update \cur_pri9 $0\cur_pri9[7:0]
   end
-  attribute \src "libresoc.v:200740.3-200749.6"
-  process $proc$libresoc.v:200740$15016
+  attribute \src "libresoc.v:200748.3-200757.6"
+  process $proc$libresoc.v:200748$15016
     assign { } { }
     assign { } { }
     assign $0\cur_idx9[3:0] $1\cur_idx9[3:0]
-    attribute \src "libresoc.v:200741.5-200741.29"
+    attribute \src "libresoc.v:200749.5-200749.29"
     switch \initial
-      attribute \src "libresoc.v:200741.9-200741.17"
+      attribute \src "libresoc.v:200749.9-200749.17"
       case 1'1
       case 
     end
@@ -423254,14 +423262,14 @@ module \xics_ics
     sync always
       update \cur_idx9 $0\cur_idx9[3:0]
   end
-  attribute \src "libresoc.v:200750.3-200759.6"
-  process $proc$libresoc.v:200750$15017
+  attribute \src "libresoc.v:200758.3-200767.6"
+  process $proc$libresoc.v:200758$15017
     assign { } { }
     assign { } { }
     assign $0\cur_pri10[7:0] $1\cur_pri10[7:0]
-    attribute \src "libresoc.v:200751.5-200751.29"
+    attribute \src "libresoc.v:200759.5-200759.29"
     switch \initial
-      attribute \src "libresoc.v:200751.9-200751.17"
+      attribute \src "libresoc.v:200759.9-200759.17"
       case 1'1
       case 
     end
@@ -423277,14 +423285,14 @@ module \xics_ics
     sync always
       update \cur_pri10 $0\cur_pri10[7:0]
   end
-  attribute \src "libresoc.v:200760.3-200769.6"
-  process $proc$libresoc.v:200760$15018
+  attribute \src "libresoc.v:200768.3-200777.6"
+  process $proc$libresoc.v:200768$15018
     assign { } { }
     assign { } { }
     assign $0\cur_idx10[3:0] $1\cur_idx10[3:0]
-    attribute \src "libresoc.v:200761.5-200761.29"
+    attribute \src "libresoc.v:200769.5-200769.29"
     switch \initial
-      attribute \src "libresoc.v:200761.9-200761.17"
+      attribute \src "libresoc.v:200769.9-200769.17"
       case 1'1
       case 
     end
@@ -423300,14 +423308,14 @@ module \xics_ics
     sync always
       update \cur_idx10 $0\cur_idx10[3:0]
   end
-  attribute \src "libresoc.v:200770.3-200779.6"
-  process $proc$libresoc.v:200770$15019
+  attribute \src "libresoc.v:200778.3-200787.6"
+  process $proc$libresoc.v:200778$15019
     assign { } { }
     assign { } { }
     assign $0\cur_pri11[7:0] $1\cur_pri11[7:0]
-    attribute \src "libresoc.v:200771.5-200771.29"
+    attribute \src "libresoc.v:200779.5-200779.29"
     switch \initial
-      attribute \src "libresoc.v:200771.9-200771.17"
+      attribute \src "libresoc.v:200779.9-200779.17"
       case 1'1
       case 
     end
@@ -423323,14 +423331,14 @@ module \xics_ics
     sync always
       update \cur_pri11 $0\cur_pri11[7:0]
   end
-  attribute \src "libresoc.v:200780.3-200789.6"
-  process $proc$libresoc.v:200780$15020
+  attribute \src "libresoc.v:200788.3-200797.6"
+  process $proc$libresoc.v:200788$15020
     assign { } { }
     assign { } { }
     assign $0\cur_idx11[3:0] $1\cur_idx11[3:0]
-    attribute \src "libresoc.v:200781.5-200781.29"
+    attribute \src "libresoc.v:200789.5-200789.29"
     switch \initial
-      attribute \src "libresoc.v:200781.9-200781.17"
+      attribute \src "libresoc.v:200789.9-200789.17"
       case 1'1
       case 
     end
@@ -423346,14 +423354,14 @@ module \xics_ics
     sync always
       update \cur_idx11 $0\cur_idx11[3:0]
   end
-  attribute \src "libresoc.v:200790.3-200799.6"
-  process $proc$libresoc.v:200790$15021
+  attribute \src "libresoc.v:200798.3-200807.6"
+  process $proc$libresoc.v:200798$15021
     assign { } { }
     assign { } { }
     assign $0\cur_pri12[7:0] $1\cur_pri12[7:0]
-    attribute \src "libresoc.v:200791.5-200791.29"
+    attribute \src "libresoc.v:200799.5-200799.29"
     switch \initial
-      attribute \src "libresoc.v:200791.9-200791.17"
+      attribute \src "libresoc.v:200799.9-200799.17"
       case 1'1
       case 
     end
@@ -423369,14 +423377,14 @@ module \xics_ics
     sync always
       update \cur_pri12 $0\cur_pri12[7:0]
   end
-  attribute \src "libresoc.v:200800.3-200809.6"
-  process $proc$libresoc.v:200800$15022
+  attribute \src "libresoc.v:200808.3-200817.6"
+  process $proc$libresoc.v:200808$15022
     assign { } { }
     assign { } { }
     assign $0\cur_idx12[3:0] $1\cur_idx12[3:0]
-    attribute \src "libresoc.v:200801.5-200801.29"
+    attribute \src "libresoc.v:200809.5-200809.29"
     switch \initial
-      attribute \src "libresoc.v:200801.9-200801.17"
+      attribute \src "libresoc.v:200809.9-200809.17"
       case 1'1
       case 
     end
@@ -423392,14 +423400,14 @@ module \xics_ics
     sync always
       update \cur_idx12 $0\cur_idx12[3:0]
   end
-  attribute \src "libresoc.v:200810.3-200819.6"
-  process $proc$libresoc.v:200810$15023
+  attribute \src "libresoc.v:200818.3-200827.6"
+  process $proc$libresoc.v:200818$15023
     assign { } { }
     assign { } { }
     assign $0\cur_pri13[7:0] $1\cur_pri13[7:0]
-    attribute \src "libresoc.v:200811.5-200811.29"
+    attribute \src "libresoc.v:200819.5-200819.29"
     switch \initial
-      attribute \src "libresoc.v:200811.9-200811.17"
+      attribute \src "libresoc.v:200819.9-200819.17"
       case 1'1
       case 
     end
@@ -423415,14 +423423,14 @@ module \xics_ics
     sync always
       update \cur_pri13 $0\cur_pri13[7:0]
   end
-  attribute \src "libresoc.v:200820.3-200829.6"
-  process $proc$libresoc.v:200820$15024
+  attribute \src "libresoc.v:200828.3-200837.6"
+  process $proc$libresoc.v:200828$15024
     assign { } { }
     assign { } { }
     assign $0\cur_idx13[3:0] $1\cur_idx13[3:0]
-    attribute \src "libresoc.v:200821.5-200821.29"
+    attribute \src "libresoc.v:200829.5-200829.29"
     switch \initial
-      attribute \src "libresoc.v:200821.9-200821.17"
+      attribute \src "libresoc.v:200829.9-200829.17"
       case 1'1
       case 
     end
@@ -423438,14 +423446,14 @@ module \xics_ics
     sync always
       update \cur_idx13 $0\cur_idx13[3:0]
   end
-  attribute \src "libresoc.v:200830.3-200839.6"
-  process $proc$libresoc.v:200830$15025
+  attribute \src "libresoc.v:200838.3-200847.6"
+  process $proc$libresoc.v:200838$15025
     assign { } { }
     assign { } { }
     assign $0\cur_pri14[7:0] $1\cur_pri14[7:0]
-    attribute \src "libresoc.v:200831.5-200831.29"
+    attribute \src "libresoc.v:200839.5-200839.29"
     switch \initial
-      attribute \src "libresoc.v:200831.9-200831.17"
+      attribute \src "libresoc.v:200839.9-200839.17"
       case 1'1
       case 
     end
@@ -423461,14 +423469,14 @@ module \xics_ics
     sync always
       update \cur_pri14 $0\cur_pri14[7:0]
   end
-  attribute \src "libresoc.v:200840.3-200889.6"
-  process $proc$libresoc.v:200840$15026
+  attribute \src "libresoc.v:200848.3-200897.6"
+  process $proc$libresoc.v:200848$15026
     assign { } { }
     assign { } { }
     assign $0\be_out[31:0] $1\be_out[31:0]
-    attribute \src "libresoc.v:200841.5-200841.29"
+    attribute \src "libresoc.v:200849.5-200849.29"
     switch \initial
-      attribute \src "libresoc.v:200841.9-200841.17"
+      attribute \src "libresoc.v:200849.9-200849.17"
       case 1'1
       case 
     end
@@ -423561,14 +423569,14 @@ module \xics_ics
     sync always
       update \be_out $0\be_out[31:0]
   end
-  attribute \src "libresoc.v:200890.3-200899.6"
-  process $proc$libresoc.v:200890$15027
+  attribute \src "libresoc.v:200898.3-200907.6"
+  process $proc$libresoc.v:200898$15027
     assign { } { }
     assign { } { }
     assign $0\cur_idx14[3:0] $1\cur_idx14[3:0]
-    attribute \src "libresoc.v:200891.5-200891.29"
+    attribute \src "libresoc.v:200899.5-200899.29"
     switch \initial
-      attribute \src "libresoc.v:200891.9-200891.17"
+      attribute \src "libresoc.v:200899.9-200899.17"
       case 1'1
       case 
     end
@@ -423584,14 +423592,14 @@ module \xics_ics
     sync always
       update \cur_idx14 $0\cur_idx14[3:0]
   end
-  attribute \src "libresoc.v:200900.3-200909.6"
-  process $proc$libresoc.v:200900$15028
+  attribute \src "libresoc.v:200908.3-200917.6"
+  process $proc$libresoc.v:200908$15028
     assign { } { }
     assign { } { }
     assign $0\cur_pri15[7:0] $1\cur_pri15[7:0]
-    attribute \src "libresoc.v:200901.5-200901.29"
+    attribute \src "libresoc.v:200909.5-200909.29"
     switch \initial
-      attribute \src "libresoc.v:200901.9-200901.17"
+      attribute \src "libresoc.v:200909.9-200909.17"
       case 1'1
       case 
     end
@@ -423607,14 +423615,14 @@ module \xics_ics
     sync always
       update \cur_pri15 $0\cur_pri15[7:0]
   end
-  attribute \src "libresoc.v:200910.3-200919.6"
-  process $proc$libresoc.v:200910$15029
+  attribute \src "libresoc.v:200918.3-200927.6"
+  process $proc$libresoc.v:200918$15029
     assign { } { }
     assign { } { }
     assign $0\cur_idx15[3:0] $1\cur_idx15[3:0]
-    attribute \src "libresoc.v:200911.5-200911.29"
+    attribute \src "libresoc.v:200919.5-200919.29"
     switch \initial
-      attribute \src "libresoc.v:200911.9-200911.17"
+      attribute \src "libresoc.v:200919.9-200919.17"
       case 1'1
       case 
     end
@@ -423630,14 +423638,14 @@ module \xics_ics
     sync always
       update \cur_idx15 $0\cur_idx15[3:0]
   end
-  attribute \src "libresoc.v:200920.3-200929.6"
-  process $proc$libresoc.v:200920$15030
+  attribute \src "libresoc.v:200928.3-200937.6"
+  process $proc$libresoc.v:200928$15030
     assign { } { }
     assign { } { }
     assign $0\ibit[0:0] $1\ibit[0:0]
-    attribute \src "libresoc.v:200921.5-200921.29"
+    attribute \src "libresoc.v:200929.5-200929.29"
     switch \initial
-      attribute \src "libresoc.v:200921.9-200921.17"
+      attribute \src "libresoc.v:200929.9-200929.17"
       case 1'1
       case 
     end
@@ -423653,14 +423661,14 @@ module \xics_ics
     sync always
       update \ibit $0\ibit[0:0]
   end
-  attribute \src "libresoc.v:200930.3-200938.6"
-  process $proc$libresoc.v:200930$15031
+  attribute \src "libresoc.v:200938.3-200946.6"
+  process $proc$libresoc.v:200938$15031
     assign { } { }
     assign { } { }
     assign $0\ics_wb__dat_r$next[31:0]$15032 $1\ics_wb__dat_r$next[31:0]$15033
-    attribute \src "libresoc.v:200931.5-200931.29"
+    attribute \src "libresoc.v:200939.5-200939.29"
     switch \initial
-      attribute \src "libresoc.v:200931.9-200931.17"
+      attribute \src "libresoc.v:200939.9-200939.17"
       case 1'1
       case 
     end
@@ -423676,14 +423684,14 @@ module \xics_ics
     sync always
       update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$15032
   end
-  attribute \src "libresoc.v:200939.3-200947.6"
-  process $proc$libresoc.v:200939$15034
+  attribute \src "libresoc.v:200947.3-200955.6"
+  process $proc$libresoc.v:200947$15034
     assign { } { }
     assign { } { }
     assign $0\ics_wb__ack$next[0:0]$15035 $1\ics_wb__ack$next[0:0]$15036
-    attribute \src "libresoc.v:200940.5-200940.29"
+    attribute \src "libresoc.v:200948.5-200948.29"
     switch \initial
-      attribute \src "libresoc.v:200940.9-200940.17"
+      attribute \src "libresoc.v:200948.9-200948.17"
       case 1'1
       case 
     end
@@ -423699,109 +423707,109 @@ module \xics_ics
     sync always
       update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$15035
   end
-  connect \$7 $ternary$libresoc.v:200310$14789_Y
-  connect \$99 $lt$libresoc.v:200311$14790_Y
-  connect \$101 $and$libresoc.v:200312$14791_Y
-  connect \$103 $lt$libresoc.v:200313$14792_Y
-  connect \$105 $and$libresoc.v:200314$14793_Y
-  connect \$107 $lt$libresoc.v:200315$14794_Y
-  connect \$109 $and$libresoc.v:200316$14795_Y
-  connect \$111 $lt$libresoc.v:200317$14796_Y
-  connect \$113 $and$libresoc.v:200318$14797_Y
-  connect \$115 $lt$libresoc.v:200319$14798_Y
-  connect \$117 $and$libresoc.v:200320$14799_Y
-  connect \$119 $lt$libresoc.v:200321$14800_Y
-  connect \$121 $and$libresoc.v:200322$14801_Y
-  connect \$123 $lt$libresoc.v:200323$14802_Y
-  connect \$125 $and$libresoc.v:200324$14803_Y
-  connect \$127 $lt$libresoc.v:200325$14804_Y
-  connect \$12 $eq$libresoc.v:200326$14805_Y
-  connect \$129 $and$libresoc.v:200327$14806_Y
-  connect \$131 $lt$libresoc.v:200328$14807_Y
-  connect \$133 $and$libresoc.v:200329$14808_Y
-  connect \$135 $lt$libresoc.v:200330$14809_Y
-  connect \$137 $and$libresoc.v:200331$14810_Y
-  connect \$11 $ternary$libresoc.v:200332$14811_Y
-  connect \$139 $lt$libresoc.v:200333$14812_Y
-  connect \$141 $and$libresoc.v:200334$14813_Y
-  connect \$143 $lt$libresoc.v:200335$14814_Y
-  connect \$145 $and$libresoc.v:200336$14815_Y
-  connect \$147 $lt$libresoc.v:200337$14816_Y
-  connect \$149 $and$libresoc.v:200338$14817_Y
-  connect \$151 $lt$libresoc.v:200339$14818_Y
-  connect \$153 $and$libresoc.v:200340$14819_Y
-  connect \$155 $lt$libresoc.v:200341$14820_Y
-  connect \$157 $and$libresoc.v:200342$14821_Y
-  connect \$159 $lt$libresoc.v:200343$14822_Y
-  connect \$161 $and$libresoc.v:200344$14823_Y
-  connect \$163 $lt$libresoc.v:200345$14824_Y
-  connect \$165 $and$libresoc.v:200346$14825_Y
-  connect \$167 $lt$libresoc.v:200347$14826_Y
-  connect \$16 $eq$libresoc.v:200348$14827_Y
-  connect \$169 $and$libresoc.v:200349$14828_Y
-  connect \$171 $lt$libresoc.v:200350$14829_Y
-  connect \$173 $and$libresoc.v:200351$14830_Y
-  connect \$175 $lt$libresoc.v:200352$14831_Y
-  connect \$177 $and$libresoc.v:200353$14832_Y
-  connect \$15 $ternary$libresoc.v:200354$14833_Y
-  connect \$179 $lt$libresoc.v:200355$14834_Y
-  connect \$181 $and$libresoc.v:200356$14835_Y
-  connect \$183 $lt$libresoc.v:200357$14836_Y
-  connect \$185 $and$libresoc.v:200358$14837_Y
-  connect \$187 $lt$libresoc.v:200359$14838_Y
-  connect \$189 $and$libresoc.v:200360$14839_Y
-  connect \$191 $lt$libresoc.v:200361$14840_Y
-  connect \$193 $and$libresoc.v:200362$14841_Y
-  connect \$195 $lt$libresoc.v:200363$14842_Y
-  connect \$197 $and$libresoc.v:200364$14843_Y
-  connect \$1 $eq$libresoc.v:200365$14844_Y
-  connect \$199 $lt$libresoc.v:200366$14845_Y
-  connect \$201 $and$libresoc.v:200367$14846_Y
-  connect \$204 $eq$libresoc.v:200368$14847_Y
-  connect \$203 $ternary$libresoc.v:200369$14848_Y
-  connect \$20 $eq$libresoc.v:200370$14849_Y
-  connect \$19 $ternary$libresoc.v:200371$14850_Y
-  connect \$24 $eq$libresoc.v:200372$14851_Y
-  connect \$23 $ternary$libresoc.v:200373$14852_Y
-  connect \$28 $eq$libresoc.v:200374$14853_Y
-  connect \$27 $ternary$libresoc.v:200375$14854_Y
-  connect \$32 $eq$libresoc.v:200376$14855_Y
-  connect \$31 $ternary$libresoc.v:200377$14856_Y
-  connect \$36 $eq$libresoc.v:200378$14857_Y
-  connect \$35 $ternary$libresoc.v:200379$14858_Y
-  connect \$3 $eq$libresoc.v:200380$14859_Y
-  connect \$40 $eq$libresoc.v:200381$14860_Y
-  connect \$39 $ternary$libresoc.v:200382$14861_Y
-  connect \$44 $eq$libresoc.v:200383$14862_Y
-  connect \$43 $ternary$libresoc.v:200384$14863_Y
-  connect \$48 $eq$libresoc.v:200385$14864_Y
-  connect \$47 $ternary$libresoc.v:200386$14865_Y
-  connect \$52 $eq$libresoc.v:200387$14866_Y
-  connect \$51 $ternary$libresoc.v:200388$14867_Y
-  connect \$56 $eq$libresoc.v:200389$14868_Y
-  connect \$55 $ternary$libresoc.v:200390$14869_Y
-  connect \$5 $and$libresoc.v:200391$14870_Y
-  connect \$60 $eq$libresoc.v:200392$14871_Y
-  connect \$59 $ternary$libresoc.v:200393$14872_Y
-  connect \$64 $eq$libresoc.v:200394$14873_Y
-  connect \$63 $ternary$libresoc.v:200395$14874_Y
-  connect \$68 $eq$libresoc.v:200396$14875_Y
-  connect \$67 $ternary$libresoc.v:200397$14876_Y
-  connect \$71 $shr$libresoc.v:200398$14877_Y [0]
-  connect \$73 $and$libresoc.v:200399$14878_Y
-  connect \$75 $lt$libresoc.v:200400$14879_Y
-  connect \$77 $and$libresoc.v:200401$14880_Y
-  connect \$79 $lt$libresoc.v:200402$14881_Y
-  connect \$81 $and$libresoc.v:200403$14882_Y
-  connect \$83 $lt$libresoc.v:200404$14883_Y
-  connect \$85 $and$libresoc.v:200405$14884_Y
-  connect \$87 $lt$libresoc.v:200406$14885_Y
-  connect \$8 $eq$libresoc.v:200407$14886_Y
-  connect \$89 $and$libresoc.v:200408$14887_Y
-  connect \$91 $lt$libresoc.v:200409$14888_Y
-  connect \$93 $and$libresoc.v:200410$14889_Y
-  connect \$95 $lt$libresoc.v:200411$14890_Y
-  connect \$97 $and$libresoc.v:200412$14891_Y
+  connect \$7 $ternary$libresoc.v:200318$14789_Y
+  connect \$99 $lt$libresoc.v:200319$14790_Y
+  connect \$101 $and$libresoc.v:200320$14791_Y
+  connect \$103 $lt$libresoc.v:200321$14792_Y
+  connect \$105 $and$libresoc.v:200322$14793_Y
+  connect \$107 $lt$libresoc.v:200323$14794_Y
+  connect \$109 $and$libresoc.v:200324$14795_Y
+  connect \$111 $lt$libresoc.v:200325$14796_Y
+  connect \$113 $and$libresoc.v:200326$14797_Y
+  connect \$115 $lt$libresoc.v:200327$14798_Y
+  connect \$117 $and$libresoc.v:200328$14799_Y
+  connect \$119 $lt$libresoc.v:200329$14800_Y
+  connect \$121 $and$libresoc.v:200330$14801_Y
+  connect \$123 $lt$libresoc.v:200331$14802_Y
+  connect \$125 $and$libresoc.v:200332$14803_Y
+  connect \$127 $lt$libresoc.v:200333$14804_Y
+  connect \$12 $eq$libresoc.v:200334$14805_Y
+  connect \$129 $and$libresoc.v:200335$14806_Y
+  connect \$131 $lt$libresoc.v:200336$14807_Y
+  connect \$133 $and$libresoc.v:200337$14808_Y
+  connect \$135 $lt$libresoc.v:200338$14809_Y
+  connect \$137 $and$libresoc.v:200339$14810_Y
+  connect \$11 $ternary$libresoc.v:200340$14811_Y
+  connect \$139 $lt$libresoc.v:200341$14812_Y
+  connect \$141 $and$libresoc.v:200342$14813_Y
+  connect \$143 $lt$libresoc.v:200343$14814_Y
+  connect \$145 $and$libresoc.v:200344$14815_Y
+  connect \$147 $lt$libresoc.v:200345$14816_Y
+  connect \$149 $and$libresoc.v:200346$14817_Y
+  connect \$151 $lt$libresoc.v:200347$14818_Y
+  connect \$153 $and$libresoc.v:200348$14819_Y
+  connect \$155 $lt$libresoc.v:200349$14820_Y
+  connect \$157 $and$libresoc.v:200350$14821_Y
+  connect \$159 $lt$libresoc.v:200351$14822_Y
+  connect \$161 $and$libresoc.v:200352$14823_Y
+  connect \$163 $lt$libresoc.v:200353$14824_Y
+  connect \$165 $and$libresoc.v:200354$14825_Y
+  connect \$167 $lt$libresoc.v:200355$14826_Y
+  connect \$16 $eq$libresoc.v:200356$14827_Y
+  connect \$169 $and$libresoc.v:200357$14828_Y
+  connect \$171 $lt$libresoc.v:200358$14829_Y
+  connect \$173 $and$libresoc.v:200359$14830_Y
+  connect \$175 $lt$libresoc.v:200360$14831_Y
+  connect \$177 $and$libresoc.v:200361$14832_Y
+  connect \$15 $ternary$libresoc.v:200362$14833_Y
+  connect \$179 $lt$libresoc.v:200363$14834_Y
+  connect \$181 $and$libresoc.v:200364$14835_Y
+  connect \$183 $lt$libresoc.v:200365$14836_Y
+  connect \$185 $and$libresoc.v:200366$14837_Y
+  connect \$187 $lt$libresoc.v:200367$14838_Y
+  connect \$189 $and$libresoc.v:200368$14839_Y
+  connect \$191 $lt$libresoc.v:200369$14840_Y
+  connect \$193 $and$libresoc.v:200370$14841_Y
+  connect \$195 $lt$libresoc.v:200371$14842_Y
+  connect \$197 $and$libresoc.v:200372$14843_Y
+  connect \$1 $eq$libresoc.v:200373$14844_Y
+  connect \$199 $lt$libresoc.v:200374$14845_Y
+  connect \$201 $and$libresoc.v:200375$14846_Y
+  connect \$204 $eq$libresoc.v:200376$14847_Y
+  connect \$203 $ternary$libresoc.v:200377$14848_Y
+  connect \$20 $eq$libresoc.v:200378$14849_Y
+  connect \$19 $ternary$libresoc.v:200379$14850_Y
+  connect \$24 $eq$libresoc.v:200380$14851_Y
+  connect \$23 $ternary$libresoc.v:200381$14852_Y
+  connect \$28 $eq$libresoc.v:200382$14853_Y
+  connect \$27 $ternary$libresoc.v:200383$14854_Y
+  connect \$32 $eq$libresoc.v:200384$14855_Y
+  connect \$31 $ternary$libresoc.v:200385$14856_Y
+  connect \$36 $eq$libresoc.v:200386$14857_Y
+  connect \$35 $ternary$libresoc.v:200387$14858_Y
+  connect \$3 $eq$libresoc.v:200388$14859_Y
+  connect \$40 $eq$libresoc.v:200389$14860_Y
+  connect \$39 $ternary$libresoc.v:200390$14861_Y
+  connect \$44 $eq$libresoc.v:200391$14862_Y
+  connect \$43 $ternary$libresoc.v:200392$14863_Y
+  connect \$48 $eq$libresoc.v:200393$14864_Y
+  connect \$47 $ternary$libresoc.v:200394$14865_Y
+  connect \$52 $eq$libresoc.v:200395$14866_Y
+  connect \$51 $ternary$libresoc.v:200396$14867_Y
+  connect \$56 $eq$libresoc.v:200397$14868_Y
+  connect \$55 $ternary$libresoc.v:200398$14869_Y
+  connect \$5 $and$libresoc.v:200399$14870_Y
+  connect \$60 $eq$libresoc.v:200400$14871_Y
+  connect \$59 $ternary$libresoc.v:200401$14872_Y
+  connect \$64 $eq$libresoc.v:200402$14873_Y
+  connect \$63 $ternary$libresoc.v:200403$14874_Y
+  connect \$68 $eq$libresoc.v:200404$14875_Y
+  connect \$67 $ternary$libresoc.v:200405$14876_Y
+  connect \$71 $shr$libresoc.v:200406$14877_Y [0]
+  connect \$73 $and$libresoc.v:200407$14878_Y
+  connect \$75 $lt$libresoc.v:200408$14879_Y
+  connect \$77 $and$libresoc.v:200409$14880_Y
+  connect \$79 $lt$libresoc.v:200410$14881_Y
+  connect \$81 $and$libresoc.v:200411$14882_Y
+  connect \$83 $lt$libresoc.v:200412$14883_Y
+  connect \$85 $and$libresoc.v:200413$14884_Y
+  connect \$87 $lt$libresoc.v:200414$14885_Y
+  connect \$8 $eq$libresoc.v:200415$14886_Y
+  connect \$89 $and$libresoc.v:200416$14887_Y
+  connect \$91 $lt$libresoc.v:200417$14888_Y
+  connect \$93 $and$libresoc.v:200418$14889_Y
+  connect \$95 $lt$libresoc.v:200419$14890_Y
+  connect \$97 $and$libresoc.v:200420$14891_Y
   connect \icp_r_pri \$203
   connect \icp_r_src \cur_idx15
   connect \max_idx 4'0000
-- 
2.30.2