From 8ec43aad2185d0e14b4fc35fb43a828b93b53ce0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 6 Jul 2020 19:49:49 +0100 Subject: [PATCH] investigating mul pipeline --- src/soc/fu/mul/pipe_data.py | 2 +- src/soc/fu/mul/post_stage.py | 10 ++++------ src/soc/fu/mul/pre_stage.py | 3 ++- src/soc/fu/mul/test/test_pipe_caller.py | 11 ++++++++++- 4 files changed, 17 insertions(+), 9 deletions(-) diff --git a/src/soc/fu/mul/pipe_data.py b/src/soc/fu/mul/pipe_data.py index 1d047bb8..1b37b484 100644 --- a/src/soc/fu/mul/pipe_data.py +++ b/src/soc/fu/mul/pipe_data.py @@ -19,7 +19,7 @@ class MulOutputData(IntegerData): ('XER', 'xer_so', '32'), # XER bit 32: SO ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32 def __init__(self, pspec): - super().__init__(pspec, False) + super().__init__(pspec, False) # still input style self.neg_res = Signal(reset_less=True) self.neg_res32 = Signal(reset_less=True) diff --git a/src/soc/fu/mul/post_stage.py b/src/soc/fu/mul/post_stage.py index f2464085..e8e099bb 100644 --- a/src/soc/fu/mul/post_stage.py +++ b/src/soc/fu/mul/post_stage.py @@ -32,10 +32,8 @@ class MulMainStage3(PipeModBase): comb += is_32bit.eq(op.is_32bit) # check negate: select signed/unsigned - o_s = Signal(signed(o.data.width * 2), reset_less=True) - mul_o = Signal(o.data.width * 2, reset_less=True) - comb += o_s.eq(-o_i) - comb += mul_o.eq(Mux(self.i.neg_res, o_s, o_i)) + mul_o = Signal(o_i.width, reset_less=True) + comb += mul_o.eq(Mux(self.i.neg_res, -o_i, o_i)) comb += o.ok.eq(1) with m.Switch(op.insn_type): @@ -67,8 +65,8 @@ class MulMainStage3(PipeModBase): # https://bugs.libre-soc.org/show_bug.cgi?id=319#c5 ca = Signal(2, reset_less=True) - comb += ca[0].eq(mul_o[-1]) # XER.CA - comb += ca[1].eq(mul_o[33] ^ (self.i.neg_res32)) # XER.CA32 + comb += ca[0].eq(mul_o[-1]) # XER.CA - XXX more? + comb += ca[1].eq(mul_o[32] ^ (self.i.neg_res32)) # XER.CA32 comb += cry_o.data.eq(ca) comb += cry_o.ok.eq(1) diff --git a/src/soc/fu/mul/pre_stage.py b/src/soc/fu/mul/pre_stage.py index 3ce2f933..84363090 100644 --- a/src/soc/fu/mul/pre_stage.py +++ b/src/soc/fu/mul/pre_stage.py @@ -1,4 +1,5 @@ -# This stage is intended to do most of the work of executing multiply +# This stage is intended to prepare the multiplication operands + from nmigen import (Module, Signal, Mux) from nmutil.pipemodbase import PipeModBase from soc.fu.alu.pipe_data import ALUInputData diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py index 5fa0779d..38e29a6a 100644 --- a/src/soc/fu/mul/test/test_pipe_caller.py +++ b/src/soc/fu/mul/test/test_pipe_caller.py @@ -77,7 +77,16 @@ class MulTestCase(FHDLTestCase): tc = TestCase(prog, self.test_name, initial_regs, initial_sprs) self.test_data.append(tc) - def test_rand_mullw(self): + def test_mullw(self): + lst = [f"mullw 3, 1, 2"] + initial_regs = [0] * 32 + #initial_regs[1] = 0xffffffffffffffff + #initial_regs[2] = 0xffffffffffffffff + initial_regs[1] = 0x2ffffffff + initial_regs[2] = 0x2 + self.run_tst_program(Program(lst), initial_regs) + + def tst_rand_mullw(self): insns = ["mullw", "mullw.", "mullwo", "mullwo."] for i in range(40): choice = random.choice(insns) -- 2.30.2