From 8ed0ce9982d3a3ae3317d5fa44b96b391f58c385 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Thu, 11 Jun 2009 21:27:34 -0700 Subject: [PATCH] i386.c (OPTION_MASK_ISA_CRC32_SET): New. gcc/ 2009-06-11 H.J. Lu * config/i386/i386.c (OPTION_MASK_ISA_CRC32_SET): New. (OPTION_MASK_ISA_CRC32_UNSET): Likewise. (ix86_handle_option): Handle OPT_mcrc32. (ix86_target_string): Add -mcrc32. (bdesc_args): Enable crc32 builtins with OPTION_MASK_ISA_CRC32. * config/i386/i386.h (TARGET_CRC32): New. * config/i386/i386.md (sse4_2_crc32): Also check TARGET_CRC32. (sse4_2_crc32di): Likewise. * config/i386/i386.opt (mcrc32: New. * doc/invoke.texi: Document -mcrc32. gcc/testsuite/ 2009-06-11 H.J. Lu * gcc.target/i386/crc32-1.c: New. * gcc.target/i386/crc32-2.c: Likewise. From-SVN: r148410 --- gcc/ChangeLog | 28 ++++++++++++++++++++----- gcc/config/i386/i386.c | 24 +++++++++++++++++---- gcc/config/i386/i386.h | 1 + gcc/config/i386/i386.md | 4 ++-- gcc/config/i386/i386.opt | 4 ++++ gcc/doc/invoke.texi | 8 ++++++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/i386/crc32-1.c | 23 ++++++++++++++++++++ gcc/testsuite/gcc.target/i386/crc32-2.c | 9 ++++++++ 9 files changed, 94 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/crc32-1.c create mode 100644 gcc/testsuite/gcc.target/i386/crc32-2.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d15b23b3727..8ced87250c5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,24 @@ +2009-06-11 H.J. Lu + + * config/i386/i386.c (OPTION_MASK_ISA_CRC32_SET): New. + (OPTION_MASK_ISA_CRC32_UNSET): Likewise. + (ix86_handle_option): Handle OPT_mcrc32. + (ix86_target_string): Add -mcrc32. + (bdesc_args): Enable crc32 builtins with OPTION_MASK_ISA_CRC32. + + * config/i386/i386.h (TARGET_CRC32): New. + + * config/i386/i386.md (sse4_2_crc32): Also check + TARGET_CRC32. + (sse4_2_crc32di): Likewise. + + * config/i386/i386.opt (mcrc32: New. + + * doc/invoke.texi: Document -mcrc32. + 2009-06-11 Richard Henderson - * common.opt (gdwarf-): Accept a version number. + * common.opt (gdwarf-): Accept a version number. * doc/invoke.texi (gdwarf-): Update docs. * opth-gen.awk: Special case -gdwarf+ to OPT_gdwarfplus. * opts.c (common_handle_option) [OPT_gdwarf_]: Verify dwarf @@ -238,9 +256,9 @@ 2009-06-09 Ghassan Shobaki - * tree-ssa-loop-prefetch.c - (loop_prefetch_arrays): Fixed a portability problem in printf format - string. + * tree-ssa-loop-prefetch.c + (loop_prefetch_arrays): Fixed a portability problem in printf format + string. 2009-06-09 Martin Jambor @@ -300,7 +318,7 @@ compute_builtin_object_size. 2009-06-08 Ghassan Shobaki - Dwarakanath Rajagopal + Dwarakanath Rajagopal * tree-ssa-loop-prefetch.c (gather_memory_references): Introduced a counter for the number of diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 0bab4632468..ec335762d16 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1970,6 +1970,7 @@ static int ix86_isa_flags_explicit; #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE +#define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32 /* Define a set of ISAs which aren't available when a given ISA is disabled. MMX and SSE ISAs are handled separately. */ @@ -2012,6 +2013,7 @@ static int ix86_isa_flags_explicit; #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE +#define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32 /* Vectorization library interface and handlers. */ tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL; @@ -2315,6 +2317,19 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value) } return true; + case OPT_mcrc32: + if (value) + { + ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET; + ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET; + } + else + { + ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET; + ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET; + } + return true; + case OPT_maes: if (value) { @@ -2378,6 +2393,7 @@ ix86_target_string (int isa, int flags, const char *arch, const char *tune, { "-mabm", OPTION_MASK_ISA_ABM }, { "-mpopcnt", OPTION_MASK_ISA_POPCNT }, { "-mmovbe", OPTION_MASK_ISA_MOVBE }, + { "-mcrc32", OPTION_MASK_ISA_CRC32 }, { "-maes", OPTION_MASK_ISA_AES }, { "-mpclmul", OPTION_MASK_ISA_PCLMUL }, }; @@ -22178,10 +22194,10 @@ static const struct builtin_description bdesc_args[] = /* SSE4.2 */ { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI }, - { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR }, - { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT }, - { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT }, - { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 }, + { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR }, + { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT }, + { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT }, + { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 }, /* SSE4A */ { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT }, diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index c8fa9c4064d..657c8ae3eef 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -60,6 +60,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_POPCNT OPTION_ISA_POPCNT #define TARGET_SAHF OPTION_ISA_SAHF #define TARGET_MOVBE OPTION_ISA_MOVBE +#define TARGET_CRC32 OPTION_ISA_CRC32 #define TARGET_AES OPTION_ISA_AES #define TARGET_PCLMUL OPTION_ISA_PCLMUL #define TARGET_CMPXCHG16B OPTION_ISA_CX16 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9f9f4c2685f..c21aa9c679e 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -22642,7 +22642,7 @@ [(match_operand:SI 1 "register_operand" "0") (match_operand:CRC32MODE 2 "nonimmediate_operand" "")] UNSPEC_CRC32))] - "TARGET_SSE4_2" + "TARGET_SSE4_2 || TARGET_CRC32" "crc32\t{%2, %0|%0, %2}" [(set_attr "type" "sselog1") (set_attr "prefix_rep" "1") @@ -22663,7 +22663,7 @@ [(match_operand:DI 1 "register_operand" "0") (match_operand:DI 2 "nonimmediate_operand" "rm")] UNSPEC_CRC32))] - "TARGET_SSE4_2 && TARGET_64BIT" + "TARGET_64BIT && (TARGET_SSE4_2 || TARGET_CRC32)" "crc32q\t{%2, %0|%0, %2}" [(set_attr "type" "sselog1") (set_attr "prefix_rep" "1") diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index e9be268e005..9ec93d8c2a8 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -343,6 +343,10 @@ mmovbe Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) VarExists Save Support code generation of movbe instruction. +mcrc32 +Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) VarExists Save +Support code generation of crc32 instruction. + maes Target Report Mask(ISA_AES) Var(ix86_isa_flags) VarExists Save Support AES built-in functions and code generation diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 4b1ca700a74..f8792f439fb 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -579,7 +579,7 @@ Objective-C and Objective-C++ Dialects}. -mno-wide-multiply -mrtd -malign-double @gol -mpreferred-stack-boundary=@var{num} -mincoming-stack-boundary=@var{num} --mcld -mcx16 -msahf -mmovbe -mrecip @gol +-mcld -mcx16 -msahf -mmovbe -mcrc32 -mrecip @gol -mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol -maes -mpclmul @gol -msse4a -m3dnow -mpopcnt -mabm -msse5 @gol @@ -11559,6 +11559,12 @@ or @code{remainder} built-in functions: see @ref{Other Builtins} for details. This option will enable GCC to use movbe instruction to implement @code{__builtin_bswap32} and @code{__builtin_bswap64}. +@item -mcrc32 +@opindex mcrc32 +This option will enable built-in functions, @code{__builtin_ia32_crc32qi}, +@code{__builtin_ia32_crc32hi}. @code{__builtin_ia32_crc32si} and +@code{__builtin_ia32_crc32di} to generate the crc32 machine instruction. + @item -mrecip @opindex mrecip This option will enable GCC to use RCPSS and RSQRTSS instructions (and their diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8d1a113d6ba..f64d23fddd6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2009-06-11 H.J. Lu + + * gcc.target/i386/crc32-1.c: New. + * gcc.target/i386/crc32-2.c: Likewise. + 2009-06-11 David Daney PR c/39252 diff --git a/gcc/testsuite/gcc.target/i386/crc32-1.c b/gcc/testsuite/gcc.target/i386/crc32-1.c new file mode 100644 index 00000000000..b3ed5b6842a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/crc32-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcrc32" } */ +/* { dg-final { scan-assembler "crc32b\[^\\n\]*eax" } } */ +/* { dg-final { scan-assembler "crc32w\[^\\n\]*eax" } } */ +/* { dg-final { scan-assembler "crc32l\[^\\n\]*eax" } } */ + +unsigned int +crc32b (unsigned int x, unsigned char y) +{ + return __builtin_ia32_crc32qi (x, y); +} + +unsigned int +crc32w (unsigned int x, unsigned short y) +{ + return __builtin_ia32_crc32hi (x, y); +} + +unsigned int +crc32d (unsigned int x, unsigned int y) +{ + return __builtin_ia32_crc32si (x, y); +} diff --git a/gcc/testsuite/gcc.target/i386/crc32-2.c b/gcc/testsuite/gcc.target/i386/crc32-2.c new file mode 100644 index 00000000000..e7af9ab45f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/crc32-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcrc32" } */ +/* { dg-final { scan-assembler "crc32q\[^\\n\]*rax" { target lp64 } } } */ + +unsigned long long +crc32d (unsigned long long x, unsigned long long y) +{ + return __builtin_ia32_crc32di (x, y); +} -- 2.30.2